mpc834x_mds.dts 7.4 KB

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  1. /*
  2. * MPC8349E MDS Device Tree Source
  3. *
  4. * Copyright 2005, 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. / {
  12. model = "MPC8349EMDS";
  13. compatible = "MPC8349EMDS", "MPC834xMDS", "MPC83xxMDS";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. cpus {
  17. #cpus = <1>;
  18. #address-cells = <1>;
  19. #size-cells = <0>;
  20. PowerPC,8349@0 {
  21. device_type = "cpu";
  22. reg = <0>;
  23. d-cache-line-size = <20>; // 32 bytes
  24. i-cache-line-size = <20>; // 32 bytes
  25. d-cache-size = <8000>; // L1, 32K
  26. i-cache-size = <8000>; // L1, 32K
  27. timebase-frequency = <0>; // from bootloader
  28. bus-frequency = <0>; // from bootloader
  29. clock-frequency = <0>; // from bootloader
  30. 32-bit;
  31. };
  32. };
  33. memory {
  34. device_type = "memory";
  35. reg = <00000000 10000000>; // 256MB at 0
  36. };
  37. bcsr@e2400000 {
  38. device_type = "board-control";
  39. reg = <e2400000 8000>;
  40. };
  41. soc8349@e0000000 {
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. #interrupt-cells = <2>;
  45. device_type = "soc";
  46. ranges = <0 e0000000 00100000>;
  47. reg = <e0000000 00000200>;
  48. bus-frequency = <0>;
  49. wdt@200 {
  50. device_type = "watchdog";
  51. compatible = "mpc83xx_wdt";
  52. reg = <200 100>;
  53. };
  54. i2c@3000 {
  55. device_type = "i2c";
  56. compatible = "fsl-i2c";
  57. reg = <3000 100>;
  58. interrupts = <e 8>;
  59. interrupt-parent = < &ipic >;
  60. dfsrr;
  61. };
  62. i2c@3100 {
  63. device_type = "i2c";
  64. compatible = "fsl-i2c";
  65. reg = <3100 100>;
  66. interrupts = <f 8>;
  67. interrupt-parent = < &ipic >;
  68. dfsrr;
  69. };
  70. spi@7000 {
  71. device_type = "spi";
  72. compatible = "mpc83xx_spi";
  73. reg = <7000 1000>;
  74. interrupts = <10 8>;
  75. interrupt-parent = < &ipic >;
  76. mode = <0>;
  77. };
  78. /* phy type (ULPI or SERIAL) are only types supportted for MPH */
  79. /* port = 0 or 1 */
  80. usb@22000 {
  81. device_type = "usb";
  82. compatible = "fsl-usb2-mph";
  83. reg = <22000 1000>;
  84. #address-cells = <1>;
  85. #size-cells = <0>;
  86. interrupt-parent = < &ipic >;
  87. interrupts = <27 8>;
  88. phy_type = "ulpi";
  89. port1;
  90. };
  91. /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
  92. usb@23000 {
  93. device_type = "usb";
  94. compatible = "fsl-usb2-dr";
  95. reg = <23000 1000>;
  96. #address-cells = <1>;
  97. #size-cells = <0>;
  98. interrupt-parent = < &ipic >;
  99. interrupts = <26 8>;
  100. dr_mode = "otg";
  101. phy_type = "ulpi";
  102. };
  103. mdio@24520 {
  104. device_type = "mdio";
  105. compatible = "gianfar";
  106. reg = <24520 20>;
  107. #address-cells = <1>;
  108. #size-cells = <0>;
  109. phy0: ethernet-phy@0 {
  110. interrupt-parent = < &ipic >;
  111. interrupts = <11 8>;
  112. reg = <0>;
  113. device_type = "ethernet-phy";
  114. };
  115. phy1: ethernet-phy@1 {
  116. interrupt-parent = < &ipic >;
  117. interrupts = <12 8>;
  118. reg = <1>;
  119. device_type = "ethernet-phy";
  120. };
  121. };
  122. ethernet@24000 {
  123. device_type = "network";
  124. model = "TSEC";
  125. compatible = "gianfar";
  126. reg = <24000 1000>;
  127. address = [ 00 00 00 00 00 00 ];
  128. local-mac-address = [ 00 00 00 00 00 00 ];
  129. interrupts = <20 8 21 8 22 8>;
  130. interrupt-parent = < &ipic >;
  131. phy-handle = < &phy0 >;
  132. };
  133. ethernet@25000 {
  134. #address-cells = <1>;
  135. #size-cells = <0>;
  136. device_type = "network";
  137. model = "TSEC";
  138. compatible = "gianfar";
  139. reg = <25000 1000>;
  140. address = [ 00 00 00 00 00 00 ];
  141. local-mac-address = [ 00 00 00 00 00 00 ];
  142. interrupts = <23 8 24 8 25 8>;
  143. interrupt-parent = < &ipic >;
  144. phy-handle = < &phy1 >;
  145. };
  146. serial@4500 {
  147. device_type = "serial";
  148. compatible = "ns16550";
  149. reg = <4500 100>;
  150. clock-frequency = <0>;
  151. interrupts = <9 8>;
  152. interrupt-parent = < &ipic >;
  153. };
  154. serial@4600 {
  155. device_type = "serial";
  156. compatible = "ns16550";
  157. reg = <4600 100>;
  158. clock-frequency = <0>;
  159. interrupts = <a 8>;
  160. interrupt-parent = < &ipic >;
  161. };
  162. pci@8500 {
  163. interrupt-map-mask = <f800 0 0 7>;
  164. interrupt-map = <
  165. /* IDSEL 0x11 */
  166. 8800 0 0 1 &ipic 14 8
  167. 8800 0 0 2 &ipic 15 8
  168. 8800 0 0 3 &ipic 16 8
  169. 8800 0 0 4 &ipic 17 8
  170. /* IDSEL 0x12 */
  171. 9000 0 0 1 &ipic 16 8
  172. 9000 0 0 2 &ipic 17 8
  173. 9000 0 0 3 &ipic 14 8
  174. 9000 0 0 4 &ipic 15 8
  175. /* IDSEL 0x13 */
  176. 9800 0 0 1 &ipic 17 8
  177. 9800 0 0 2 &ipic 14 8
  178. 9800 0 0 3 &ipic 15 8
  179. 9800 0 0 4 &ipic 16 8
  180. /* IDSEL 0x15 */
  181. a800 0 0 1 &ipic 14 8
  182. a800 0 0 2 &ipic 15 8
  183. a800 0 0 3 &ipic 16 8
  184. a800 0 0 4 &ipic 17 8
  185. /* IDSEL 0x16 */
  186. b000 0 0 1 &ipic 17 8
  187. b000 0 0 2 &ipic 14 8
  188. b000 0 0 3 &ipic 15 8
  189. b000 0 0 4 &ipic 16 8
  190. /* IDSEL 0x17 */
  191. b800 0 0 1 &ipic 16 8
  192. b800 0 0 2 &ipic 17 8
  193. b800 0 0 3 &ipic 14 8
  194. b800 0 0 4 &ipic 15 8
  195. /* IDSEL 0x18 */
  196. c000 0 0 1 &ipic 15 8
  197. c000 0 0 2 &ipic 16 8
  198. c000 0 0 3 &ipic 17 8
  199. c000 0 0 4 &ipic 14 8>;
  200. interrupt-parent = < &ipic >;
  201. interrupts = <42 8>;
  202. bus-range = <0 0>;
  203. ranges = <02000000 0 a0000000 a0000000 0 10000000
  204. 42000000 0 80000000 80000000 0 10000000
  205. 01000000 0 00000000 e2000000 0 00100000>;
  206. clock-frequency = <3f940aa>;
  207. #interrupt-cells = <1>;
  208. #size-cells = <2>;
  209. #address-cells = <3>;
  210. reg = <8500 100>;
  211. compatible = "83xx";
  212. device_type = "pci";
  213. };
  214. pci@8600 {
  215. interrupt-map-mask = <f800 0 0 7>;
  216. interrupt-map = <
  217. /* IDSEL 0x11 */
  218. 8800 0 0 1 &ipic 14 8
  219. 8800 0 0 2 &ipic 15 8
  220. 8800 0 0 3 &ipic 16 8
  221. 8800 0 0 4 &ipic 17 8
  222. /* IDSEL 0x12 */
  223. 9000 0 0 1 &ipic 16 8
  224. 9000 0 0 2 &ipic 17 8
  225. 9000 0 0 3 &ipic 14 8
  226. 9000 0 0 4 &ipic 15 8
  227. /* IDSEL 0x13 */
  228. 9800 0 0 1 &ipic 17 8
  229. 9800 0 0 2 &ipic 14 8
  230. 9800 0 0 3 &ipic 15 8
  231. 9800 0 0 4 &ipic 16 8
  232. /* IDSEL 0x15 */
  233. a800 0 0 1 &ipic 14 8
  234. a800 0 0 2 &ipic 15 8
  235. a800 0 0 3 &ipic 16 8
  236. a800 0 0 4 &ipic 17 8
  237. /* IDSEL 0x16 */
  238. b000 0 0 1 &ipic 17 8
  239. b000 0 0 2 &ipic 14 8
  240. b000 0 0 3 &ipic 15 8
  241. b000 0 0 4 &ipic 16 8
  242. /* IDSEL 0x17 */
  243. b800 0 0 1 &ipic 16 8
  244. b800 0 0 2 &ipic 17 8
  245. b800 0 0 3 &ipic 14 8
  246. b800 0 0 4 &ipic 15 8
  247. /* IDSEL 0x18 */
  248. c000 0 0 1 &ipic 15 8
  249. c000 0 0 2 &ipic 16 8
  250. c000 0 0 3 &ipic 17 8
  251. c000 0 0 4 &ipic 14 8>;
  252. interrupt-parent = < &ipic >;
  253. interrupts = <42 8>;
  254. bus-range = <0 0>;
  255. ranges = <02000000 0 b0000000 b0000000 0 10000000
  256. 42000000 0 90000000 90000000 0 10000000
  257. 01000000 0 00000000 e2100000 0 00100000>;
  258. clock-frequency = <3f940aa>;
  259. #interrupt-cells = <1>;
  260. #size-cells = <2>;
  261. #address-cells = <3>;
  262. reg = <8600 100>;
  263. compatible = "83xx";
  264. device_type = "pci";
  265. };
  266. /* May need to remove if on a part without crypto engine */
  267. crypto@30000 {
  268. device_type = "crypto";
  269. model = "SEC2";
  270. compatible = "talitos";
  271. reg = <30000 10000>;
  272. interrupts = <b 8>;
  273. interrupt-parent = < &ipic >;
  274. num-channels = <4>;
  275. channel-fifo-len = <18>;
  276. exec-units-mask = <0000007e>;
  277. /* desc mask is for rev2.0,
  278. * we need runtime fixup for >2.0 */
  279. descriptor-types-mask = <01010ebf>;
  280. };
  281. /* IPIC
  282. * interrupts cell = <intr #, sense>
  283. * sense values match linux IORESOURCE_IRQ_* defines:
  284. * sense == 8: Level, low assertion
  285. * sense == 2: Edge, high-to-low change
  286. */
  287. ipic: pic@700 {
  288. interrupt-controller;
  289. #address-cells = <0>;
  290. #interrupt-cells = <2>;
  291. reg = <700 100>;
  292. built-in;
  293. device_type = "ipic";
  294. };
  295. };
  296. };