mpc8349emitx.dts 5.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242
  1. /*
  2. * MPC8349E-mITX Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. / {
  12. model = "MPC8349EMITX";
  13. compatible = "MPC8349EMITX", "MPC834xMITX", "MPC83xxMITX";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. cpus {
  17. #cpus = <1>;
  18. #address-cells = <1>;
  19. #size-cells = <0>;
  20. PowerPC,8349@0 {
  21. device_type = "cpu";
  22. reg = <0>;
  23. d-cache-line-size = <20>;
  24. i-cache-line-size = <20>;
  25. d-cache-size = <8000>;
  26. i-cache-size = <8000>;
  27. timebase-frequency = <0>; // from bootloader
  28. bus-frequency = <0>; // from bootloader
  29. clock-frequency = <0>; // from bootloader
  30. 32-bit;
  31. };
  32. };
  33. memory {
  34. device_type = "memory";
  35. reg = <00000000 10000000>;
  36. };
  37. soc8349@e0000000 {
  38. #address-cells = <1>;
  39. #size-cells = <1>;
  40. #interrupt-cells = <2>;
  41. device_type = "soc";
  42. ranges = <0 e0000000 00100000>;
  43. reg = <e0000000 00000200>;
  44. bus-frequency = <0>; // from bootloader
  45. wdt@200 {
  46. device_type = "watchdog";
  47. compatible = "mpc83xx_wdt";
  48. reg = <200 100>;
  49. };
  50. i2c@3000 {
  51. device_type = "i2c";
  52. compatible = "fsl-i2c";
  53. reg = <3000 100>;
  54. interrupts = <e 8>;
  55. interrupt-parent = < &ipic >;
  56. dfsrr;
  57. };
  58. i2c@3100 {
  59. device_type = "i2c";
  60. compatible = "fsl-i2c";
  61. reg = <3100 100>;
  62. interrupts = <f 8>;
  63. interrupt-parent = < &ipic >;
  64. dfsrr;
  65. };
  66. spi@7000 {
  67. device_type = "spi";
  68. compatible = "mpc83xx_spi";
  69. reg = <7000 1000>;
  70. interrupts = <10 8>;
  71. interrupt-parent = < &ipic >;
  72. mode = <0>;
  73. };
  74. usb@22000 {
  75. device_type = "usb";
  76. compatible = "fsl-usb2-mph";
  77. reg = <22000 1000>;
  78. #address-cells = <1>;
  79. #size-cells = <0>;
  80. interrupt-parent = < &ipic >;
  81. interrupts = <27 8>;
  82. phy_type = "ulpi";
  83. port1;
  84. };
  85. usb@23000 {
  86. device_type = "usb";
  87. compatible = "fsl-usb2-dr";
  88. reg = <23000 1000>;
  89. #address-cells = <1>;
  90. #size-cells = <0>;
  91. interrupt-parent = < &ipic >;
  92. interrupts = <26 8>;
  93. phy_type = "ulpi";
  94. };
  95. mdio@24520 {
  96. device_type = "mdio";
  97. compatible = "gianfar";
  98. reg = <24520 20>;
  99. #address-cells = <1>;
  100. #size-cells = <0>;
  101. /* Vitesse 8201 */
  102. phy1c: ethernet-phy@1c {
  103. interrupt-parent = < &ipic >;
  104. interrupts = <12 8>;
  105. reg = <1c>;
  106. device_type = "ethernet-phy";
  107. };
  108. /* Vitesse 7385 */
  109. phy1f: ethernet-phy@1f {
  110. interrupt-parent = < &ipic >;
  111. interrupts = <12 8>;
  112. reg = <1f>;
  113. device_type = "ethernet-phy";
  114. };
  115. };
  116. ethernet@24000 {
  117. device_type = "network";
  118. model = "TSEC";
  119. compatible = "gianfar";
  120. reg = <24000 1000>;
  121. address = [ 00 00 00 00 00 00 ];
  122. local-mac-address = [ 00 00 00 00 00 00 ];
  123. interrupts = <20 8 21 8 22 8>;
  124. interrupt-parent = < &ipic >;
  125. phy-handle = < &phy1c >;
  126. };
  127. ethernet@25000 {
  128. #address-cells = <1>;
  129. #size-cells = <0>;
  130. device_type = "network";
  131. model = "TSEC";
  132. compatible = "gianfar";
  133. reg = <25000 1000>;
  134. address = [ 00 00 00 00 00 00 ];
  135. local-mac-address = [ 00 00 00 00 00 00 ];
  136. interrupts = <23 8 24 8 25 8>;
  137. interrupt-parent = < &ipic >;
  138. phy-handle = < &phy1f >;
  139. };
  140. serial@4500 {
  141. device_type = "serial";
  142. compatible = "ns16550";
  143. reg = <4500 100>;
  144. clock-frequency = <0>; // from bootloader
  145. interrupts = <9 8>;
  146. interrupt-parent = < &ipic >;
  147. };
  148. serial@4600 {
  149. device_type = "serial";
  150. compatible = "ns16550";
  151. reg = <4600 100>;
  152. clock-frequency = <0>; // from bootloader
  153. interrupts = <a 8>;
  154. interrupt-parent = < &ipic >;
  155. };
  156. pci@8500 {
  157. interrupt-map-mask = <f800 0 0 7>;
  158. interrupt-map = <
  159. /* IDSEL 0x10 - SATA */
  160. 8000 0 0 1 &ipic 16 8 /* SATA_INTA */
  161. >;
  162. interrupt-parent = < &ipic >;
  163. interrupts = <42 8>;
  164. bus-range = <0 0>;
  165. ranges = <42000000 0 80000000 80000000 0 10000000
  166. 02000000 0 90000000 90000000 0 10000000
  167. 01000000 0 00000000 e2000000 0 01000000>;
  168. clock-frequency = <3f940aa>;
  169. #interrupt-cells = <1>;
  170. #size-cells = <2>;
  171. #address-cells = <3>;
  172. reg = <8500 100>;
  173. compatible = "83xx";
  174. device_type = "pci";
  175. };
  176. pci@8600 {
  177. interrupt-map-mask = <f800 0 0 7>;
  178. interrupt-map = <
  179. /* IDSEL 0x0E - MiniPCI Slot */
  180. 7000 0 0 1 &ipic 15 8 /* PCI_INTA */
  181. /* IDSEL 0x0F - PCI Slot */
  182. 7800 0 0 1 &ipic 14 8 /* PCI_INTA */
  183. 7800 0 0 2 &ipic 15 8 /* PCI_INTB */
  184. >;
  185. interrupt-parent = < &ipic >;
  186. interrupts = <43 8>;
  187. bus-range = <1 1>;
  188. ranges = <42000000 0 a0000000 a0000000 0 10000000
  189. 02000000 0 b0000000 b0000000 0 10000000
  190. 01000000 0 00000000 e3000000 0 01000000>;
  191. clock-frequency = <3f940aa>;
  192. #interrupt-cells = <1>;
  193. #size-cells = <2>;
  194. #address-cells = <3>;
  195. reg = <8600 100>;
  196. compatible = "83xx";
  197. device_type = "pci";
  198. };
  199. crypto@30000 {
  200. device_type = "crypto";
  201. model = "SEC2";
  202. compatible = "talitos";
  203. reg = <30000 10000>;
  204. interrupts = <b 8>;
  205. interrupt-parent = < &ipic >;
  206. num-channels = <4>;
  207. channel-fifo-len = <18>;
  208. exec-units-mask = <0000007e>;
  209. descriptor-types-mask = <01010ebf>;
  210. };
  211. ipic: pic@700 {
  212. interrupt-controller;
  213. #address-cells = <0>;
  214. #interrupt-cells = <2>;
  215. reg = <700 100>;
  216. built-in;
  217. device_type = "ipic";
  218. };
  219. };
  220. };