cx23885-cards.c 21 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/init.h>
  22. #include <linux/module.h>
  23. #include <linux/pci.h>
  24. #include <linux/delay.h>
  25. #include <media/cx25840.h>
  26. #include "cx23885.h"
  27. #include "tuner-xc2028.h"
  28. #include "netup-init.h"
  29. /* ------------------------------------------------------------------ */
  30. /* board config info */
  31. struct cx23885_board cx23885_boards[] = {
  32. [CX23885_BOARD_UNKNOWN] = {
  33. .name = "UNKNOWN/GENERIC",
  34. /* Ensure safe default for unknown boards */
  35. .clk_freq = 0,
  36. .input = {{
  37. .type = CX23885_VMUX_COMPOSITE1,
  38. .vmux = 0,
  39. }, {
  40. .type = CX23885_VMUX_COMPOSITE2,
  41. .vmux = 1,
  42. }, {
  43. .type = CX23885_VMUX_COMPOSITE3,
  44. .vmux = 2,
  45. }, {
  46. .type = CX23885_VMUX_COMPOSITE4,
  47. .vmux = 3,
  48. } },
  49. },
  50. [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
  51. .name = "Hauppauge WinTV-HVR1800lp",
  52. .portc = CX23885_MPEG_DVB,
  53. .input = {{
  54. .type = CX23885_VMUX_TELEVISION,
  55. .vmux = 0,
  56. .gpio0 = 0xff00,
  57. }, {
  58. .type = CX23885_VMUX_DEBUG,
  59. .vmux = 0,
  60. .gpio0 = 0xff01,
  61. }, {
  62. .type = CX23885_VMUX_COMPOSITE1,
  63. .vmux = 1,
  64. .gpio0 = 0xff02,
  65. }, {
  66. .type = CX23885_VMUX_SVIDEO,
  67. .vmux = 2,
  68. .gpio0 = 0xff02,
  69. } },
  70. },
  71. [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
  72. .name = "Hauppauge WinTV-HVR1800",
  73. .porta = CX23885_ANALOG_VIDEO,
  74. .portb = CX23885_MPEG_ENCODER,
  75. .portc = CX23885_MPEG_DVB,
  76. .tuner_type = TUNER_PHILIPS_TDA8290,
  77. .tuner_addr = 0x42, /* 0x84 >> 1 */
  78. .input = {{
  79. .type = CX23885_VMUX_TELEVISION,
  80. .vmux = CX25840_VIN7_CH3 |
  81. CX25840_VIN5_CH2 |
  82. CX25840_VIN2_CH1,
  83. .gpio0 = 0,
  84. }, {
  85. .type = CX23885_VMUX_COMPOSITE1,
  86. .vmux = CX25840_VIN7_CH3 |
  87. CX25840_VIN4_CH2 |
  88. CX25840_VIN6_CH1,
  89. .gpio0 = 0,
  90. }, {
  91. .type = CX23885_VMUX_SVIDEO,
  92. .vmux = CX25840_VIN7_CH3 |
  93. CX25840_VIN4_CH2 |
  94. CX25840_VIN8_CH1 |
  95. CX25840_SVIDEO_ON,
  96. .gpio0 = 0,
  97. } },
  98. },
  99. [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
  100. .name = "Hauppauge WinTV-HVR1250",
  101. .portc = CX23885_MPEG_DVB,
  102. .input = {{
  103. .type = CX23885_VMUX_TELEVISION,
  104. .vmux = 0,
  105. .gpio0 = 0xff00,
  106. }, {
  107. .type = CX23885_VMUX_DEBUG,
  108. .vmux = 0,
  109. .gpio0 = 0xff01,
  110. }, {
  111. .type = CX23885_VMUX_COMPOSITE1,
  112. .vmux = 1,
  113. .gpio0 = 0xff02,
  114. }, {
  115. .type = CX23885_VMUX_SVIDEO,
  116. .vmux = 2,
  117. .gpio0 = 0xff02,
  118. } },
  119. },
  120. [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
  121. .name = "DViCO FusionHDTV5 Express",
  122. .portb = CX23885_MPEG_DVB,
  123. },
  124. [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
  125. .name = "Hauppauge WinTV-HVR1500Q",
  126. .portc = CX23885_MPEG_DVB,
  127. },
  128. [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
  129. .name = "Hauppauge WinTV-HVR1500",
  130. .portc = CX23885_MPEG_DVB,
  131. },
  132. [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
  133. .name = "Hauppauge WinTV-HVR1200",
  134. .portc = CX23885_MPEG_DVB,
  135. },
  136. [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
  137. .name = "Hauppauge WinTV-HVR1700",
  138. .portc = CX23885_MPEG_DVB,
  139. },
  140. [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
  141. .name = "Hauppauge WinTV-HVR1400",
  142. .portc = CX23885_MPEG_DVB,
  143. },
  144. [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
  145. .name = "DViCO FusionHDTV7 Dual Express",
  146. .portb = CX23885_MPEG_DVB,
  147. .portc = CX23885_MPEG_DVB,
  148. },
  149. [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
  150. .name = "DViCO FusionHDTV DVB-T Dual Express",
  151. .portb = CX23885_MPEG_DVB,
  152. .portc = CX23885_MPEG_DVB,
  153. },
  154. [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
  155. .name = "Leadtek Winfast PxDVR3200 H",
  156. .portc = CX23885_MPEG_DVB,
  157. },
  158. [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
  159. .name = "Compro VideoMate E650F",
  160. .portc = CX23885_MPEG_DVB,
  161. },
  162. [CX23885_BOARD_TBS_6920] = {
  163. .name = "TurboSight TBS 6920",
  164. .portb = CX23885_MPEG_DVB,
  165. },
  166. [CX23885_BOARD_TEVII_S470] = {
  167. .name = "TeVii S470",
  168. .portb = CX23885_MPEG_DVB,
  169. },
  170. [CX23885_BOARD_DVBWORLD_2005] = {
  171. .name = "DVBWorld DVB-S2 2005",
  172. .portb = CX23885_MPEG_DVB,
  173. },
  174. [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
  175. .cimax = 1,
  176. .name = "NetUP Dual DVB-S2 CI",
  177. .portb = CX23885_MPEG_DVB,
  178. .portc = CX23885_MPEG_DVB,
  179. },
  180. };
  181. const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
  182. /* ------------------------------------------------------------------ */
  183. /* PCI subsystem IDs */
  184. struct cx23885_subid cx23885_subids[] = {
  185. {
  186. .subvendor = 0x0070,
  187. .subdevice = 0x3400,
  188. .card = CX23885_BOARD_UNKNOWN,
  189. }, {
  190. .subvendor = 0x0070,
  191. .subdevice = 0x7600,
  192. .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
  193. }, {
  194. .subvendor = 0x0070,
  195. .subdevice = 0x7800,
  196. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  197. }, {
  198. .subvendor = 0x0070,
  199. .subdevice = 0x7801,
  200. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  201. }, {
  202. .subvendor = 0x0070,
  203. .subdevice = 0x7809,
  204. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  205. }, {
  206. .subvendor = 0x0070,
  207. .subdevice = 0x7911,
  208. .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
  209. }, {
  210. .subvendor = 0x18ac,
  211. .subdevice = 0xd500,
  212. .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
  213. }, {
  214. .subvendor = 0x0070,
  215. .subdevice = 0x7790,
  216. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  217. }, {
  218. .subvendor = 0x0070,
  219. .subdevice = 0x7797,
  220. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  221. }, {
  222. .subvendor = 0x0070,
  223. .subdevice = 0x7710,
  224. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  225. }, {
  226. .subvendor = 0x0070,
  227. .subdevice = 0x7717,
  228. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  229. }, {
  230. .subvendor = 0x0070,
  231. .subdevice = 0x71d1,
  232. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  233. }, {
  234. .subvendor = 0x0070,
  235. .subdevice = 0x71d3,
  236. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  237. }, {
  238. .subvendor = 0x0070,
  239. .subdevice = 0x8101,
  240. .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
  241. }, {
  242. .subvendor = 0x0070,
  243. .subdevice = 0x8010,
  244. .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
  245. }, {
  246. .subvendor = 0x18ac,
  247. .subdevice = 0xd618,
  248. .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
  249. }, {
  250. .subvendor = 0x18ac,
  251. .subdevice = 0xdb78,
  252. .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
  253. }, {
  254. .subvendor = 0x107d,
  255. .subdevice = 0x6681,
  256. .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
  257. }, {
  258. .subvendor = 0x185b,
  259. .subdevice = 0xe800,
  260. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
  261. }, {
  262. .subvendor = 0x6920,
  263. .subdevice = 0x8888,
  264. .card = CX23885_BOARD_TBS_6920,
  265. }, {
  266. .subvendor = 0xd470,
  267. .subdevice = 0x9022,
  268. .card = CX23885_BOARD_TEVII_S470,
  269. }, {
  270. .subvendor = 0x0001,
  271. .subdevice = 0x2005,
  272. .card = CX23885_BOARD_DVBWORLD_2005,
  273. }, {
  274. .subvendor = 0x1b55,
  275. .subdevice = 0x2a2c,
  276. .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
  277. },
  278. };
  279. const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
  280. void cx23885_card_list(struct cx23885_dev *dev)
  281. {
  282. int i;
  283. if (0 == dev->pci->subsystem_vendor &&
  284. 0 == dev->pci->subsystem_device) {
  285. printk(KERN_INFO
  286. "%s: Board has no valid PCIe Subsystem ID and can't\n"
  287. "%s: be autodetected. Pass card=<n> insmod option\n"
  288. "%s: to workaround that. Redirect complaints to the\n"
  289. "%s: vendor of the TV card. Best regards,\n"
  290. "%s: -- tux\n",
  291. dev->name, dev->name, dev->name, dev->name, dev->name);
  292. } else {
  293. printk(KERN_INFO
  294. "%s: Your board isn't known (yet) to the driver.\n"
  295. "%s: Try to pick one of the existing card configs via\n"
  296. "%s: card=<n> insmod option. Updating to the latest\n"
  297. "%s: version might help as well.\n",
  298. dev->name, dev->name, dev->name, dev->name);
  299. }
  300. printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
  301. dev->name);
  302. for (i = 0; i < cx23885_bcount; i++)
  303. printk(KERN_INFO "%s: card=%d -> %s\n",
  304. dev->name, i, cx23885_boards[i].name);
  305. }
  306. static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
  307. {
  308. struct tveeprom tv;
  309. tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
  310. eeprom_data);
  311. /* Make sure we support the board model */
  312. switch (tv.model) {
  313. case 71009:
  314. /* WinTV-HVR1200 (PCIe, Retail, full height)
  315. * DVB-T and basic analog */
  316. case 71359:
  317. /* WinTV-HVR1200 (PCIe, OEM, half height)
  318. * DVB-T and basic analog */
  319. case 71439:
  320. /* WinTV-HVR1200 (PCIe, OEM, half height)
  321. * DVB-T and basic analog */
  322. case 71449:
  323. /* WinTV-HVR1200 (PCIe, OEM, full height)
  324. * DVB-T and basic analog */
  325. case 71939:
  326. /* WinTV-HVR1200 (PCIe, OEM, half height)
  327. * DVB-T and basic analog */
  328. case 71949:
  329. /* WinTV-HVR1200 (PCIe, OEM, full height)
  330. * DVB-T and basic analog */
  331. case 71959:
  332. /* WinTV-HVR1200 (PCIe, OEM, full height)
  333. * DVB-T and basic analog */
  334. case 71979:
  335. /* WinTV-HVR1200 (PCIe, OEM, half height)
  336. * DVB-T and basic analog */
  337. case 71999:
  338. /* WinTV-HVR1200 (PCIe, OEM, full height)
  339. * DVB-T and basic analog */
  340. case 76601:
  341. /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
  342. channel ATSC and MPEG2 HW Encoder */
  343. case 77001:
  344. /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
  345. and Basic analog */
  346. case 77011:
  347. /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
  348. and Basic analog */
  349. case 77041:
  350. /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
  351. and Basic analog */
  352. case 77051:
  353. /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
  354. and Basic analog */
  355. case 78011:
  356. /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
  357. Dual channel ATSC and MPEG2 HW Encoder */
  358. case 78501:
  359. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  360. Dual channel ATSC and MPEG2 HW Encoder */
  361. case 78521:
  362. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  363. Dual channel ATSC and MPEG2 HW Encoder */
  364. case 78531:
  365. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
  366. Dual channel ATSC and MPEG2 HW Encoder */
  367. case 78631:
  368. /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
  369. Dual channel ATSC and MPEG2 HW Encoder */
  370. case 79001:
  371. /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
  372. ATSC and Basic analog */
  373. case 79101:
  374. /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
  375. ATSC and Basic analog */
  376. case 79561:
  377. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  378. ATSC and Basic analog */
  379. case 79571:
  380. /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
  381. ATSC and Basic analog */
  382. case 79671:
  383. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  384. ATSC and Basic analog */
  385. case 80019:
  386. /* WinTV-HVR1400 (Express Card, Retail, IR,
  387. * DVB-T and Basic analog */
  388. case 81509:
  389. /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
  390. * DVB-T and MPEG2 HW Encoder */
  391. case 81519:
  392. /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
  393. * DVB-T and MPEG2 HW Encoder */
  394. break;
  395. default:
  396. printk(KERN_WARNING "%s: warning: unknown hauppauge model #%d\n",
  397. dev->name, tv.model);
  398. break;
  399. }
  400. printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
  401. dev->name, tv.model);
  402. }
  403. int cx23885_tuner_callback(void *priv, int component, int command, int arg)
  404. {
  405. struct cx23885_tsport *port = priv;
  406. struct cx23885_dev *dev = port->dev;
  407. u32 bitmask = 0;
  408. if (command == XC2028_RESET_CLK)
  409. return 0;
  410. if (command != 0) {
  411. printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
  412. __func__, command);
  413. return -EINVAL;
  414. }
  415. switch (dev->board) {
  416. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  417. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  418. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  419. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  420. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  421. /* Tuner Reset Command */
  422. bitmask = 0x04;
  423. break;
  424. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  425. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  426. /* Two identical tuners on two different i2c buses,
  427. * we need to reset the correct gpio. */
  428. if (port->nr == 0)
  429. bitmask = 0x01;
  430. else if (port->nr == 1)
  431. bitmask = 0x04;
  432. break;
  433. }
  434. if (bitmask) {
  435. /* Drive the tuner into reset and back out */
  436. cx_clear(GP0_IO, bitmask);
  437. mdelay(200);
  438. cx_set(GP0_IO, bitmask);
  439. }
  440. return 0;
  441. }
  442. void cx23885_gpio_setup(struct cx23885_dev *dev)
  443. {
  444. switch (dev->board) {
  445. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  446. /* GPIO-0 cx24227 demodulator reset */
  447. cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
  448. break;
  449. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  450. /* GPIO-0 cx24227 demodulator */
  451. /* GPIO-2 xc3028 tuner */
  452. /* Put the parts into reset */
  453. cx_set(GP0_IO, 0x00050000);
  454. cx_clear(GP0_IO, 0x00000005);
  455. msleep(5);
  456. /* Bring the parts out of reset */
  457. cx_set(GP0_IO, 0x00050005);
  458. break;
  459. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  460. /* GPIO-0 cx24227 demodulator reset */
  461. /* GPIO-2 xc5000 tuner reset */
  462. cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
  463. break;
  464. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  465. /* GPIO-0 656_CLK */
  466. /* GPIO-1 656_D0 */
  467. /* GPIO-2 8295A Reset */
  468. /* GPIO-3-10 cx23417 data0-7 */
  469. /* GPIO-11-14 cx23417 addr0-3 */
  470. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  471. /* GPIO-19 IR_RX */
  472. /* CX23417 GPIO's */
  473. /* EIO15 Zilog Reset */
  474. /* EIO14 S5H1409/CX24227 Reset */
  475. /* Force the TDA8295A into reset and back */
  476. cx_set(GP0_IO, 0x00040004);
  477. mdelay(20);
  478. cx_clear(GP0_IO, 0x00000004);
  479. mdelay(20);
  480. cx_set(GP0_IO, 0x00040004);
  481. mdelay(20);
  482. break;
  483. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  484. /* GPIO-0 tda10048 demodulator reset */
  485. /* GPIO-2 tda18271 tuner reset */
  486. /* Put the parts into reset and back */
  487. cx_set(GP0_IO, 0x00050000);
  488. mdelay(20);
  489. cx_clear(GP0_IO, 0x00000005);
  490. mdelay(20);
  491. cx_set(GP0_IO, 0x00050005);
  492. break;
  493. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  494. /* GPIO-0 TDA10048 demodulator reset */
  495. /* GPIO-2 TDA8295A Reset */
  496. /* GPIO-3-10 cx23417 data0-7 */
  497. /* GPIO-11-14 cx23417 addr0-3 */
  498. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  499. /* The following GPIO's are on the interna AVCore (cx25840) */
  500. /* GPIO-19 IR_RX */
  501. /* GPIO-20 IR_TX 416/DVBT Select */
  502. /* GPIO-21 IIS DAT */
  503. /* GPIO-22 IIS WCLK */
  504. /* GPIO-23 IIS BCLK */
  505. /* Put the parts into reset and back */
  506. cx_set(GP0_IO, 0x00050000);
  507. mdelay(20);
  508. cx_clear(GP0_IO, 0x00000005);
  509. mdelay(20);
  510. cx_set(GP0_IO, 0x00050005);
  511. break;
  512. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  513. /* GPIO-0 Dibcom7000p demodulator reset */
  514. /* GPIO-2 xc3028L tuner reset */
  515. /* GPIO-13 LED */
  516. /* Put the parts into reset and back */
  517. cx_set(GP0_IO, 0x00050000);
  518. mdelay(20);
  519. cx_clear(GP0_IO, 0x00000005);
  520. mdelay(20);
  521. cx_set(GP0_IO, 0x00050005);
  522. break;
  523. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  524. /* GPIO-0 xc5000 tuner reset i2c bus 0 */
  525. /* GPIO-1 s5h1409 demod reset i2c bus 0 */
  526. /* GPIO-2 xc5000 tuner reset i2c bus 1 */
  527. /* GPIO-3 s5h1409 demod reset i2c bus 0 */
  528. /* Put the parts into reset and back */
  529. cx_set(GP0_IO, 0x000f0000);
  530. mdelay(20);
  531. cx_clear(GP0_IO, 0x0000000f);
  532. mdelay(20);
  533. cx_set(GP0_IO, 0x000f000f);
  534. break;
  535. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  536. /* GPIO-0 portb xc3028 reset */
  537. /* GPIO-1 portb zl10353 reset */
  538. /* GPIO-2 portc xc3028 reset */
  539. /* GPIO-3 portc zl10353 reset */
  540. /* Put the parts into reset and back */
  541. cx_set(GP0_IO, 0x000f0000);
  542. mdelay(20);
  543. cx_clear(GP0_IO, 0x0000000f);
  544. mdelay(20);
  545. cx_set(GP0_IO, 0x000f000f);
  546. break;
  547. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  548. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  549. /* GPIO-2 xc3028 tuner reset */
  550. /* The following GPIO's are on the internal AVCore (cx25840) */
  551. /* GPIO-? zl10353 demod reset */
  552. /* Put the parts into reset and back */
  553. cx_set(GP0_IO, 0x00040000);
  554. mdelay(20);
  555. cx_clear(GP0_IO, 0x00000004);
  556. mdelay(20);
  557. cx_set(GP0_IO, 0x00040004);
  558. break;
  559. case CX23885_BOARD_TBS_6920:
  560. case CX23885_BOARD_TEVII_S470:
  561. cx_write(MC417_CTL, 0x00000036);
  562. cx_write(MC417_OEN, 0x00001000);
  563. cx_write(MC417_RWD, 0x00001800);
  564. break;
  565. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  566. /* GPIO-0 INTA from CiMax1
  567. GPIO-1 INTB from CiMax2
  568. GPIO-2 reset chips
  569. GPIO-3 to GPIO-10 data/addr for CA
  570. GPIO-11 ~CS0 to CiMax1
  571. GPIO-12 ~CS1 to CiMax2
  572. GPIO-13 ADL0 load LSB addr
  573. GPIO-14 ADL1 load MSB addr
  574. GPIO-15 ~RDY from CiMax
  575. GPIO-17 ~RD to CiMax
  576. GPIO-18 ~WR to CiMax
  577. */
  578. cx_set(GP0_IO, 0x00040000); /* GPIO as out */
  579. /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
  580. cx_clear(GP0_IO, 0x00030004);
  581. mdelay(100);/* reset delay */
  582. cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
  583. cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
  584. /* GPIO-15 IN as ~ACK, rest as OUT */
  585. cx_write(MC417_OEN, 0x00001000);
  586. /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
  587. cx_write(MC417_RWD, 0x0000c300);
  588. /* enable irq */
  589. cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
  590. break;
  591. }
  592. }
  593. int cx23885_ir_init(struct cx23885_dev *dev)
  594. {
  595. switch (dev->board) {
  596. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  597. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  598. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  599. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  600. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  601. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  602. /* FIXME: Implement me */
  603. break;
  604. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  605. request_module("ir-kbd-i2c");
  606. break;
  607. }
  608. return 0;
  609. }
  610. void cx23885_card_setup(struct cx23885_dev *dev)
  611. {
  612. struct cx23885_tsport *ts1 = &dev->ts1;
  613. struct cx23885_tsport *ts2 = &dev->ts2;
  614. static u8 eeprom[256];
  615. if (dev->i2c_bus[0].i2c_rc == 0) {
  616. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  617. tveeprom_read(&dev->i2c_bus[0].i2c_client,
  618. eeprom, sizeof(eeprom));
  619. }
  620. switch (dev->board) {
  621. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  622. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  623. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  624. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  625. if (dev->i2c_bus[0].i2c_rc == 0)
  626. hauppauge_eeprom(dev, eeprom+0x80);
  627. break;
  628. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  629. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  630. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  631. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  632. if (dev->i2c_bus[0].i2c_rc == 0)
  633. hauppauge_eeprom(dev, eeprom+0xc0);
  634. break;
  635. }
  636. switch (dev->board) {
  637. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  638. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  639. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  640. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  641. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  642. /* break omitted intentionally */
  643. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  644. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  645. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  646. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  647. break;
  648. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  649. /* Defaults for VID B - Analog encoder */
  650. /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
  651. ts1->gen_ctrl_val = 0x10e;
  652. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  653. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  654. /* APB_TSVALERR_POL (active low)*/
  655. ts1->vld_misc_val = 0x2000;
  656. ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
  657. /* Defaults for VID C */
  658. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  659. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  660. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  661. break;
  662. case CX23885_BOARD_TEVII_S470:
  663. case CX23885_BOARD_TBS_6920:
  664. case CX23885_BOARD_DVBWORLD_2005:
  665. ts1->gen_ctrl_val = 0x5; /* Parallel */
  666. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  667. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  668. break;
  669. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  670. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  671. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  672. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  673. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  674. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  675. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  676. break;
  677. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  678. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  679. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  680. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  681. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  682. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  683. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  684. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  685. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  686. default:
  687. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  688. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  689. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  690. }
  691. /* Certain boards support analog, or require the avcore to be
  692. * loaded, ensure this happens.
  693. */
  694. switch (dev->board) {
  695. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  696. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  697. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  698. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  699. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  700. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  701. dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->i2c_bus[2].i2c_adap,
  702. "cx25840", "cx25840", 0x88 >> 1);
  703. v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
  704. break;
  705. }
  706. /* AUX-PLL 27MHz CLK */
  707. switch (dev->board) {
  708. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  709. netup_initialize(dev);
  710. break;
  711. }
  712. }
  713. /* ------------------------------------------------------------------ */