iwl-agn.c 86 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/mac80211.h>
  42. #include <asm/div64.h>
  43. #define DRV_NAME "iwlagn"
  44. #include "iwl-eeprom.h"
  45. #include "iwl-dev.h"
  46. #include "iwl-core.h"
  47. #include "iwl-io.h"
  48. #include "iwl-helpers.h"
  49. #include "iwl-sta.h"
  50. #include "iwl-calib.h"
  51. /******************************************************************************
  52. *
  53. * module boiler plate
  54. *
  55. ******************************************************************************/
  56. /*
  57. * module name, copyright, version, etc.
  58. */
  59. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  60. #ifdef CONFIG_IWLWIFI_DEBUG
  61. #define VD "d"
  62. #else
  63. #define VD
  64. #endif
  65. #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
  66. #define VS "s"
  67. #else
  68. #define VS
  69. #endif
  70. #define DRV_VERSION IWLWIFI_VERSION VD VS
  71. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  72. MODULE_VERSION(DRV_VERSION);
  73. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  74. MODULE_LICENSE("GPL");
  75. MODULE_ALIAS("iwl4965");
  76. /*************** STATION TABLE MANAGEMENT ****
  77. * mac80211 should be examined to determine if sta_info is duplicating
  78. * the functionality provided here
  79. */
  80. /**************************************************************/
  81. /**
  82. * iwl_commit_rxon - commit staging_rxon to hardware
  83. *
  84. * The RXON command in staging_rxon is committed to the hardware and
  85. * the active_rxon structure is updated with the new data. This
  86. * function correctly transitions out of the RXON_ASSOC_MSK state if
  87. * a HW tune is required based on the RXON structure changes.
  88. */
  89. int iwl_commit_rxon(struct iwl_priv *priv)
  90. {
  91. /* cast away the const for active_rxon in this function */
  92. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  93. int ret;
  94. bool new_assoc =
  95. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  96. if (!iwl_is_alive(priv))
  97. return -EBUSY;
  98. /* always get timestamp with Rx frame */
  99. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  100. /* allow CTS-to-self if possible. this is relevant only for
  101. * 5000, but will not damage 4965 */
  102. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  103. ret = iwl_check_rxon_cmd(priv);
  104. if (ret) {
  105. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  106. return -EINVAL;
  107. }
  108. /* If we don't need to send a full RXON, we can use
  109. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  110. * and other flags for the current radio configuration. */
  111. if (!iwl_full_rxon_required(priv)) {
  112. ret = iwl_send_rxon_assoc(priv);
  113. if (ret) {
  114. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  115. return ret;
  116. }
  117. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  118. return 0;
  119. }
  120. /* station table will be cleared */
  121. priv->assoc_station_added = 0;
  122. /* If we are currently associated and the new config requires
  123. * an RXON_ASSOC and the new config wants the associated mask enabled,
  124. * we must clear the associated from the active configuration
  125. * before we apply the new config */
  126. if (iwl_is_associated(priv) && new_assoc) {
  127. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  128. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  129. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  130. sizeof(struct iwl_rxon_cmd),
  131. &priv->active_rxon);
  132. /* If the mask clearing failed then we set
  133. * active_rxon back to what it was previously */
  134. if (ret) {
  135. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  136. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  137. return ret;
  138. }
  139. }
  140. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  141. "* with%s RXON_FILTER_ASSOC_MSK\n"
  142. "* channel = %d\n"
  143. "* bssid = %pM\n",
  144. (new_assoc ? "" : "out"),
  145. le16_to_cpu(priv->staging_rxon.channel),
  146. priv->staging_rxon.bssid_addr);
  147. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  148. /* Apply the new configuration
  149. * RXON unassoc clears the station table in uCode, send it before
  150. * we add the bcast station. If assoc bit is set, we will send RXON
  151. * after having added the bcast and bssid station.
  152. */
  153. if (!new_assoc) {
  154. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  155. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  156. if (ret) {
  157. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  158. return ret;
  159. }
  160. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  161. }
  162. iwl_clear_stations_table(priv);
  163. priv->start_calib = 0;
  164. /* Add the broadcast address so we can send broadcast frames */
  165. if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
  166. IWL_INVALID_STATION) {
  167. IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
  168. return -EIO;
  169. }
  170. /* If we have set the ASSOC_MSK and we are in BSS mode then
  171. * add the IWL_AP_ID to the station rate table */
  172. if (new_assoc) {
  173. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  174. ret = iwl_rxon_add_station(priv,
  175. priv->active_rxon.bssid_addr, 1);
  176. if (ret == IWL_INVALID_STATION) {
  177. IWL_ERR(priv,
  178. "Error adding AP address for TX.\n");
  179. return -EIO;
  180. }
  181. priv->assoc_station_added = 1;
  182. if (priv->default_wep_key &&
  183. iwl_send_static_wepkey_cmd(priv, 0))
  184. IWL_ERR(priv,
  185. "Could not send WEP static key.\n");
  186. }
  187. /* Apply the new configuration
  188. * RXON assoc doesn't clear the station table in uCode,
  189. */
  190. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  191. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  192. if (ret) {
  193. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  194. return ret;
  195. }
  196. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  197. }
  198. iwl_init_sensitivity(priv);
  199. /* If we issue a new RXON command which required a tune then we must
  200. * send a new TXPOWER command or we won't be able to Tx any frames */
  201. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  202. if (ret) {
  203. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  204. return ret;
  205. }
  206. return 0;
  207. }
  208. void iwl_update_chain_flags(struct iwl_priv *priv)
  209. {
  210. if (priv->cfg->ops->hcmd->set_rxon_chain)
  211. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  212. iwlcore_commit_rxon(priv);
  213. }
  214. static void iwl_clear_free_frames(struct iwl_priv *priv)
  215. {
  216. struct list_head *element;
  217. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  218. priv->frames_count);
  219. while (!list_empty(&priv->free_frames)) {
  220. element = priv->free_frames.next;
  221. list_del(element);
  222. kfree(list_entry(element, struct iwl_frame, list));
  223. priv->frames_count--;
  224. }
  225. if (priv->frames_count) {
  226. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  227. priv->frames_count);
  228. priv->frames_count = 0;
  229. }
  230. }
  231. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  232. {
  233. struct iwl_frame *frame;
  234. struct list_head *element;
  235. if (list_empty(&priv->free_frames)) {
  236. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  237. if (!frame) {
  238. IWL_ERR(priv, "Could not allocate frame!\n");
  239. return NULL;
  240. }
  241. priv->frames_count++;
  242. return frame;
  243. }
  244. element = priv->free_frames.next;
  245. list_del(element);
  246. return list_entry(element, struct iwl_frame, list);
  247. }
  248. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  249. {
  250. memset(frame, 0, sizeof(*frame));
  251. list_add(&frame->list, &priv->free_frames);
  252. }
  253. static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
  254. struct ieee80211_hdr *hdr,
  255. int left)
  256. {
  257. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  258. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  259. (priv->iw_mode != NL80211_IFTYPE_AP)))
  260. return 0;
  261. if (priv->ibss_beacon->len > left)
  262. return 0;
  263. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  264. return priv->ibss_beacon->len;
  265. }
  266. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  267. struct iwl_frame *frame, u8 rate)
  268. {
  269. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  270. unsigned int frame_size;
  271. tx_beacon_cmd = &frame->u.beacon;
  272. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  273. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  274. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  275. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  276. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  277. BUG_ON(frame_size > MAX_MPDU_SIZE);
  278. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  279. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  280. tx_beacon_cmd->tx.rate_n_flags =
  281. iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  282. else
  283. tx_beacon_cmd->tx.rate_n_flags =
  284. iwl_hw_set_rate_n_flags(rate, 0);
  285. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  286. TX_CMD_FLG_TSF_MSK |
  287. TX_CMD_FLG_STA_RATE_MSK;
  288. return sizeof(*tx_beacon_cmd) + frame_size;
  289. }
  290. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  291. {
  292. struct iwl_frame *frame;
  293. unsigned int frame_size;
  294. int rc;
  295. u8 rate;
  296. frame = iwl_get_free_frame(priv);
  297. if (!frame) {
  298. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  299. "command.\n");
  300. return -ENOMEM;
  301. }
  302. rate = iwl_rate_get_lowest_plcp(priv);
  303. frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
  304. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  305. &frame->u.cmd[0]);
  306. iwl_free_frame(priv, frame);
  307. return rc;
  308. }
  309. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  310. {
  311. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  312. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  313. if (sizeof(dma_addr_t) > sizeof(u32))
  314. addr |=
  315. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  316. return addr;
  317. }
  318. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  319. {
  320. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  321. return le16_to_cpu(tb->hi_n_len) >> 4;
  322. }
  323. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  324. dma_addr_t addr, u16 len)
  325. {
  326. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  327. u16 hi_n_len = len << 4;
  328. put_unaligned_le32(addr, &tb->lo);
  329. if (sizeof(dma_addr_t) > sizeof(u32))
  330. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  331. tb->hi_n_len = cpu_to_le16(hi_n_len);
  332. tfd->num_tbs = idx + 1;
  333. }
  334. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  335. {
  336. return tfd->num_tbs & 0x1f;
  337. }
  338. /**
  339. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  340. * @priv - driver private data
  341. * @txq - tx queue
  342. *
  343. * Does NOT advance any TFD circular buffer read/write indexes
  344. * Does NOT free the TFD itself (which is within circular buffer)
  345. */
  346. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  347. {
  348. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  349. struct iwl_tfd *tfd;
  350. struct pci_dev *dev = priv->pci_dev;
  351. int index = txq->q.read_ptr;
  352. int i;
  353. int num_tbs;
  354. tfd = &tfd_tmp[index];
  355. /* Sanity check on number of chunks */
  356. num_tbs = iwl_tfd_get_num_tbs(tfd);
  357. if (num_tbs >= IWL_NUM_OF_TBS) {
  358. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  359. /* @todo issue fatal error, it is quite serious situation */
  360. return;
  361. }
  362. /* Unmap tx_cmd */
  363. if (num_tbs)
  364. pci_unmap_single(dev,
  365. pci_unmap_addr(&txq->cmd[index]->meta, mapping),
  366. pci_unmap_len(&txq->cmd[index]->meta, len),
  367. PCI_DMA_BIDIRECTIONAL);
  368. /* Unmap chunks, if any. */
  369. for (i = 1; i < num_tbs; i++) {
  370. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  371. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  372. if (txq->txb) {
  373. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  374. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  375. }
  376. }
  377. }
  378. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  379. struct iwl_tx_queue *txq,
  380. dma_addr_t addr, u16 len,
  381. u8 reset, u8 pad)
  382. {
  383. struct iwl_queue *q;
  384. struct iwl_tfd *tfd, *tfd_tmp;
  385. u32 num_tbs;
  386. q = &txq->q;
  387. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  388. tfd = &tfd_tmp[q->write_ptr];
  389. if (reset)
  390. memset(tfd, 0, sizeof(*tfd));
  391. num_tbs = iwl_tfd_get_num_tbs(tfd);
  392. /* Each TFD can point to a maximum 20 Tx buffers */
  393. if (num_tbs >= IWL_NUM_OF_TBS) {
  394. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  395. IWL_NUM_OF_TBS);
  396. return -EINVAL;
  397. }
  398. BUG_ON(addr & ~DMA_BIT_MASK(36));
  399. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  400. IWL_ERR(priv, "Unaligned address = %llx\n",
  401. (unsigned long long)addr);
  402. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  403. return 0;
  404. }
  405. /*
  406. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  407. * given Tx queue, and enable the DMA channel used for that queue.
  408. *
  409. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  410. * channels supported in hardware.
  411. */
  412. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  413. struct iwl_tx_queue *txq)
  414. {
  415. int txq_id = txq->q.id;
  416. /* Circular buffer (TFD queue in DRAM) physical base address */
  417. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  418. txq->q.dma_addr >> 8);
  419. return 0;
  420. }
  421. /******************************************************************************
  422. *
  423. * Generic RX handler implementations
  424. *
  425. ******************************************************************************/
  426. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  427. struct iwl_rx_mem_buffer *rxb)
  428. {
  429. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  430. struct iwl_alive_resp *palive;
  431. struct delayed_work *pwork;
  432. palive = &pkt->u.alive_frame;
  433. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  434. "0x%01X 0x%01X\n",
  435. palive->is_valid, palive->ver_type,
  436. palive->ver_subtype);
  437. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  438. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  439. memcpy(&priv->card_alive_init,
  440. &pkt->u.alive_frame,
  441. sizeof(struct iwl_init_alive_resp));
  442. pwork = &priv->init_alive_start;
  443. } else {
  444. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  445. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  446. sizeof(struct iwl_alive_resp));
  447. pwork = &priv->alive_start;
  448. }
  449. /* We delay the ALIVE response by 5ms to
  450. * give the HW RF Kill time to activate... */
  451. if (palive->is_valid == UCODE_VALID_OK)
  452. queue_delayed_work(priv->workqueue, pwork,
  453. msecs_to_jiffies(5));
  454. else
  455. IWL_WARN(priv, "uCode did not respond OK.\n");
  456. }
  457. static void iwl_bg_beacon_update(struct work_struct *work)
  458. {
  459. struct iwl_priv *priv =
  460. container_of(work, struct iwl_priv, beacon_update);
  461. struct sk_buff *beacon;
  462. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  463. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  464. if (!beacon) {
  465. IWL_ERR(priv, "update beacon failed\n");
  466. return;
  467. }
  468. mutex_lock(&priv->mutex);
  469. /* new beacon skb is allocated every time; dispose previous.*/
  470. if (priv->ibss_beacon)
  471. dev_kfree_skb(priv->ibss_beacon);
  472. priv->ibss_beacon = beacon;
  473. mutex_unlock(&priv->mutex);
  474. iwl_send_beacon_cmd(priv);
  475. }
  476. /**
  477. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  478. *
  479. * This callback is provided in order to send a statistics request.
  480. *
  481. * This timer function is continually reset to execute within
  482. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  483. * was received. We need to ensure we receive the statistics in order
  484. * to update the temperature used for calibrating the TXPOWER.
  485. */
  486. static void iwl_bg_statistics_periodic(unsigned long data)
  487. {
  488. struct iwl_priv *priv = (struct iwl_priv *)data;
  489. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  490. return;
  491. /* dont send host command if rf-kill is on */
  492. if (!iwl_is_ready_rf(priv))
  493. return;
  494. iwl_send_statistics_request(priv, CMD_ASYNC);
  495. }
  496. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  497. struct iwl_rx_mem_buffer *rxb)
  498. {
  499. #ifdef CONFIG_IWLWIFI_DEBUG
  500. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  501. struct iwl4965_beacon_notif *beacon =
  502. (struct iwl4965_beacon_notif *)pkt->u.raw;
  503. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  504. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  505. "tsf %d %d rate %d\n",
  506. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  507. beacon->beacon_notify_hdr.failure_frame,
  508. le32_to_cpu(beacon->ibss_mgr_status),
  509. le32_to_cpu(beacon->high_tsf),
  510. le32_to_cpu(beacon->low_tsf), rate);
  511. #endif
  512. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  513. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  514. queue_work(priv->workqueue, &priv->beacon_update);
  515. }
  516. /* Handle notification from uCode that card's power state is changing
  517. * due to software, hardware, or critical temperature RFKILL */
  518. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  519. struct iwl_rx_mem_buffer *rxb)
  520. {
  521. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  522. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  523. unsigned long status = priv->status;
  524. unsigned long reg_flags;
  525. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
  526. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  527. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  528. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  529. RF_CARD_DISABLED)) {
  530. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  531. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  532. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  533. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  534. if (!(flags & RXON_CARD_DISABLED)) {
  535. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  536. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  537. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  538. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  539. }
  540. if (flags & RF_CARD_DISABLED) {
  541. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  542. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  543. iwl_read32(priv, CSR_UCODE_DRV_GP1);
  544. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  545. if (!iwl_grab_nic_access(priv))
  546. iwl_release_nic_access(priv);
  547. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  548. }
  549. }
  550. if (flags & HW_CARD_DISABLED)
  551. set_bit(STATUS_RF_KILL_HW, &priv->status);
  552. else
  553. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  554. if (!(flags & RXON_CARD_DISABLED))
  555. iwl_scan_cancel(priv);
  556. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  557. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  558. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  559. test_bit(STATUS_RF_KILL_HW, &priv->status));
  560. else
  561. wake_up_interruptible(&priv->wait_command_queue);
  562. }
  563. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  564. {
  565. if (src == IWL_PWR_SRC_VAUX) {
  566. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  567. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  568. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  569. ~APMG_PS_CTRL_MSK_PWR_SRC);
  570. } else {
  571. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  572. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  573. ~APMG_PS_CTRL_MSK_PWR_SRC);
  574. }
  575. return 0;
  576. }
  577. /**
  578. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  579. *
  580. * Setup the RX handlers for each of the reply types sent from the uCode
  581. * to the host.
  582. *
  583. * This function chains into the hardware specific files for them to setup
  584. * any hardware specific handlers as well.
  585. */
  586. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  587. {
  588. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  589. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  590. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  591. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  592. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  593. iwl_rx_pm_debug_statistics_notif;
  594. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  595. /*
  596. * The same handler is used for both the REPLY to a discrete
  597. * statistics request from the host as well as for the periodic
  598. * statistics notifications (after received beacons) from the uCode.
  599. */
  600. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
  601. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  602. iwl_setup_spectrum_handlers(priv);
  603. iwl_setup_rx_scan_handlers(priv);
  604. /* status change handler */
  605. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  606. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  607. iwl_rx_missed_beacon_notif;
  608. /* Rx handlers */
  609. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  610. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  611. /* block ack */
  612. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  613. /* Set up hardware specific Rx handlers */
  614. priv->cfg->ops->lib->rx_handler_setup(priv);
  615. }
  616. /**
  617. * iwl_rx_handle - Main entry function for receiving responses from uCode
  618. *
  619. * Uses the priv->rx_handlers callback function array to invoke
  620. * the appropriate handlers, including command responses,
  621. * frame-received notifications, and other notifications.
  622. */
  623. void iwl_rx_handle(struct iwl_priv *priv)
  624. {
  625. struct iwl_rx_mem_buffer *rxb;
  626. struct iwl_rx_packet *pkt;
  627. struct iwl_rx_queue *rxq = &priv->rxq;
  628. u32 r, i;
  629. int reclaim;
  630. unsigned long flags;
  631. u8 fill_rx = 0;
  632. u32 count = 8;
  633. int total_empty;
  634. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  635. * buffer that the driver may process (last buffer filled by ucode). */
  636. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  637. i = rxq->read;
  638. /* Rx interrupt, but nothing sent from uCode */
  639. if (i == r)
  640. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  641. /* calculate total frames need to be restock after handling RX */
  642. total_empty = r - priv->rxq.write_actual;
  643. if (total_empty < 0)
  644. total_empty += RX_QUEUE_SIZE;
  645. if (total_empty > (RX_QUEUE_SIZE / 2))
  646. fill_rx = 1;
  647. while (i != r) {
  648. rxb = rxq->queue[i];
  649. /* If an RXB doesn't have a Rx queue slot associated with it,
  650. * then a bug has been introduced in the queue refilling
  651. * routines -- catch it here */
  652. BUG_ON(rxb == NULL);
  653. rxq->queue[i] = NULL;
  654. pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
  655. priv->hw_params.rx_buf_size + 256,
  656. PCI_DMA_FROMDEVICE);
  657. pkt = (struct iwl_rx_packet *)rxb->skb->data;
  658. /* Reclaim a command buffer only if this packet is a response
  659. * to a (driver-originated) command.
  660. * If the packet (e.g. Rx frame) originated from uCode,
  661. * there is no command buffer to reclaim.
  662. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  663. * but apparently a few don't get set; catch them here. */
  664. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  665. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  666. (pkt->hdr.cmd != REPLY_RX) &&
  667. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  668. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  669. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  670. (pkt->hdr.cmd != REPLY_TX);
  671. /* Based on type of command response or notification,
  672. * handle those that need handling via function in
  673. * rx_handlers table. See iwl_setup_rx_handlers() */
  674. if (priv->rx_handlers[pkt->hdr.cmd]) {
  675. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  676. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  677. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  678. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  679. } else {
  680. /* No handling needed */
  681. IWL_DEBUG_RX(priv,
  682. "r %d i %d No handler needed for %s, 0x%02x\n",
  683. r, i, get_cmd_string(pkt->hdr.cmd),
  684. pkt->hdr.cmd);
  685. }
  686. if (reclaim) {
  687. /* Invoke any callbacks, transfer the skb to caller, and
  688. * fire off the (possibly) blocking iwl_send_cmd()
  689. * as we reclaim the driver command queue */
  690. if (rxb && rxb->skb)
  691. iwl_tx_cmd_complete(priv, rxb);
  692. else
  693. IWL_WARN(priv, "Claim null rxb?\n");
  694. }
  695. /* For now we just don't re-use anything. We can tweak this
  696. * later to try and re-use notification packets and SKBs that
  697. * fail to Rx correctly */
  698. if (rxb->skb != NULL) {
  699. priv->alloc_rxb_skb--;
  700. dev_kfree_skb_any(rxb->skb);
  701. rxb->skb = NULL;
  702. }
  703. spin_lock_irqsave(&rxq->lock, flags);
  704. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  705. spin_unlock_irqrestore(&rxq->lock, flags);
  706. i = (i + 1) & RX_QUEUE_MASK;
  707. /* If there are a lot of unused frames,
  708. * restock the Rx queue so ucode wont assert. */
  709. if (fill_rx) {
  710. count++;
  711. if (count >= 8) {
  712. priv->rxq.read = i;
  713. iwl_rx_replenish_now(priv);
  714. count = 0;
  715. }
  716. }
  717. }
  718. /* Backtrack one entry */
  719. priv->rxq.read = i;
  720. if (fill_rx)
  721. iwl_rx_replenish_now(priv);
  722. else
  723. iwl_rx_queue_restock(priv);
  724. }
  725. /* call this function to flush any scheduled tasklet */
  726. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  727. {
  728. /* wait to make sure we flush pending tasklet*/
  729. synchronize_irq(priv->pci_dev->irq);
  730. tasklet_kill(&priv->irq_tasklet);
  731. }
  732. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  733. {
  734. u32 inta, handled = 0;
  735. u32 inta_fh;
  736. unsigned long flags;
  737. #ifdef CONFIG_IWLWIFI_DEBUG
  738. u32 inta_mask;
  739. #endif
  740. spin_lock_irqsave(&priv->lock, flags);
  741. /* Ack/clear/reset pending uCode interrupts.
  742. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  743. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  744. inta = iwl_read32(priv, CSR_INT);
  745. iwl_write32(priv, CSR_INT, inta);
  746. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  747. * Any new interrupts that happen after this, either while we're
  748. * in this tasklet, or later, will show up in next ISR/tasklet. */
  749. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  750. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  751. #ifdef CONFIG_IWLWIFI_DEBUG
  752. if (priv->debug_level & IWL_DL_ISR) {
  753. /* just for debug */
  754. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  755. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  756. inta, inta_mask, inta_fh);
  757. }
  758. #endif
  759. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  760. * atomic, make sure that inta covers all the interrupts that
  761. * we've discovered, even if FH interrupt came in just after
  762. * reading CSR_INT. */
  763. if (inta_fh & CSR49_FH_INT_RX_MASK)
  764. inta |= CSR_INT_BIT_FH_RX;
  765. if (inta_fh & CSR49_FH_INT_TX_MASK)
  766. inta |= CSR_INT_BIT_FH_TX;
  767. /* Now service all interrupt bits discovered above. */
  768. if (inta & CSR_INT_BIT_HW_ERR) {
  769. IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
  770. /* Tell the device to stop sending interrupts */
  771. iwl_disable_interrupts(priv);
  772. priv->isr_stats.hw++;
  773. iwl_irq_handle_error(priv);
  774. handled |= CSR_INT_BIT_HW_ERR;
  775. spin_unlock_irqrestore(&priv->lock, flags);
  776. return;
  777. }
  778. #ifdef CONFIG_IWLWIFI_DEBUG
  779. if (priv->debug_level & (IWL_DL_ISR)) {
  780. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  781. if (inta & CSR_INT_BIT_SCD) {
  782. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  783. "the frame/frames.\n");
  784. priv->isr_stats.sch++;
  785. }
  786. /* Alive notification via Rx interrupt will do the real work */
  787. if (inta & CSR_INT_BIT_ALIVE) {
  788. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  789. priv->isr_stats.alive++;
  790. }
  791. }
  792. #endif
  793. /* Safely ignore these bits for debug checks below */
  794. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  795. /* HW RF KILL switch toggled */
  796. if (inta & CSR_INT_BIT_RF_KILL) {
  797. int hw_rf_kill = 0;
  798. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  799. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  800. hw_rf_kill = 1;
  801. IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
  802. hw_rf_kill ? "disable radio" : "enable radio");
  803. priv->isr_stats.rfkill++;
  804. /* driver only loads ucode once setting the interface up.
  805. * the driver allows loading the ucode even if the radio
  806. * is killed. Hence update the killswitch state here. The
  807. * rfkill handler will care about restarting if needed.
  808. */
  809. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  810. if (hw_rf_kill)
  811. set_bit(STATUS_RF_KILL_HW, &priv->status);
  812. else
  813. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  814. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  815. }
  816. handled |= CSR_INT_BIT_RF_KILL;
  817. }
  818. /* Chip got too hot and stopped itself */
  819. if (inta & CSR_INT_BIT_CT_KILL) {
  820. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  821. priv->isr_stats.ctkill++;
  822. handled |= CSR_INT_BIT_CT_KILL;
  823. }
  824. /* Error detected by uCode */
  825. if (inta & CSR_INT_BIT_SW_ERR) {
  826. IWL_ERR(priv, "Microcode SW error detected. "
  827. " Restarting 0x%X.\n", inta);
  828. priv->isr_stats.sw++;
  829. priv->isr_stats.sw_err = inta;
  830. iwl_irq_handle_error(priv);
  831. handled |= CSR_INT_BIT_SW_ERR;
  832. }
  833. /* uCode wakes up after power-down sleep */
  834. if (inta & CSR_INT_BIT_WAKEUP) {
  835. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  836. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  837. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  838. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  839. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  840. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  841. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  842. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  843. priv->isr_stats.wakeup++;
  844. handled |= CSR_INT_BIT_WAKEUP;
  845. }
  846. /* All uCode command responses, including Tx command responses,
  847. * Rx "responses" (frame-received notification), and other
  848. * notifications from uCode come through here*/
  849. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  850. iwl_rx_handle(priv);
  851. priv->isr_stats.rx++;
  852. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  853. }
  854. if (inta & CSR_INT_BIT_FH_TX) {
  855. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  856. priv->isr_stats.tx++;
  857. handled |= CSR_INT_BIT_FH_TX;
  858. /* FH finished to write, send event */
  859. priv->ucode_write_complete = 1;
  860. wake_up_interruptible(&priv->wait_command_queue);
  861. }
  862. if (inta & ~handled) {
  863. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  864. priv->isr_stats.unhandled++;
  865. }
  866. if (inta & ~(priv->inta_mask)) {
  867. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  868. inta & ~priv->inta_mask);
  869. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  870. }
  871. /* Re-enable all interrupts */
  872. /* only Re-enable if diabled by irq */
  873. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  874. iwl_enable_interrupts(priv);
  875. #ifdef CONFIG_IWLWIFI_DEBUG
  876. if (priv->debug_level & (IWL_DL_ISR)) {
  877. inta = iwl_read32(priv, CSR_INT);
  878. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  879. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  880. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  881. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  882. }
  883. #endif
  884. spin_unlock_irqrestore(&priv->lock, flags);
  885. }
  886. /* tasklet for iwlagn interrupt */
  887. static void iwl_irq_tasklet(struct iwl_priv *priv)
  888. {
  889. u32 inta = 0;
  890. u32 handled = 0;
  891. unsigned long flags;
  892. #ifdef CONFIG_IWLWIFI_DEBUG
  893. u32 inta_mask;
  894. #endif
  895. spin_lock_irqsave(&priv->lock, flags);
  896. /* Ack/clear/reset pending uCode interrupts.
  897. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  898. */
  899. iwl_write32(priv, CSR_INT, priv->inta);
  900. inta = priv->inta;
  901. #ifdef CONFIG_IWLWIFI_DEBUG
  902. if (priv->debug_level & IWL_DL_ISR) {
  903. /* just for debug */
  904. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  905. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  906. inta, inta_mask);
  907. }
  908. #endif
  909. /* saved interrupt in inta variable now we can reset priv->inta */
  910. priv->inta = 0;
  911. /* Now service all interrupt bits discovered above. */
  912. if (inta & CSR_INT_BIT_HW_ERR) {
  913. IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
  914. /* Tell the device to stop sending interrupts */
  915. iwl_disable_interrupts(priv);
  916. priv->isr_stats.hw++;
  917. iwl_irq_handle_error(priv);
  918. handled |= CSR_INT_BIT_HW_ERR;
  919. spin_unlock_irqrestore(&priv->lock, flags);
  920. return;
  921. }
  922. #ifdef CONFIG_IWLWIFI_DEBUG
  923. if (priv->debug_level & (IWL_DL_ISR)) {
  924. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  925. if (inta & CSR_INT_BIT_SCD) {
  926. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  927. "the frame/frames.\n");
  928. priv->isr_stats.sch++;
  929. }
  930. /* Alive notification via Rx interrupt will do the real work */
  931. if (inta & CSR_INT_BIT_ALIVE) {
  932. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  933. priv->isr_stats.alive++;
  934. }
  935. }
  936. #endif
  937. /* Safely ignore these bits for debug checks below */
  938. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  939. /* HW RF KILL switch toggled */
  940. if (inta & CSR_INT_BIT_RF_KILL) {
  941. int hw_rf_kill = 0;
  942. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  943. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  944. hw_rf_kill = 1;
  945. IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
  946. hw_rf_kill ? "disable radio" : "enable radio");
  947. priv->isr_stats.rfkill++;
  948. /* driver only loads ucode once setting the interface up.
  949. * the driver allows loading the ucode even if the radio
  950. * is killed. Hence update the killswitch state here. The
  951. * rfkill handler will care about restarting if needed.
  952. */
  953. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  954. if (hw_rf_kill)
  955. set_bit(STATUS_RF_KILL_HW, &priv->status);
  956. else
  957. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  958. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  959. }
  960. handled |= CSR_INT_BIT_RF_KILL;
  961. }
  962. /* Chip got too hot and stopped itself */
  963. if (inta & CSR_INT_BIT_CT_KILL) {
  964. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  965. priv->isr_stats.ctkill++;
  966. handled |= CSR_INT_BIT_CT_KILL;
  967. }
  968. /* Error detected by uCode */
  969. if (inta & CSR_INT_BIT_SW_ERR) {
  970. IWL_ERR(priv, "Microcode SW error detected. "
  971. " Restarting 0x%X.\n", inta);
  972. priv->isr_stats.sw++;
  973. priv->isr_stats.sw_err = inta;
  974. iwl_irq_handle_error(priv);
  975. handled |= CSR_INT_BIT_SW_ERR;
  976. }
  977. /* uCode wakes up after power-down sleep */
  978. if (inta & CSR_INT_BIT_WAKEUP) {
  979. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  980. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  981. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  982. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  983. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  984. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  985. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  986. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  987. priv->isr_stats.wakeup++;
  988. handled |= CSR_INT_BIT_WAKEUP;
  989. }
  990. /* All uCode command responses, including Tx command responses,
  991. * Rx "responses" (frame-received notification), and other
  992. * notifications from uCode come through here*/
  993. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  994. CSR_INT_BIT_RX_PERIODIC)) {
  995. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  996. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  997. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  998. iwl_write32(priv, CSR_FH_INT_STATUS,
  999. CSR49_FH_INT_RX_MASK);
  1000. }
  1001. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1002. handled |= CSR_INT_BIT_RX_PERIODIC;
  1003. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1004. }
  1005. /* Sending RX interrupt require many steps to be done in the
  1006. * the device:
  1007. * 1- write interrupt to current index in ICT table.
  1008. * 2- dma RX frame.
  1009. * 3- update RX shared data to indicate last write index.
  1010. * 4- send interrupt.
  1011. * This could lead to RX race, driver could receive RX interrupt
  1012. * but the shared data changes does not reflect this.
  1013. * this could lead to RX race, RX periodic will solve this race
  1014. */
  1015. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1016. CSR_INT_PERIODIC_DIS);
  1017. iwl_rx_handle(priv);
  1018. /* Only set RX periodic if real RX is received. */
  1019. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1020. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1021. CSR_INT_PERIODIC_ENA);
  1022. priv->isr_stats.rx++;
  1023. }
  1024. if (inta & CSR_INT_BIT_FH_TX) {
  1025. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1026. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  1027. priv->isr_stats.tx++;
  1028. handled |= CSR_INT_BIT_FH_TX;
  1029. /* FH finished to write, send event */
  1030. priv->ucode_write_complete = 1;
  1031. wake_up_interruptible(&priv->wait_command_queue);
  1032. }
  1033. if (inta & ~handled) {
  1034. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1035. priv->isr_stats.unhandled++;
  1036. }
  1037. if (inta & ~(priv->inta_mask)) {
  1038. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1039. inta & ~priv->inta_mask);
  1040. }
  1041. /* Re-enable all interrupts */
  1042. /* only Re-enable if diabled by irq */
  1043. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1044. iwl_enable_interrupts(priv);
  1045. spin_unlock_irqrestore(&priv->lock, flags);
  1046. }
  1047. /******************************************************************************
  1048. *
  1049. * uCode download functions
  1050. *
  1051. ******************************************************************************/
  1052. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1053. {
  1054. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1055. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1056. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1057. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1058. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1059. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1060. }
  1061. static void iwl_nic_start(struct iwl_priv *priv)
  1062. {
  1063. /* Remove all resets to allow NIC to operate */
  1064. iwl_write32(priv, CSR_RESET, 0);
  1065. }
  1066. /**
  1067. * iwl_read_ucode - Read uCode images from disk file.
  1068. *
  1069. * Copy into buffers for card to fetch via bus-mastering
  1070. */
  1071. static int iwl_read_ucode(struct iwl_priv *priv)
  1072. {
  1073. struct iwl_ucode_header *ucode;
  1074. int ret = -EINVAL, index;
  1075. const struct firmware *ucode_raw;
  1076. const char *name_pre = priv->cfg->fw_name_pre;
  1077. const unsigned int api_max = priv->cfg->ucode_api_max;
  1078. const unsigned int api_min = priv->cfg->ucode_api_min;
  1079. char buf[25];
  1080. u8 *src;
  1081. size_t len;
  1082. u32 api_ver, build;
  1083. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1084. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1085. * request_firmware() is synchronous, file is in memory on return. */
  1086. for (index = api_max; index >= api_min; index--) {
  1087. sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
  1088. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1089. if (ret < 0) {
  1090. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1091. buf, ret);
  1092. if (ret == -ENOENT)
  1093. continue;
  1094. else
  1095. goto error;
  1096. } else {
  1097. if (index < api_max)
  1098. IWL_ERR(priv, "Loaded firmware %s, "
  1099. "which is deprecated. "
  1100. "Please use API v%u instead.\n",
  1101. buf, api_max);
  1102. IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
  1103. buf, ucode_raw->size);
  1104. break;
  1105. }
  1106. }
  1107. if (ret < 0)
  1108. goto error;
  1109. /* Make sure that we got at least the v1 header! */
  1110. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1111. IWL_ERR(priv, "File size way too small!\n");
  1112. ret = -EINVAL;
  1113. goto err_release;
  1114. }
  1115. /* Data from ucode file: header followed by uCode images */
  1116. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1117. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1118. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1119. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1120. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1121. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1122. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1123. init_data_size =
  1124. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1125. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1126. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1127. /* api_ver should match the api version forming part of the
  1128. * firmware filename ... but we don't check for that and only rely
  1129. * on the API version read from firmware header from here on forward */
  1130. if (api_ver < api_min || api_ver > api_max) {
  1131. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1132. "Driver supports v%u, firmware is v%u.\n",
  1133. api_max, api_ver);
  1134. priv->ucode_ver = 0;
  1135. ret = -EINVAL;
  1136. goto err_release;
  1137. }
  1138. if (api_ver != api_max)
  1139. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1140. "got v%u. New firmware can be obtained "
  1141. "from http://www.intellinuxwireless.org.\n",
  1142. api_max, api_ver);
  1143. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1144. IWL_UCODE_MAJOR(priv->ucode_ver),
  1145. IWL_UCODE_MINOR(priv->ucode_ver),
  1146. IWL_UCODE_API(priv->ucode_ver),
  1147. IWL_UCODE_SERIAL(priv->ucode_ver));
  1148. if (build)
  1149. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1150. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1151. priv->ucode_ver);
  1152. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1153. inst_size);
  1154. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1155. data_size);
  1156. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1157. init_size);
  1158. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1159. init_data_size);
  1160. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1161. boot_size);
  1162. /* Verify size of file vs. image size info in file's header */
  1163. if (ucode_raw->size !=
  1164. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1165. inst_size + data_size + init_size +
  1166. init_data_size + boot_size) {
  1167. IWL_DEBUG_INFO(priv,
  1168. "uCode file size %d does not match expected size\n",
  1169. (int)ucode_raw->size);
  1170. ret = -EINVAL;
  1171. goto err_release;
  1172. }
  1173. /* Verify that uCode images will fit in card's SRAM */
  1174. if (inst_size > priv->hw_params.max_inst_size) {
  1175. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1176. inst_size);
  1177. ret = -EINVAL;
  1178. goto err_release;
  1179. }
  1180. if (data_size > priv->hw_params.max_data_size) {
  1181. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1182. data_size);
  1183. ret = -EINVAL;
  1184. goto err_release;
  1185. }
  1186. if (init_size > priv->hw_params.max_inst_size) {
  1187. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1188. init_size);
  1189. ret = -EINVAL;
  1190. goto err_release;
  1191. }
  1192. if (init_data_size > priv->hw_params.max_data_size) {
  1193. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1194. init_data_size);
  1195. ret = -EINVAL;
  1196. goto err_release;
  1197. }
  1198. if (boot_size > priv->hw_params.max_bsm_size) {
  1199. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1200. boot_size);
  1201. ret = -EINVAL;
  1202. goto err_release;
  1203. }
  1204. /* Allocate ucode buffers for card's bus-master loading ... */
  1205. /* Runtime instructions and 2 copies of data:
  1206. * 1) unmodified from disk
  1207. * 2) backup cache for save/restore during power-downs */
  1208. priv->ucode_code.len = inst_size;
  1209. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1210. priv->ucode_data.len = data_size;
  1211. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1212. priv->ucode_data_backup.len = data_size;
  1213. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1214. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1215. !priv->ucode_data_backup.v_addr)
  1216. goto err_pci_alloc;
  1217. /* Initialization instructions and data */
  1218. if (init_size && init_data_size) {
  1219. priv->ucode_init.len = init_size;
  1220. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1221. priv->ucode_init_data.len = init_data_size;
  1222. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1223. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1224. goto err_pci_alloc;
  1225. }
  1226. /* Bootstrap (instructions only, no data) */
  1227. if (boot_size) {
  1228. priv->ucode_boot.len = boot_size;
  1229. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1230. if (!priv->ucode_boot.v_addr)
  1231. goto err_pci_alloc;
  1232. }
  1233. /* Copy images into buffers for card's bus-master reads ... */
  1234. /* Runtime instructions (first block of data in file) */
  1235. len = inst_size;
  1236. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1237. memcpy(priv->ucode_code.v_addr, src, len);
  1238. src += len;
  1239. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1240. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1241. /* Runtime data (2nd block)
  1242. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1243. len = data_size;
  1244. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1245. memcpy(priv->ucode_data.v_addr, src, len);
  1246. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1247. src += len;
  1248. /* Initialization instructions (3rd block) */
  1249. if (init_size) {
  1250. len = init_size;
  1251. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1252. len);
  1253. memcpy(priv->ucode_init.v_addr, src, len);
  1254. src += len;
  1255. }
  1256. /* Initialization data (4th block) */
  1257. if (init_data_size) {
  1258. len = init_data_size;
  1259. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1260. len);
  1261. memcpy(priv->ucode_init_data.v_addr, src, len);
  1262. src += len;
  1263. }
  1264. /* Bootstrap instructions (5th block) */
  1265. len = boot_size;
  1266. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1267. memcpy(priv->ucode_boot.v_addr, src, len);
  1268. /* We have our copies now, allow OS release its copies */
  1269. release_firmware(ucode_raw);
  1270. return 0;
  1271. err_pci_alloc:
  1272. IWL_ERR(priv, "failed to allocate pci memory\n");
  1273. ret = -ENOMEM;
  1274. iwl_dealloc_ucode_pci(priv);
  1275. err_release:
  1276. release_firmware(ucode_raw);
  1277. error:
  1278. return ret;
  1279. }
  1280. /**
  1281. * iwl_alive_start - called after REPLY_ALIVE notification received
  1282. * from protocol/runtime uCode (initialization uCode's
  1283. * Alive gets handled by iwl_init_alive_start()).
  1284. */
  1285. static void iwl_alive_start(struct iwl_priv *priv)
  1286. {
  1287. int ret = 0;
  1288. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1289. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1290. /* We had an error bringing up the hardware, so take it
  1291. * all the way back down so we can try again */
  1292. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1293. goto restart;
  1294. }
  1295. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1296. * This is a paranoid check, because we would not have gotten the
  1297. * "runtime" alive if code weren't properly loaded. */
  1298. if (iwl_verify_ucode(priv)) {
  1299. /* Runtime instruction load was bad;
  1300. * take it all the way back down so we can try again */
  1301. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1302. goto restart;
  1303. }
  1304. iwl_clear_stations_table(priv);
  1305. ret = priv->cfg->ops->lib->alive_notify(priv);
  1306. if (ret) {
  1307. IWL_WARN(priv,
  1308. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1309. goto restart;
  1310. }
  1311. /* After the ALIVE response, we can send host commands to the uCode */
  1312. set_bit(STATUS_ALIVE, &priv->status);
  1313. if (iwl_is_rfkill(priv))
  1314. return;
  1315. ieee80211_wake_queues(priv->hw);
  1316. priv->active_rate = priv->rates_mask;
  1317. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1318. if (iwl_is_associated(priv)) {
  1319. struct iwl_rxon_cmd *active_rxon =
  1320. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1321. /* apply any changes in staging */
  1322. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1323. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1324. } else {
  1325. /* Initialize our rx_config data */
  1326. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1327. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1328. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1329. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1330. }
  1331. /* Configure Bluetooth device coexistence support */
  1332. iwl_send_bt_config(priv);
  1333. iwl_reset_run_time_calib(priv);
  1334. /* Configure the adapter for unassociated operation */
  1335. iwlcore_commit_rxon(priv);
  1336. /* At this point, the NIC is initialized and operational */
  1337. iwl_rf_kill_ct_config(priv);
  1338. iwl_leds_register(priv);
  1339. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1340. set_bit(STATUS_READY, &priv->status);
  1341. wake_up_interruptible(&priv->wait_command_queue);
  1342. iwl_power_update_mode(priv, 1);
  1343. /* reassociate for ADHOC mode */
  1344. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1345. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1346. priv->vif);
  1347. if (beacon)
  1348. iwl_mac_beacon_update(priv->hw, beacon);
  1349. }
  1350. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1351. iwl_set_mode(priv, priv->iw_mode);
  1352. return;
  1353. restart:
  1354. queue_work(priv->workqueue, &priv->restart);
  1355. }
  1356. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1357. static void __iwl_down(struct iwl_priv *priv)
  1358. {
  1359. unsigned long flags;
  1360. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1361. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1362. if (!exit_pending)
  1363. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1364. iwl_leds_unregister(priv);
  1365. iwl_clear_stations_table(priv);
  1366. /* Unblock any waiting calls */
  1367. wake_up_interruptible_all(&priv->wait_command_queue);
  1368. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1369. * exiting the module */
  1370. if (!exit_pending)
  1371. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1372. /* stop and reset the on-board processor */
  1373. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1374. /* tell the device to stop sending interrupts */
  1375. spin_lock_irqsave(&priv->lock, flags);
  1376. iwl_disable_interrupts(priv);
  1377. spin_unlock_irqrestore(&priv->lock, flags);
  1378. iwl_synchronize_irq(priv);
  1379. if (priv->mac80211_registered)
  1380. ieee80211_stop_queues(priv->hw);
  1381. /* If we have not previously called iwl_init() then
  1382. * clear all bits but the RF Kill bit and return */
  1383. if (!iwl_is_init(priv)) {
  1384. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1385. STATUS_RF_KILL_HW |
  1386. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1387. STATUS_GEO_CONFIGURED |
  1388. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1389. STATUS_EXIT_PENDING;
  1390. goto exit;
  1391. }
  1392. /* ...otherwise clear out all the status bits but the RF Kill
  1393. * bit and continue taking the NIC down. */
  1394. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1395. STATUS_RF_KILL_HW |
  1396. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1397. STATUS_GEO_CONFIGURED |
  1398. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1399. STATUS_FW_ERROR |
  1400. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1401. STATUS_EXIT_PENDING;
  1402. /* device going down, Stop using ICT table */
  1403. iwl_disable_ict(priv);
  1404. spin_lock_irqsave(&priv->lock, flags);
  1405. iwl_clear_bit(priv, CSR_GP_CNTRL,
  1406. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1407. spin_unlock_irqrestore(&priv->lock, flags);
  1408. iwl_txq_ctx_stop(priv);
  1409. iwl_rxq_stop(priv);
  1410. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  1411. APMG_CLK_VAL_DMA_CLK_RQT);
  1412. udelay(5);
  1413. /* FIXME: apm_ops.suspend(priv) */
  1414. if (exit_pending)
  1415. priv->cfg->ops->lib->apm_ops.stop(priv);
  1416. else
  1417. priv->cfg->ops->lib->apm_ops.reset(priv);
  1418. exit:
  1419. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1420. if (priv->ibss_beacon)
  1421. dev_kfree_skb(priv->ibss_beacon);
  1422. priv->ibss_beacon = NULL;
  1423. /* clear out any free frames */
  1424. iwl_clear_free_frames(priv);
  1425. }
  1426. static void iwl_down(struct iwl_priv *priv)
  1427. {
  1428. mutex_lock(&priv->mutex);
  1429. __iwl_down(priv);
  1430. mutex_unlock(&priv->mutex);
  1431. iwl_cancel_deferred_work(priv);
  1432. }
  1433. #define HW_READY_TIMEOUT (50)
  1434. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1435. {
  1436. int ret = 0;
  1437. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1438. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1439. /* See if we got it */
  1440. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1441. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1442. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1443. HW_READY_TIMEOUT);
  1444. if (ret != -ETIMEDOUT)
  1445. priv->hw_ready = true;
  1446. else
  1447. priv->hw_ready = false;
  1448. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1449. (priv->hw_ready == 1) ? "ready" : "not ready");
  1450. return ret;
  1451. }
  1452. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1453. {
  1454. int ret = 0;
  1455. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1456. ret = iwl_set_hw_ready(priv);
  1457. if (priv->hw_ready)
  1458. return ret;
  1459. /* If HW is not ready, prepare the conditions to check again */
  1460. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1461. CSR_HW_IF_CONFIG_REG_PREPARE);
  1462. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1463. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1464. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1465. /* HW should be ready by now, check again. */
  1466. if (ret != -ETIMEDOUT)
  1467. iwl_set_hw_ready(priv);
  1468. return ret;
  1469. }
  1470. #define MAX_HW_RESTARTS 5
  1471. static int __iwl_up(struct iwl_priv *priv)
  1472. {
  1473. int i;
  1474. int ret;
  1475. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1476. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1477. return -EIO;
  1478. }
  1479. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1480. IWL_ERR(priv, "ucode not available for device bringup\n");
  1481. return -EIO;
  1482. }
  1483. iwl_prepare_card_hw(priv);
  1484. if (!priv->hw_ready) {
  1485. IWL_WARN(priv, "Exit HW not ready\n");
  1486. return -EIO;
  1487. }
  1488. /* If platform's RF_KILL switch is NOT set to KILL */
  1489. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1490. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1491. else
  1492. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1493. if (iwl_is_rfkill(priv)) {
  1494. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1495. iwl_enable_interrupts(priv);
  1496. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1497. return 0;
  1498. }
  1499. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1500. ret = iwl_hw_nic_init(priv);
  1501. if (ret) {
  1502. IWL_ERR(priv, "Unable to init nic\n");
  1503. return ret;
  1504. }
  1505. /* make sure rfkill handshake bits are cleared */
  1506. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1507. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1508. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1509. /* clear (again), then enable host interrupts */
  1510. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1511. iwl_enable_interrupts(priv);
  1512. /* really make sure rfkill handshake bits are cleared */
  1513. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1514. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1515. /* Copy original ucode data image from disk into backup cache.
  1516. * This will be used to initialize the on-board processor's
  1517. * data SRAM for a clean start when the runtime program first loads. */
  1518. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1519. priv->ucode_data.len);
  1520. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1521. iwl_clear_stations_table(priv);
  1522. /* load bootstrap state machine,
  1523. * load bootstrap program into processor's memory,
  1524. * prepare to load the "initialize" uCode */
  1525. ret = priv->cfg->ops->lib->load_ucode(priv);
  1526. if (ret) {
  1527. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1528. ret);
  1529. continue;
  1530. }
  1531. /* start card; "initialize" will load runtime ucode */
  1532. iwl_nic_start(priv);
  1533. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1534. return 0;
  1535. }
  1536. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1537. __iwl_down(priv);
  1538. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1539. /* tried to restart and config the device for as long as our
  1540. * patience could withstand */
  1541. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1542. return -EIO;
  1543. }
  1544. /*****************************************************************************
  1545. *
  1546. * Workqueue callbacks
  1547. *
  1548. *****************************************************************************/
  1549. static void iwl_bg_init_alive_start(struct work_struct *data)
  1550. {
  1551. struct iwl_priv *priv =
  1552. container_of(data, struct iwl_priv, init_alive_start.work);
  1553. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1554. return;
  1555. mutex_lock(&priv->mutex);
  1556. priv->cfg->ops->lib->init_alive_start(priv);
  1557. mutex_unlock(&priv->mutex);
  1558. }
  1559. static void iwl_bg_alive_start(struct work_struct *data)
  1560. {
  1561. struct iwl_priv *priv =
  1562. container_of(data, struct iwl_priv, alive_start.work);
  1563. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1564. return;
  1565. /* enable dram interrupt */
  1566. iwl_reset_ict(priv);
  1567. mutex_lock(&priv->mutex);
  1568. iwl_alive_start(priv);
  1569. mutex_unlock(&priv->mutex);
  1570. }
  1571. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1572. {
  1573. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1574. run_time_calib_work);
  1575. mutex_lock(&priv->mutex);
  1576. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1577. test_bit(STATUS_SCANNING, &priv->status)) {
  1578. mutex_unlock(&priv->mutex);
  1579. return;
  1580. }
  1581. if (priv->start_calib) {
  1582. iwl_chain_noise_calibration(priv, &priv->statistics);
  1583. iwl_sensitivity_calibration(priv, &priv->statistics);
  1584. }
  1585. mutex_unlock(&priv->mutex);
  1586. return;
  1587. }
  1588. static void iwl_bg_up(struct work_struct *data)
  1589. {
  1590. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  1591. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1592. return;
  1593. mutex_lock(&priv->mutex);
  1594. __iwl_up(priv);
  1595. mutex_unlock(&priv->mutex);
  1596. }
  1597. static void iwl_bg_restart(struct work_struct *data)
  1598. {
  1599. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1600. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1601. return;
  1602. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  1603. mutex_lock(&priv->mutex);
  1604. priv->vif = NULL;
  1605. priv->is_open = 0;
  1606. mutex_unlock(&priv->mutex);
  1607. iwl_down(priv);
  1608. ieee80211_restart_hw(priv->hw);
  1609. } else {
  1610. iwl_down(priv);
  1611. queue_work(priv->workqueue, &priv->up);
  1612. }
  1613. }
  1614. static void iwl_bg_rx_replenish(struct work_struct *data)
  1615. {
  1616. struct iwl_priv *priv =
  1617. container_of(data, struct iwl_priv, rx_replenish);
  1618. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1619. return;
  1620. mutex_lock(&priv->mutex);
  1621. iwl_rx_replenish(priv);
  1622. mutex_unlock(&priv->mutex);
  1623. }
  1624. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  1625. void iwl_post_associate(struct iwl_priv *priv)
  1626. {
  1627. struct ieee80211_conf *conf = NULL;
  1628. int ret = 0;
  1629. unsigned long flags;
  1630. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1631. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  1632. return;
  1633. }
  1634. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  1635. priv->assoc_id, priv->active_rxon.bssid_addr);
  1636. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1637. return;
  1638. if (!priv->vif || !priv->is_open)
  1639. return;
  1640. iwl_scan_cancel_timeout(priv, 200);
  1641. conf = ieee80211_get_hw_conf(priv->hw);
  1642. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1643. iwlcore_commit_rxon(priv);
  1644. iwl_setup_rxon_timing(priv);
  1645. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1646. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1647. if (ret)
  1648. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1649. "Attempting to continue.\n");
  1650. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1651. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  1652. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1653. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1654. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1655. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  1656. priv->assoc_id, priv->beacon_int);
  1657. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1658. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1659. else
  1660. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1661. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1662. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1663. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1664. else
  1665. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1666. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1667. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1668. }
  1669. iwlcore_commit_rxon(priv);
  1670. switch (priv->iw_mode) {
  1671. case NL80211_IFTYPE_STATION:
  1672. break;
  1673. case NL80211_IFTYPE_ADHOC:
  1674. /* assume default assoc id */
  1675. priv->assoc_id = 1;
  1676. iwl_rxon_add_station(priv, priv->bssid, 0);
  1677. iwl_send_beacon_cmd(priv);
  1678. break;
  1679. default:
  1680. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  1681. __func__, priv->iw_mode);
  1682. break;
  1683. }
  1684. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1685. priv->assoc_station_added = 1;
  1686. spin_lock_irqsave(&priv->lock, flags);
  1687. iwl_activate_qos(priv, 0);
  1688. spin_unlock_irqrestore(&priv->lock, flags);
  1689. /* the chain noise calibration will enabled PM upon completion
  1690. * If chain noise has already been run, then we need to enable
  1691. * power management here */
  1692. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  1693. iwl_power_update_mode(priv, 0);
  1694. /* Enable Rx differential gain and sensitivity calibrations */
  1695. iwl_chain_noise_reset(priv);
  1696. priv->start_calib = 1;
  1697. }
  1698. /*****************************************************************************
  1699. *
  1700. * mac80211 entry point functions
  1701. *
  1702. *****************************************************************************/
  1703. #define UCODE_READY_TIMEOUT (4 * HZ)
  1704. static int iwl_mac_start(struct ieee80211_hw *hw)
  1705. {
  1706. struct iwl_priv *priv = hw->priv;
  1707. int ret;
  1708. IWL_DEBUG_MAC80211(priv, "enter\n");
  1709. /* we should be verifying the device is ready to be opened */
  1710. mutex_lock(&priv->mutex);
  1711. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  1712. * ucode filename and max sizes are card-specific. */
  1713. if (!priv->ucode_code.len) {
  1714. ret = iwl_read_ucode(priv);
  1715. if (ret) {
  1716. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  1717. mutex_unlock(&priv->mutex);
  1718. return ret;
  1719. }
  1720. }
  1721. ret = __iwl_up(priv);
  1722. mutex_unlock(&priv->mutex);
  1723. if (ret)
  1724. return ret;
  1725. if (iwl_is_rfkill(priv))
  1726. goto out;
  1727. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  1728. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  1729. * mac80211 will not be run successfully. */
  1730. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  1731. test_bit(STATUS_READY, &priv->status),
  1732. UCODE_READY_TIMEOUT);
  1733. if (!ret) {
  1734. if (!test_bit(STATUS_READY, &priv->status)) {
  1735. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  1736. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  1737. return -ETIMEDOUT;
  1738. }
  1739. }
  1740. out:
  1741. priv->is_open = 1;
  1742. IWL_DEBUG_MAC80211(priv, "leave\n");
  1743. return 0;
  1744. }
  1745. static void iwl_mac_stop(struct ieee80211_hw *hw)
  1746. {
  1747. struct iwl_priv *priv = hw->priv;
  1748. IWL_DEBUG_MAC80211(priv, "enter\n");
  1749. if (!priv->is_open)
  1750. return;
  1751. priv->is_open = 0;
  1752. if (iwl_is_ready_rf(priv)) {
  1753. /* stop mac, cancel any scan request and clear
  1754. * RXON_FILTER_ASSOC_MSK BIT
  1755. */
  1756. mutex_lock(&priv->mutex);
  1757. iwl_scan_cancel_timeout(priv, 100);
  1758. mutex_unlock(&priv->mutex);
  1759. }
  1760. iwl_down(priv);
  1761. flush_workqueue(priv->workqueue);
  1762. /* enable interrupts again in order to receive rfkill changes */
  1763. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1764. iwl_enable_interrupts(priv);
  1765. IWL_DEBUG_MAC80211(priv, "leave\n");
  1766. }
  1767. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  1768. {
  1769. struct iwl_priv *priv = hw->priv;
  1770. IWL_DEBUG_MACDUMP(priv, "enter\n");
  1771. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  1772. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  1773. if (iwl_tx_skb(priv, skb))
  1774. dev_kfree_skb_any(skb);
  1775. IWL_DEBUG_MACDUMP(priv, "leave\n");
  1776. return NETDEV_TX_OK;
  1777. }
  1778. void iwl_config_ap(struct iwl_priv *priv)
  1779. {
  1780. int ret = 0;
  1781. unsigned long flags;
  1782. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1783. return;
  1784. /* The following should be done only at AP bring up */
  1785. if (!iwl_is_associated(priv)) {
  1786. /* RXON - unassoc (to set timing command) */
  1787. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1788. iwlcore_commit_rxon(priv);
  1789. /* RXON Timing */
  1790. iwl_setup_rxon_timing(priv);
  1791. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1792. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1793. if (ret)
  1794. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1795. "Attempting to continue.\n");
  1796. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1797. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1798. /* FIXME: what should be the assoc_id for AP? */
  1799. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1800. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1801. priv->staging_rxon.flags |=
  1802. RXON_FLG_SHORT_PREAMBLE_MSK;
  1803. else
  1804. priv->staging_rxon.flags &=
  1805. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1806. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1807. if (priv->assoc_capability &
  1808. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1809. priv->staging_rxon.flags |=
  1810. RXON_FLG_SHORT_SLOT_MSK;
  1811. else
  1812. priv->staging_rxon.flags &=
  1813. ~RXON_FLG_SHORT_SLOT_MSK;
  1814. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1815. priv->staging_rxon.flags &=
  1816. ~RXON_FLG_SHORT_SLOT_MSK;
  1817. }
  1818. /* restore RXON assoc */
  1819. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1820. iwlcore_commit_rxon(priv);
  1821. spin_lock_irqsave(&priv->lock, flags);
  1822. iwl_activate_qos(priv, 1);
  1823. spin_unlock_irqrestore(&priv->lock, flags);
  1824. iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
  1825. }
  1826. iwl_send_beacon_cmd(priv);
  1827. /* FIXME - we need to add code here to detect a totally new
  1828. * configuration, reset the AP, unassoc, rxon timing, assoc,
  1829. * clear sta table, add BCAST sta... */
  1830. }
  1831. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  1832. struct ieee80211_key_conf *keyconf, const u8 *addr,
  1833. u32 iv32, u16 *phase1key)
  1834. {
  1835. struct iwl_priv *priv = hw->priv;
  1836. IWL_DEBUG_MAC80211(priv, "enter\n");
  1837. iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
  1838. IWL_DEBUG_MAC80211(priv, "leave\n");
  1839. }
  1840. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  1841. struct ieee80211_vif *vif,
  1842. struct ieee80211_sta *sta,
  1843. struct ieee80211_key_conf *key)
  1844. {
  1845. struct iwl_priv *priv = hw->priv;
  1846. const u8 *addr;
  1847. int ret;
  1848. u8 sta_id;
  1849. bool is_default_wep_key = false;
  1850. IWL_DEBUG_MAC80211(priv, "enter\n");
  1851. if (priv->cfg->mod_params->sw_crypto) {
  1852. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  1853. return -EOPNOTSUPP;
  1854. }
  1855. addr = sta ? sta->addr : iwl_bcast_addr;
  1856. sta_id = iwl_find_station(priv, addr);
  1857. if (sta_id == IWL_INVALID_STATION) {
  1858. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  1859. addr);
  1860. return -EINVAL;
  1861. }
  1862. mutex_lock(&priv->mutex);
  1863. iwl_scan_cancel_timeout(priv, 100);
  1864. mutex_unlock(&priv->mutex);
  1865. /* If we are getting WEP group key and we didn't receive any key mapping
  1866. * so far, we are in legacy wep mode (group key only), otherwise we are
  1867. * in 1X mode.
  1868. * In legacy wep mode, we use another host command to the uCode */
  1869. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  1870. priv->iw_mode != NL80211_IFTYPE_AP) {
  1871. if (cmd == SET_KEY)
  1872. is_default_wep_key = !priv->key_mapping_key;
  1873. else
  1874. is_default_wep_key =
  1875. (key->hw_key_idx == HW_KEY_DEFAULT);
  1876. }
  1877. switch (cmd) {
  1878. case SET_KEY:
  1879. if (is_default_wep_key)
  1880. ret = iwl_set_default_wep_key(priv, key);
  1881. else
  1882. ret = iwl_set_dynamic_key(priv, key, sta_id);
  1883. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  1884. break;
  1885. case DISABLE_KEY:
  1886. if (is_default_wep_key)
  1887. ret = iwl_remove_default_wep_key(priv, key);
  1888. else
  1889. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  1890. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  1891. break;
  1892. default:
  1893. ret = -EINVAL;
  1894. }
  1895. IWL_DEBUG_MAC80211(priv, "leave\n");
  1896. return ret;
  1897. }
  1898. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  1899. enum ieee80211_ampdu_mlme_action action,
  1900. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  1901. {
  1902. struct iwl_priv *priv = hw->priv;
  1903. int ret;
  1904. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  1905. sta->addr, tid);
  1906. if (!(priv->cfg->sku & IWL_SKU_N))
  1907. return -EACCES;
  1908. switch (action) {
  1909. case IEEE80211_AMPDU_RX_START:
  1910. IWL_DEBUG_HT(priv, "start Rx\n");
  1911. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  1912. case IEEE80211_AMPDU_RX_STOP:
  1913. IWL_DEBUG_HT(priv, "stop Rx\n");
  1914. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  1915. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1916. return 0;
  1917. else
  1918. return ret;
  1919. case IEEE80211_AMPDU_TX_START:
  1920. IWL_DEBUG_HT(priv, "start Tx\n");
  1921. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  1922. case IEEE80211_AMPDU_TX_STOP:
  1923. IWL_DEBUG_HT(priv, "stop Tx\n");
  1924. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  1925. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1926. return 0;
  1927. else
  1928. return ret;
  1929. default:
  1930. IWL_DEBUG_HT(priv, "unknown\n");
  1931. return -EINVAL;
  1932. break;
  1933. }
  1934. return 0;
  1935. }
  1936. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  1937. struct ieee80211_low_level_stats *stats)
  1938. {
  1939. struct iwl_priv *priv = hw->priv;
  1940. priv = hw->priv;
  1941. IWL_DEBUG_MAC80211(priv, "enter\n");
  1942. IWL_DEBUG_MAC80211(priv, "leave\n");
  1943. return 0;
  1944. }
  1945. /*****************************************************************************
  1946. *
  1947. * sysfs attributes
  1948. *
  1949. *****************************************************************************/
  1950. #ifdef CONFIG_IWLWIFI_DEBUG
  1951. /*
  1952. * The following adds a new attribute to the sysfs representation
  1953. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  1954. * used for controlling the debug level.
  1955. *
  1956. * See the level definitions in iwl for details.
  1957. */
  1958. static ssize_t show_debug_level(struct device *d,
  1959. struct device_attribute *attr, char *buf)
  1960. {
  1961. struct iwl_priv *priv = dev_get_drvdata(d);
  1962. return sprintf(buf, "0x%08X\n", priv->debug_level);
  1963. }
  1964. static ssize_t store_debug_level(struct device *d,
  1965. struct device_attribute *attr,
  1966. const char *buf, size_t count)
  1967. {
  1968. struct iwl_priv *priv = dev_get_drvdata(d);
  1969. unsigned long val;
  1970. int ret;
  1971. ret = strict_strtoul(buf, 0, &val);
  1972. if (ret)
  1973. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  1974. else
  1975. priv->debug_level = val;
  1976. return strnlen(buf, count);
  1977. }
  1978. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  1979. show_debug_level, store_debug_level);
  1980. #endif /* CONFIG_IWLWIFI_DEBUG */
  1981. static ssize_t show_version(struct device *d,
  1982. struct device_attribute *attr, char *buf)
  1983. {
  1984. struct iwl_priv *priv = dev_get_drvdata(d);
  1985. struct iwl_alive_resp *palive = &priv->card_alive;
  1986. ssize_t pos = 0;
  1987. u16 eeprom_ver;
  1988. if (palive->is_valid)
  1989. pos += sprintf(buf + pos,
  1990. "fw version: 0x%01X.0x%01X.0x%01X.0x%01X\n"
  1991. "fw type: 0x%01X 0x%01X\n",
  1992. palive->ucode_major, palive->ucode_minor,
  1993. palive->sw_rev[0], palive->sw_rev[1],
  1994. palive->ver_type, palive->ver_subtype);
  1995. else
  1996. pos += sprintf(buf + pos, "fw not loaded\n");
  1997. if (priv->eeprom) {
  1998. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1999. pos += sprintf(buf + pos, "NVM Type: %s, version: 0x%x\n",
  2000. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  2001. ? "OTP" : "EEPROM", eeprom_ver);
  2002. } else {
  2003. pos += sprintf(buf + pos, "EEPROM not initialzed\n");
  2004. }
  2005. return pos;
  2006. }
  2007. static DEVICE_ATTR(version, S_IWUSR | S_IRUGO, show_version, NULL);
  2008. static ssize_t show_temperature(struct device *d,
  2009. struct device_attribute *attr, char *buf)
  2010. {
  2011. struct iwl_priv *priv = dev_get_drvdata(d);
  2012. if (!iwl_is_alive(priv))
  2013. return -EAGAIN;
  2014. return sprintf(buf, "%d\n", priv->temperature);
  2015. }
  2016. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2017. static ssize_t show_tx_power(struct device *d,
  2018. struct device_attribute *attr, char *buf)
  2019. {
  2020. struct iwl_priv *priv = dev_get_drvdata(d);
  2021. if (!iwl_is_ready_rf(priv))
  2022. return sprintf(buf, "off\n");
  2023. else
  2024. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2025. }
  2026. static ssize_t store_tx_power(struct device *d,
  2027. struct device_attribute *attr,
  2028. const char *buf, size_t count)
  2029. {
  2030. struct iwl_priv *priv = dev_get_drvdata(d);
  2031. unsigned long val;
  2032. int ret;
  2033. ret = strict_strtoul(buf, 10, &val);
  2034. if (ret)
  2035. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2036. else
  2037. iwl_set_tx_power(priv, val, false);
  2038. return count;
  2039. }
  2040. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2041. static ssize_t show_flags(struct device *d,
  2042. struct device_attribute *attr, char *buf)
  2043. {
  2044. struct iwl_priv *priv = dev_get_drvdata(d);
  2045. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  2046. }
  2047. static ssize_t store_flags(struct device *d,
  2048. struct device_attribute *attr,
  2049. const char *buf, size_t count)
  2050. {
  2051. struct iwl_priv *priv = dev_get_drvdata(d);
  2052. unsigned long val;
  2053. u32 flags;
  2054. int ret = strict_strtoul(buf, 0, &val);
  2055. if (ret)
  2056. return ret;
  2057. flags = (u32)val;
  2058. mutex_lock(&priv->mutex);
  2059. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  2060. /* Cancel any currently running scans... */
  2061. if (iwl_scan_cancel_timeout(priv, 100))
  2062. IWL_WARN(priv, "Could not cancel scan.\n");
  2063. else {
  2064. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  2065. priv->staging_rxon.flags = cpu_to_le32(flags);
  2066. iwlcore_commit_rxon(priv);
  2067. }
  2068. }
  2069. mutex_unlock(&priv->mutex);
  2070. return count;
  2071. }
  2072. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2073. static ssize_t show_filter_flags(struct device *d,
  2074. struct device_attribute *attr, char *buf)
  2075. {
  2076. struct iwl_priv *priv = dev_get_drvdata(d);
  2077. return sprintf(buf, "0x%04X\n",
  2078. le32_to_cpu(priv->active_rxon.filter_flags));
  2079. }
  2080. static ssize_t store_filter_flags(struct device *d,
  2081. struct device_attribute *attr,
  2082. const char *buf, size_t count)
  2083. {
  2084. struct iwl_priv *priv = dev_get_drvdata(d);
  2085. unsigned long val;
  2086. u32 filter_flags;
  2087. int ret = strict_strtoul(buf, 0, &val);
  2088. if (ret)
  2089. return ret;
  2090. filter_flags = (u32)val;
  2091. mutex_lock(&priv->mutex);
  2092. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  2093. /* Cancel any currently running scans... */
  2094. if (iwl_scan_cancel_timeout(priv, 100))
  2095. IWL_WARN(priv, "Could not cancel scan.\n");
  2096. else {
  2097. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2098. "0x%04X\n", filter_flags);
  2099. priv->staging_rxon.filter_flags =
  2100. cpu_to_le32(filter_flags);
  2101. iwlcore_commit_rxon(priv);
  2102. }
  2103. }
  2104. mutex_unlock(&priv->mutex);
  2105. return count;
  2106. }
  2107. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2108. store_filter_flags);
  2109. static ssize_t store_power_level(struct device *d,
  2110. struct device_attribute *attr,
  2111. const char *buf, size_t count)
  2112. {
  2113. struct iwl_priv *priv = dev_get_drvdata(d);
  2114. int ret;
  2115. unsigned long mode;
  2116. mutex_lock(&priv->mutex);
  2117. ret = strict_strtoul(buf, 10, &mode);
  2118. if (ret)
  2119. goto out;
  2120. ret = iwl_power_set_user_mode(priv, mode);
  2121. if (ret) {
  2122. IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n");
  2123. goto out;
  2124. }
  2125. ret = count;
  2126. out:
  2127. mutex_unlock(&priv->mutex);
  2128. return ret;
  2129. }
  2130. static ssize_t show_power_level(struct device *d,
  2131. struct device_attribute *attr, char *buf)
  2132. {
  2133. struct iwl_priv *priv = dev_get_drvdata(d);
  2134. int level = priv->power_data.power_mode;
  2135. char *p = buf;
  2136. p += sprintf(p, "%d\n", level);
  2137. return p - buf + 1;
  2138. }
  2139. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  2140. store_power_level);
  2141. static ssize_t show_statistics(struct device *d,
  2142. struct device_attribute *attr, char *buf)
  2143. {
  2144. struct iwl_priv *priv = dev_get_drvdata(d);
  2145. u32 size = sizeof(struct iwl_notif_statistics);
  2146. u32 len = 0, ofs = 0;
  2147. u8 *data = (u8 *)&priv->statistics;
  2148. int rc = 0;
  2149. if (!iwl_is_alive(priv))
  2150. return -EAGAIN;
  2151. mutex_lock(&priv->mutex);
  2152. rc = iwl_send_statistics_request(priv, 0);
  2153. mutex_unlock(&priv->mutex);
  2154. if (rc) {
  2155. len = sprintf(buf,
  2156. "Error sending statistics request: 0x%08X\n", rc);
  2157. return len;
  2158. }
  2159. while (size && (PAGE_SIZE - len)) {
  2160. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2161. PAGE_SIZE - len, 1);
  2162. len = strlen(buf);
  2163. if (PAGE_SIZE - len)
  2164. buf[len++] = '\n';
  2165. ofs += 16;
  2166. size -= min(size, 16U);
  2167. }
  2168. return len;
  2169. }
  2170. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2171. /*****************************************************************************
  2172. *
  2173. * driver setup and teardown
  2174. *
  2175. *****************************************************************************/
  2176. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2177. {
  2178. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2179. init_waitqueue_head(&priv->wait_command_queue);
  2180. INIT_WORK(&priv->up, iwl_bg_up);
  2181. INIT_WORK(&priv->restart, iwl_bg_restart);
  2182. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2183. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2184. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2185. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2186. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2187. iwl_setup_scan_deferred_work(priv);
  2188. if (priv->cfg->ops->lib->setup_deferred_work)
  2189. priv->cfg->ops->lib->setup_deferred_work(priv);
  2190. init_timer(&priv->statistics_periodic);
  2191. priv->statistics_periodic.data = (unsigned long)priv;
  2192. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2193. if (!priv->cfg->use_isr_legacy)
  2194. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2195. iwl_irq_tasklet, (unsigned long)priv);
  2196. else
  2197. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2198. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2199. }
  2200. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2201. {
  2202. if (priv->cfg->ops->lib->cancel_deferred_work)
  2203. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2204. cancel_delayed_work_sync(&priv->init_alive_start);
  2205. cancel_delayed_work(&priv->scan_check);
  2206. cancel_delayed_work(&priv->alive_start);
  2207. cancel_work_sync(&priv->beacon_update);
  2208. del_timer_sync(&priv->statistics_periodic);
  2209. }
  2210. static struct attribute *iwl_sysfs_entries[] = {
  2211. &dev_attr_flags.attr,
  2212. &dev_attr_filter_flags.attr,
  2213. &dev_attr_power_level.attr,
  2214. &dev_attr_statistics.attr,
  2215. &dev_attr_temperature.attr,
  2216. &dev_attr_tx_power.attr,
  2217. #ifdef CONFIG_IWLWIFI_DEBUG
  2218. &dev_attr_debug_level.attr,
  2219. #endif
  2220. &dev_attr_version.attr,
  2221. NULL
  2222. };
  2223. static struct attribute_group iwl_attribute_group = {
  2224. .name = NULL, /* put in device directory */
  2225. .attrs = iwl_sysfs_entries,
  2226. };
  2227. static struct ieee80211_ops iwl_hw_ops = {
  2228. .tx = iwl_mac_tx,
  2229. .start = iwl_mac_start,
  2230. .stop = iwl_mac_stop,
  2231. .add_interface = iwl_mac_add_interface,
  2232. .remove_interface = iwl_mac_remove_interface,
  2233. .config = iwl_mac_config,
  2234. .configure_filter = iwl_configure_filter,
  2235. .set_key = iwl_mac_set_key,
  2236. .update_tkip_key = iwl_mac_update_tkip_key,
  2237. .get_stats = iwl_mac_get_stats,
  2238. .get_tx_stats = iwl_mac_get_tx_stats,
  2239. .conf_tx = iwl_mac_conf_tx,
  2240. .reset_tsf = iwl_mac_reset_tsf,
  2241. .bss_info_changed = iwl_bss_info_changed,
  2242. .ampdu_action = iwl_mac_ampdu_action,
  2243. .hw_scan = iwl_mac_hw_scan
  2244. };
  2245. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2246. {
  2247. int err = 0;
  2248. struct iwl_priv *priv;
  2249. struct ieee80211_hw *hw;
  2250. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2251. unsigned long flags;
  2252. u16 pci_cmd;
  2253. /************************
  2254. * 1. Allocating HW data
  2255. ************************/
  2256. /* Disabling hardware scan means that mac80211 will perform scans
  2257. * "the hard way", rather than using device's scan. */
  2258. if (cfg->mod_params->disable_hw_scan) {
  2259. if (cfg->mod_params->debug & IWL_DL_INFO)
  2260. dev_printk(KERN_DEBUG, &(pdev->dev),
  2261. "Disabling hw_scan\n");
  2262. iwl_hw_ops.hw_scan = NULL;
  2263. }
  2264. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2265. if (!hw) {
  2266. err = -ENOMEM;
  2267. goto out;
  2268. }
  2269. priv = hw->priv;
  2270. /* At this point both hw and priv are allocated. */
  2271. SET_IEEE80211_DEV(hw, &pdev->dev);
  2272. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2273. priv->cfg = cfg;
  2274. priv->pci_dev = pdev;
  2275. priv->inta_mask = CSR_INI_SET_MASK;
  2276. #ifdef CONFIG_IWLWIFI_DEBUG
  2277. priv->debug_level = priv->cfg->mod_params->debug;
  2278. atomic_set(&priv->restrict_refcnt, 0);
  2279. #endif
  2280. /**************************
  2281. * 2. Initializing PCI bus
  2282. **************************/
  2283. if (pci_enable_device(pdev)) {
  2284. err = -ENODEV;
  2285. goto out_ieee80211_free_hw;
  2286. }
  2287. pci_set_master(pdev);
  2288. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2289. if (!err)
  2290. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2291. if (err) {
  2292. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2293. if (!err)
  2294. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2295. /* both attempts failed: */
  2296. if (err) {
  2297. IWL_WARN(priv, "No suitable DMA available.\n");
  2298. goto out_pci_disable_device;
  2299. }
  2300. }
  2301. err = pci_request_regions(pdev, DRV_NAME);
  2302. if (err)
  2303. goto out_pci_disable_device;
  2304. pci_set_drvdata(pdev, priv);
  2305. /***********************
  2306. * 3. Read REV register
  2307. ***********************/
  2308. priv->hw_base = pci_iomap(pdev, 0, 0);
  2309. if (!priv->hw_base) {
  2310. err = -ENODEV;
  2311. goto out_pci_release_regions;
  2312. }
  2313. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2314. (unsigned long long) pci_resource_len(pdev, 0));
  2315. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2316. /* this spin lock will be used in apm_ops.init and EEPROM access
  2317. * we should init now
  2318. */
  2319. spin_lock_init(&priv->reg_lock);
  2320. iwl_hw_detect(priv);
  2321. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2322. priv->cfg->name, priv->hw_rev);
  2323. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2324. * PCI Tx retries from interfering with C3 CPU state */
  2325. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2326. iwl_prepare_card_hw(priv);
  2327. if (!priv->hw_ready) {
  2328. IWL_WARN(priv, "Failed, HW not ready\n");
  2329. goto out_iounmap;
  2330. }
  2331. /* amp init */
  2332. err = priv->cfg->ops->lib->apm_ops.init(priv);
  2333. if (err < 0) {
  2334. IWL_ERR(priv, "Failed to init APMG\n");
  2335. goto out_iounmap;
  2336. }
  2337. /*****************
  2338. * 4. Read EEPROM
  2339. *****************/
  2340. /* Read the EEPROM */
  2341. err = iwl_eeprom_init(priv);
  2342. if (err) {
  2343. IWL_ERR(priv, "Unable to init EEPROM\n");
  2344. goto out_iounmap;
  2345. }
  2346. err = iwl_eeprom_check_version(priv);
  2347. if (err)
  2348. goto out_free_eeprom;
  2349. /* extract MAC Address */
  2350. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2351. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2352. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2353. /************************
  2354. * 5. Setup HW constants
  2355. ************************/
  2356. if (iwl_set_hw_params(priv)) {
  2357. IWL_ERR(priv, "failed to set hw parameters\n");
  2358. goto out_free_eeprom;
  2359. }
  2360. /*******************
  2361. * 6. Setup priv
  2362. *******************/
  2363. err = iwl_init_drv(priv);
  2364. if (err)
  2365. goto out_free_eeprom;
  2366. /* At this point both hw and priv are initialized. */
  2367. /********************
  2368. * 7. Setup services
  2369. ********************/
  2370. spin_lock_irqsave(&priv->lock, flags);
  2371. iwl_disable_interrupts(priv);
  2372. spin_unlock_irqrestore(&priv->lock, flags);
  2373. pci_enable_msi(priv->pci_dev);
  2374. iwl_alloc_isr_ict(priv);
  2375. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2376. IRQF_SHARED, DRV_NAME, priv);
  2377. if (err) {
  2378. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2379. goto out_disable_msi;
  2380. }
  2381. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2382. if (err) {
  2383. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2384. goto out_free_irq;
  2385. }
  2386. iwl_setup_deferred_work(priv);
  2387. iwl_setup_rx_handlers(priv);
  2388. /**********************************
  2389. * 8. Setup and register mac80211
  2390. **********************************/
  2391. /* enable interrupts if needed: hw bug w/a */
  2392. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2393. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2394. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2395. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2396. }
  2397. iwl_enable_interrupts(priv);
  2398. err = iwl_setup_mac(priv);
  2399. if (err)
  2400. goto out_remove_sysfs;
  2401. err = iwl_dbgfs_register(priv, DRV_NAME);
  2402. if (err)
  2403. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  2404. /* If platform's RF_KILL switch is NOT set to KILL */
  2405. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2406. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2407. else
  2408. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2409. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  2410. test_bit(STATUS_RF_KILL_HW, &priv->status));
  2411. iwl_power_initialize(priv);
  2412. return 0;
  2413. out_remove_sysfs:
  2414. destroy_workqueue(priv->workqueue);
  2415. priv->workqueue = NULL;
  2416. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2417. out_free_irq:
  2418. free_irq(priv->pci_dev->irq, priv);
  2419. iwl_free_isr_ict(priv);
  2420. out_disable_msi:
  2421. pci_disable_msi(priv->pci_dev);
  2422. iwl_uninit_drv(priv);
  2423. out_free_eeprom:
  2424. iwl_eeprom_free(priv);
  2425. out_iounmap:
  2426. pci_iounmap(pdev, priv->hw_base);
  2427. out_pci_release_regions:
  2428. pci_set_drvdata(pdev, NULL);
  2429. pci_release_regions(pdev);
  2430. out_pci_disable_device:
  2431. pci_disable_device(pdev);
  2432. out_ieee80211_free_hw:
  2433. ieee80211_free_hw(priv->hw);
  2434. out:
  2435. return err;
  2436. }
  2437. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  2438. {
  2439. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2440. unsigned long flags;
  2441. if (!priv)
  2442. return;
  2443. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  2444. iwl_dbgfs_unregister(priv);
  2445. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2446. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  2447. * to be called and iwl_down since we are removing the device
  2448. * we need to set STATUS_EXIT_PENDING bit.
  2449. */
  2450. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2451. if (priv->mac80211_registered) {
  2452. ieee80211_unregister_hw(priv->hw);
  2453. priv->mac80211_registered = 0;
  2454. } else {
  2455. iwl_down(priv);
  2456. }
  2457. /* make sure we flush any pending irq or
  2458. * tasklet for the driver
  2459. */
  2460. spin_lock_irqsave(&priv->lock, flags);
  2461. iwl_disable_interrupts(priv);
  2462. spin_unlock_irqrestore(&priv->lock, flags);
  2463. iwl_synchronize_irq(priv);
  2464. iwl_dealloc_ucode_pci(priv);
  2465. if (priv->rxq.bd)
  2466. iwl_rx_queue_free(priv, &priv->rxq);
  2467. iwl_hw_txq_ctx_free(priv);
  2468. iwl_clear_stations_table(priv);
  2469. iwl_eeprom_free(priv);
  2470. /*netif_stop_queue(dev); */
  2471. flush_workqueue(priv->workqueue);
  2472. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  2473. * priv->workqueue... so we can't take down the workqueue
  2474. * until now... */
  2475. destroy_workqueue(priv->workqueue);
  2476. priv->workqueue = NULL;
  2477. free_irq(priv->pci_dev->irq, priv);
  2478. pci_disable_msi(priv->pci_dev);
  2479. pci_iounmap(pdev, priv->hw_base);
  2480. pci_release_regions(pdev);
  2481. pci_disable_device(pdev);
  2482. pci_set_drvdata(pdev, NULL);
  2483. iwl_uninit_drv(priv);
  2484. iwl_free_isr_ict(priv);
  2485. if (priv->ibss_beacon)
  2486. dev_kfree_skb(priv->ibss_beacon);
  2487. ieee80211_free_hw(priv->hw);
  2488. }
  2489. /*****************************************************************************
  2490. *
  2491. * driver and module entry point
  2492. *
  2493. *****************************************************************************/
  2494. /* Hardware specific file defines the PCI IDs table for that hardware module */
  2495. static struct pci_device_id iwl_hw_card_ids[] = {
  2496. #ifdef CONFIG_IWL4965
  2497. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  2498. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  2499. #endif /* CONFIG_IWL4965 */
  2500. #ifdef CONFIG_IWL5000
  2501. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
  2502. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
  2503. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
  2504. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
  2505. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
  2506. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
  2507. {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
  2508. {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
  2509. {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
  2510. {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
  2511. /* 5350 WiFi/WiMax */
  2512. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
  2513. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
  2514. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
  2515. /* 5150 Wifi/WiMax */
  2516. {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
  2517. {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
  2518. /* 6000/6050 Series */
  2519. {IWL_PCI_DEVICE(0x0082, 0x1102, iwl6000_2ag_cfg)},
  2520. {IWL_PCI_DEVICE(0x0085, 0x1112, iwl6000_2ag_cfg)},
  2521. {IWL_PCI_DEVICE(0x0082, 0x1122, iwl6000_2ag_cfg)},
  2522. {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2523. {IWL_PCI_DEVICE(0x422C, PCI_ANY_ID, iwl6000_2agn_cfg)},
  2524. {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2525. {IWL_PCI_DEVICE(0x4239, PCI_ANY_ID, iwl6000_2agn_cfg)},
  2526. {IWL_PCI_DEVICE(0x0082, PCI_ANY_ID, iwl6000_2agn_cfg)},
  2527. {IWL_PCI_DEVICE(0x0085, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2528. {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2529. {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2530. {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2531. {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2532. /* 1000 Series WiFi */
  2533. {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2534. {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2535. #endif /* CONFIG_IWL5000 */
  2536. {0}
  2537. };
  2538. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  2539. static struct pci_driver iwl_driver = {
  2540. .name = DRV_NAME,
  2541. .id_table = iwl_hw_card_ids,
  2542. .probe = iwl_pci_probe,
  2543. .remove = __devexit_p(iwl_pci_remove),
  2544. #ifdef CONFIG_PM
  2545. .suspend = iwl_pci_suspend,
  2546. .resume = iwl_pci_resume,
  2547. #endif
  2548. };
  2549. static int __init iwl_init(void)
  2550. {
  2551. int ret;
  2552. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  2553. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  2554. ret = iwlagn_rate_control_register();
  2555. if (ret) {
  2556. printk(KERN_ERR DRV_NAME
  2557. "Unable to register rate control algorithm: %d\n", ret);
  2558. return ret;
  2559. }
  2560. ret = pci_register_driver(&iwl_driver);
  2561. if (ret) {
  2562. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  2563. goto error_register;
  2564. }
  2565. return ret;
  2566. error_register:
  2567. iwlagn_rate_control_unregister();
  2568. return ret;
  2569. }
  2570. static void __exit iwl_exit(void)
  2571. {
  2572. pci_unregister_driver(&iwl_driver);
  2573. iwlagn_rate_control_unregister();
  2574. }
  2575. module_exit(iwl_exit);
  2576. module_init(iwl_init);