dmaengine.c 28 KB

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  1. /*
  2. * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59
  16. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called COPYING.
  20. */
  21. /*
  22. * This code implements the DMA subsystem. It provides a HW-neutral interface
  23. * for other kernel code to use asynchronous memory copy capabilities,
  24. * if present, and allows different HW DMA drivers to register as providing
  25. * this capability.
  26. *
  27. * Due to the fact we are accelerating what is already a relatively fast
  28. * operation, the code goes to great lengths to avoid additional overhead,
  29. * such as locking.
  30. *
  31. * LOCKING:
  32. *
  33. * The subsystem keeps a global list of dma_device structs it is protected by a
  34. * mutex, dma_list_mutex.
  35. *
  36. * A subsystem can get access to a channel by calling dmaengine_get() followed
  37. * by dma_find_channel(), or if it has need for an exclusive channel it can call
  38. * dma_request_channel(). Once a channel is allocated a reference is taken
  39. * against its corresponding driver to disable removal.
  40. *
  41. * Each device has a channels list, which runs unlocked but is never modified
  42. * once the device is registered, it's just setup by the driver.
  43. *
  44. * See Documentation/dmaengine.txt for more details
  45. */
  46. #include <linux/init.h>
  47. #include <linux/module.h>
  48. #include <linux/mm.h>
  49. #include <linux/device.h>
  50. #include <linux/dmaengine.h>
  51. #include <linux/hardirq.h>
  52. #include <linux/spinlock.h>
  53. #include <linux/percpu.h>
  54. #include <linux/rcupdate.h>
  55. #include <linux/mutex.h>
  56. #include <linux/jiffies.h>
  57. #include <linux/rculist.h>
  58. #include <linux/idr.h>
  59. static DEFINE_MUTEX(dma_list_mutex);
  60. static LIST_HEAD(dma_device_list);
  61. static long dmaengine_ref_count;
  62. static struct idr dma_idr;
  63. /* --- sysfs implementation --- */
  64. /**
  65. * dev_to_dma_chan - convert a device pointer to the its sysfs container object
  66. * @dev - device node
  67. *
  68. * Must be called under dma_list_mutex
  69. */
  70. static struct dma_chan *dev_to_dma_chan(struct device *dev)
  71. {
  72. struct dma_chan_dev *chan_dev;
  73. chan_dev = container_of(dev, typeof(*chan_dev), device);
  74. return chan_dev->chan;
  75. }
  76. static ssize_t show_memcpy_count(struct device *dev, struct device_attribute *attr, char *buf)
  77. {
  78. struct dma_chan *chan;
  79. unsigned long count = 0;
  80. int i;
  81. int err;
  82. mutex_lock(&dma_list_mutex);
  83. chan = dev_to_dma_chan(dev);
  84. if (chan) {
  85. for_each_possible_cpu(i)
  86. count += per_cpu_ptr(chan->local, i)->memcpy_count;
  87. err = sprintf(buf, "%lu\n", count);
  88. } else
  89. err = -ENODEV;
  90. mutex_unlock(&dma_list_mutex);
  91. return err;
  92. }
  93. static ssize_t show_bytes_transferred(struct device *dev, struct device_attribute *attr,
  94. char *buf)
  95. {
  96. struct dma_chan *chan;
  97. unsigned long count = 0;
  98. int i;
  99. int err;
  100. mutex_lock(&dma_list_mutex);
  101. chan = dev_to_dma_chan(dev);
  102. if (chan) {
  103. for_each_possible_cpu(i)
  104. count += per_cpu_ptr(chan->local, i)->bytes_transferred;
  105. err = sprintf(buf, "%lu\n", count);
  106. } else
  107. err = -ENODEV;
  108. mutex_unlock(&dma_list_mutex);
  109. return err;
  110. }
  111. static ssize_t show_in_use(struct device *dev, struct device_attribute *attr, char *buf)
  112. {
  113. struct dma_chan *chan;
  114. int err;
  115. mutex_lock(&dma_list_mutex);
  116. chan = dev_to_dma_chan(dev);
  117. if (chan)
  118. err = sprintf(buf, "%d\n", chan->client_count);
  119. else
  120. err = -ENODEV;
  121. mutex_unlock(&dma_list_mutex);
  122. return err;
  123. }
  124. static struct device_attribute dma_attrs[] = {
  125. __ATTR(memcpy_count, S_IRUGO, show_memcpy_count, NULL),
  126. __ATTR(bytes_transferred, S_IRUGO, show_bytes_transferred, NULL),
  127. __ATTR(in_use, S_IRUGO, show_in_use, NULL),
  128. __ATTR_NULL
  129. };
  130. static void chan_dev_release(struct device *dev)
  131. {
  132. struct dma_chan_dev *chan_dev;
  133. chan_dev = container_of(dev, typeof(*chan_dev), device);
  134. if (atomic_dec_and_test(chan_dev->idr_ref)) {
  135. mutex_lock(&dma_list_mutex);
  136. idr_remove(&dma_idr, chan_dev->dev_id);
  137. mutex_unlock(&dma_list_mutex);
  138. kfree(chan_dev->idr_ref);
  139. }
  140. kfree(chan_dev);
  141. }
  142. static struct class dma_devclass = {
  143. .name = "dma",
  144. .dev_attrs = dma_attrs,
  145. .dev_release = chan_dev_release,
  146. };
  147. /* --- client and device registration --- */
  148. #define dma_device_satisfies_mask(device, mask) \
  149. __dma_device_satisfies_mask((device), &(mask))
  150. static int
  151. __dma_device_satisfies_mask(struct dma_device *device, dma_cap_mask_t *want)
  152. {
  153. dma_cap_mask_t has;
  154. bitmap_and(has.bits, want->bits, device->cap_mask.bits,
  155. DMA_TX_TYPE_END);
  156. return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
  157. }
  158. static struct module *dma_chan_to_owner(struct dma_chan *chan)
  159. {
  160. return chan->device->dev->driver->owner;
  161. }
  162. /**
  163. * balance_ref_count - catch up the channel reference count
  164. * @chan - channel to balance ->client_count versus dmaengine_ref_count
  165. *
  166. * balance_ref_count must be called under dma_list_mutex
  167. */
  168. static void balance_ref_count(struct dma_chan *chan)
  169. {
  170. struct module *owner = dma_chan_to_owner(chan);
  171. while (chan->client_count < dmaengine_ref_count) {
  172. __module_get(owner);
  173. chan->client_count++;
  174. }
  175. }
  176. /**
  177. * dma_chan_get - try to grab a dma channel's parent driver module
  178. * @chan - channel to grab
  179. *
  180. * Must be called under dma_list_mutex
  181. */
  182. static int dma_chan_get(struct dma_chan *chan)
  183. {
  184. int err = -ENODEV;
  185. struct module *owner = dma_chan_to_owner(chan);
  186. if (chan->client_count) {
  187. __module_get(owner);
  188. err = 0;
  189. } else if (try_module_get(owner))
  190. err = 0;
  191. if (err == 0)
  192. chan->client_count++;
  193. /* allocate upon first client reference */
  194. if (chan->client_count == 1 && err == 0) {
  195. int desc_cnt = chan->device->device_alloc_chan_resources(chan);
  196. if (desc_cnt < 0) {
  197. err = desc_cnt;
  198. chan->client_count = 0;
  199. module_put(owner);
  200. } else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
  201. balance_ref_count(chan);
  202. }
  203. return err;
  204. }
  205. /**
  206. * dma_chan_put - drop a reference to a dma channel's parent driver module
  207. * @chan - channel to release
  208. *
  209. * Must be called under dma_list_mutex
  210. */
  211. static void dma_chan_put(struct dma_chan *chan)
  212. {
  213. if (!chan->client_count)
  214. return; /* this channel failed alloc_chan_resources */
  215. chan->client_count--;
  216. module_put(dma_chan_to_owner(chan));
  217. if (chan->client_count == 0)
  218. chan->device->device_free_chan_resources(chan);
  219. }
  220. enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
  221. {
  222. enum dma_status status;
  223. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  224. dma_async_issue_pending(chan);
  225. do {
  226. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  227. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  228. printk(KERN_ERR "dma_sync_wait_timeout!\n");
  229. return DMA_ERROR;
  230. }
  231. } while (status == DMA_IN_PROGRESS);
  232. return status;
  233. }
  234. EXPORT_SYMBOL(dma_sync_wait);
  235. /**
  236. * dma_cap_mask_all - enable iteration over all operation types
  237. */
  238. static dma_cap_mask_t dma_cap_mask_all;
  239. /**
  240. * dma_chan_tbl_ent - tracks channel allocations per core/operation
  241. * @chan - associated channel for this entry
  242. */
  243. struct dma_chan_tbl_ent {
  244. struct dma_chan *chan;
  245. };
  246. /**
  247. * channel_table - percpu lookup table for memory-to-memory offload providers
  248. */
  249. static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
  250. static int __init dma_channel_table_init(void)
  251. {
  252. enum dma_transaction_type cap;
  253. int err = 0;
  254. bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
  255. /* 'interrupt', 'private', and 'slave' are channel capabilities,
  256. * but are not associated with an operation so they do not need
  257. * an entry in the channel_table
  258. */
  259. clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
  260. clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
  261. clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
  262. for_each_dma_cap_mask(cap, dma_cap_mask_all) {
  263. channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
  264. if (!channel_table[cap]) {
  265. err = -ENOMEM;
  266. break;
  267. }
  268. }
  269. if (err) {
  270. pr_err("dmaengine: initialization failure\n");
  271. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  272. if (channel_table[cap])
  273. free_percpu(channel_table[cap]);
  274. }
  275. return err;
  276. }
  277. arch_initcall(dma_channel_table_init);
  278. /**
  279. * dma_find_channel - find a channel to carry out the operation
  280. * @tx_type: transaction type
  281. */
  282. struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
  283. {
  284. return this_cpu_read(channel_table[tx_type]->chan);
  285. }
  286. EXPORT_SYMBOL(dma_find_channel);
  287. /**
  288. * dma_issue_pending_all - flush all pending operations across all channels
  289. */
  290. void dma_issue_pending_all(void)
  291. {
  292. struct dma_device *device;
  293. struct dma_chan *chan;
  294. rcu_read_lock();
  295. list_for_each_entry_rcu(device, &dma_device_list, global_node) {
  296. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  297. continue;
  298. list_for_each_entry(chan, &device->channels, device_node)
  299. if (chan->client_count)
  300. device->device_issue_pending(chan);
  301. }
  302. rcu_read_unlock();
  303. }
  304. EXPORT_SYMBOL(dma_issue_pending_all);
  305. /**
  306. * nth_chan - returns the nth channel of the given capability
  307. * @cap: capability to match
  308. * @n: nth channel desired
  309. *
  310. * Defaults to returning the channel with the desired capability and the
  311. * lowest reference count when 'n' cannot be satisfied. Must be called
  312. * under dma_list_mutex.
  313. */
  314. static struct dma_chan *nth_chan(enum dma_transaction_type cap, int n)
  315. {
  316. struct dma_device *device;
  317. struct dma_chan *chan;
  318. struct dma_chan *ret = NULL;
  319. struct dma_chan *min = NULL;
  320. list_for_each_entry(device, &dma_device_list, global_node) {
  321. if (!dma_has_cap(cap, device->cap_mask) ||
  322. dma_has_cap(DMA_PRIVATE, device->cap_mask))
  323. continue;
  324. list_for_each_entry(chan, &device->channels, device_node) {
  325. if (!chan->client_count)
  326. continue;
  327. if (!min)
  328. min = chan;
  329. else if (chan->table_count < min->table_count)
  330. min = chan;
  331. if (n-- == 0) {
  332. ret = chan;
  333. break; /* done */
  334. }
  335. }
  336. if (ret)
  337. break; /* done */
  338. }
  339. if (!ret)
  340. ret = min;
  341. if (ret)
  342. ret->table_count++;
  343. return ret;
  344. }
  345. /**
  346. * dma_channel_rebalance - redistribute the available channels
  347. *
  348. * Optimize for cpu isolation (each cpu gets a dedicated channel for an
  349. * operation type) in the SMP case, and operation isolation (avoid
  350. * multi-tasking channels) in the non-SMP case. Must be called under
  351. * dma_list_mutex.
  352. */
  353. static void dma_channel_rebalance(void)
  354. {
  355. struct dma_chan *chan;
  356. struct dma_device *device;
  357. int cpu;
  358. int cap;
  359. int n;
  360. /* undo the last distribution */
  361. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  362. for_each_possible_cpu(cpu)
  363. per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
  364. list_for_each_entry(device, &dma_device_list, global_node) {
  365. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  366. continue;
  367. list_for_each_entry(chan, &device->channels, device_node)
  368. chan->table_count = 0;
  369. }
  370. /* don't populate the channel_table if no clients are available */
  371. if (!dmaengine_ref_count)
  372. return;
  373. /* redistribute available channels */
  374. n = 0;
  375. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  376. for_each_online_cpu(cpu) {
  377. if (num_possible_cpus() > 1)
  378. chan = nth_chan(cap, n++);
  379. else
  380. chan = nth_chan(cap, -1);
  381. per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
  382. }
  383. }
  384. static struct dma_chan *private_candidate(dma_cap_mask_t *mask, struct dma_device *dev,
  385. dma_filter_fn fn, void *fn_param)
  386. {
  387. struct dma_chan *chan;
  388. if (!__dma_device_satisfies_mask(dev, mask)) {
  389. pr_debug("%s: wrong capabilities\n", __func__);
  390. return NULL;
  391. }
  392. /* devices with multiple channels need special handling as we need to
  393. * ensure that all channels are either private or public.
  394. */
  395. if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
  396. list_for_each_entry(chan, &dev->channels, device_node) {
  397. /* some channels are already publicly allocated */
  398. if (chan->client_count)
  399. return NULL;
  400. }
  401. list_for_each_entry(chan, &dev->channels, device_node) {
  402. if (chan->client_count) {
  403. pr_debug("%s: %s busy\n",
  404. __func__, dma_chan_name(chan));
  405. continue;
  406. }
  407. if (fn && !fn(chan, fn_param)) {
  408. pr_debug("%s: %s filter said false\n",
  409. __func__, dma_chan_name(chan));
  410. continue;
  411. }
  412. return chan;
  413. }
  414. return NULL;
  415. }
  416. /**
  417. * dma_request_channel - try to allocate an exclusive channel
  418. * @mask: capabilities that the channel must satisfy
  419. * @fn: optional callback to disposition available channels
  420. * @fn_param: opaque parameter to pass to dma_filter_fn
  421. */
  422. struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param)
  423. {
  424. struct dma_device *device, *_d;
  425. struct dma_chan *chan = NULL;
  426. int err;
  427. /* Find a channel */
  428. mutex_lock(&dma_list_mutex);
  429. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  430. chan = private_candidate(mask, device, fn, fn_param);
  431. if (chan) {
  432. /* Found a suitable channel, try to grab, prep, and
  433. * return it. We first set DMA_PRIVATE to disable
  434. * balance_ref_count as this channel will not be
  435. * published in the general-purpose allocator
  436. */
  437. dma_cap_set(DMA_PRIVATE, device->cap_mask);
  438. device->privatecnt++;
  439. err = dma_chan_get(chan);
  440. if (err == -ENODEV) {
  441. pr_debug("%s: %s module removed\n", __func__,
  442. dma_chan_name(chan));
  443. list_del_rcu(&device->global_node);
  444. } else if (err)
  445. pr_err("dmaengine: failed to get %s: (%d)\n",
  446. dma_chan_name(chan), err);
  447. else
  448. break;
  449. if (--device->privatecnt == 0)
  450. dma_cap_clear(DMA_PRIVATE, device->cap_mask);
  451. chan = NULL;
  452. }
  453. }
  454. mutex_unlock(&dma_list_mutex);
  455. pr_debug("%s: %s (%s)\n", __func__, chan ? "success" : "fail",
  456. chan ? dma_chan_name(chan) : NULL);
  457. return chan;
  458. }
  459. EXPORT_SYMBOL_GPL(__dma_request_channel);
  460. void dma_release_channel(struct dma_chan *chan)
  461. {
  462. mutex_lock(&dma_list_mutex);
  463. WARN_ONCE(chan->client_count != 1,
  464. "chan reference count %d != 1\n", chan->client_count);
  465. dma_chan_put(chan);
  466. /* drop PRIVATE cap enabled by __dma_request_channel() */
  467. if (--chan->device->privatecnt == 0)
  468. dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
  469. mutex_unlock(&dma_list_mutex);
  470. }
  471. EXPORT_SYMBOL_GPL(dma_release_channel);
  472. /**
  473. * dmaengine_get - register interest in dma_channels
  474. */
  475. void dmaengine_get(void)
  476. {
  477. struct dma_device *device, *_d;
  478. struct dma_chan *chan;
  479. int err;
  480. mutex_lock(&dma_list_mutex);
  481. dmaengine_ref_count++;
  482. /* try to grab channels */
  483. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  484. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  485. continue;
  486. list_for_each_entry(chan, &device->channels, device_node) {
  487. err = dma_chan_get(chan);
  488. if (err == -ENODEV) {
  489. /* module removed before we could use it */
  490. list_del_rcu(&device->global_node);
  491. break;
  492. } else if (err)
  493. pr_err("dmaengine: failed to get %s: (%d)\n",
  494. dma_chan_name(chan), err);
  495. }
  496. }
  497. /* if this is the first reference and there were channels
  498. * waiting we need to rebalance to get those channels
  499. * incorporated into the channel table
  500. */
  501. if (dmaengine_ref_count == 1)
  502. dma_channel_rebalance();
  503. mutex_unlock(&dma_list_mutex);
  504. }
  505. EXPORT_SYMBOL(dmaengine_get);
  506. /**
  507. * dmaengine_put - let dma drivers be removed when ref_count == 0
  508. */
  509. void dmaengine_put(void)
  510. {
  511. struct dma_device *device;
  512. struct dma_chan *chan;
  513. mutex_lock(&dma_list_mutex);
  514. dmaengine_ref_count--;
  515. BUG_ON(dmaengine_ref_count < 0);
  516. /* drop channel references */
  517. list_for_each_entry(device, &dma_device_list, global_node) {
  518. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  519. continue;
  520. list_for_each_entry(chan, &device->channels, device_node)
  521. dma_chan_put(chan);
  522. }
  523. mutex_unlock(&dma_list_mutex);
  524. }
  525. EXPORT_SYMBOL(dmaengine_put);
  526. static bool device_has_all_tx_types(struct dma_device *device)
  527. {
  528. /* A device that satisfies this test has channels that will never cause
  529. * an async_tx channel switch event as all possible operation types can
  530. * be handled.
  531. */
  532. #ifdef CONFIG_ASYNC_TX_DMA
  533. if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  534. return false;
  535. #endif
  536. #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
  537. if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
  538. return false;
  539. #endif
  540. #if defined(CONFIG_ASYNC_MEMSET) || defined(CONFIG_ASYNC_MEMSET_MODULE)
  541. if (!dma_has_cap(DMA_MEMSET, device->cap_mask))
  542. return false;
  543. #endif
  544. #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
  545. if (!dma_has_cap(DMA_XOR, device->cap_mask))
  546. return false;
  547. #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
  548. if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
  549. return false;
  550. #endif
  551. #endif
  552. #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
  553. if (!dma_has_cap(DMA_PQ, device->cap_mask))
  554. return false;
  555. #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
  556. if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
  557. return false;
  558. #endif
  559. #endif
  560. return true;
  561. }
  562. static int get_dma_id(struct dma_device *device)
  563. {
  564. int rc;
  565. idr_retry:
  566. if (!idr_pre_get(&dma_idr, GFP_KERNEL))
  567. return -ENOMEM;
  568. mutex_lock(&dma_list_mutex);
  569. rc = idr_get_new(&dma_idr, NULL, &device->dev_id);
  570. mutex_unlock(&dma_list_mutex);
  571. if (rc == -EAGAIN)
  572. goto idr_retry;
  573. else if (rc != 0)
  574. return rc;
  575. return 0;
  576. }
  577. /**
  578. * dma_async_device_register - registers DMA devices found
  579. * @device: &dma_device
  580. */
  581. int dma_async_device_register(struct dma_device *device)
  582. {
  583. int chancnt = 0, rc;
  584. struct dma_chan* chan;
  585. atomic_t *idr_ref;
  586. if (!device)
  587. return -ENODEV;
  588. /* validate device routines */
  589. BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
  590. !device->device_prep_dma_memcpy);
  591. BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
  592. !device->device_prep_dma_xor);
  593. BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
  594. !device->device_prep_dma_xor_val);
  595. BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
  596. !device->device_prep_dma_pq);
  597. BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
  598. !device->device_prep_dma_pq_val);
  599. BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) &&
  600. !device->device_prep_dma_memset);
  601. BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
  602. !device->device_prep_dma_interrupt);
  603. BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
  604. !device->device_prep_slave_sg);
  605. BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
  606. !device->device_control);
  607. BUG_ON(!device->device_alloc_chan_resources);
  608. BUG_ON(!device->device_free_chan_resources);
  609. BUG_ON(!device->device_tx_status);
  610. BUG_ON(!device->device_issue_pending);
  611. BUG_ON(!device->dev);
  612. /* note: this only matters in the
  613. * CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH=y case
  614. */
  615. if (device_has_all_tx_types(device))
  616. dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
  617. idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
  618. if (!idr_ref)
  619. return -ENOMEM;
  620. rc = get_dma_id(device);
  621. if (rc != 0) {
  622. kfree(idr_ref);
  623. return rc;
  624. }
  625. atomic_set(idr_ref, 0);
  626. /* represent channels in sysfs. Probably want devs too */
  627. list_for_each_entry(chan, &device->channels, device_node) {
  628. rc = -ENOMEM;
  629. chan->local = alloc_percpu(typeof(*chan->local));
  630. if (chan->local == NULL)
  631. goto err_out;
  632. chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
  633. if (chan->dev == NULL) {
  634. free_percpu(chan->local);
  635. chan->local = NULL;
  636. goto err_out;
  637. }
  638. chan->chan_id = chancnt++;
  639. chan->dev->device.class = &dma_devclass;
  640. chan->dev->device.parent = device->dev;
  641. chan->dev->chan = chan;
  642. chan->dev->idr_ref = idr_ref;
  643. chan->dev->dev_id = device->dev_id;
  644. atomic_inc(idr_ref);
  645. dev_set_name(&chan->dev->device, "dma%dchan%d",
  646. device->dev_id, chan->chan_id);
  647. rc = device_register(&chan->dev->device);
  648. if (rc) {
  649. free_percpu(chan->local);
  650. chan->local = NULL;
  651. kfree(chan->dev);
  652. atomic_dec(idr_ref);
  653. goto err_out;
  654. }
  655. chan->client_count = 0;
  656. }
  657. device->chancnt = chancnt;
  658. mutex_lock(&dma_list_mutex);
  659. /* take references on public channels */
  660. if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
  661. list_for_each_entry(chan, &device->channels, device_node) {
  662. /* if clients are already waiting for channels we need
  663. * to take references on their behalf
  664. */
  665. if (dma_chan_get(chan) == -ENODEV) {
  666. /* note we can only get here for the first
  667. * channel as the remaining channels are
  668. * guaranteed to get a reference
  669. */
  670. rc = -ENODEV;
  671. mutex_unlock(&dma_list_mutex);
  672. goto err_out;
  673. }
  674. }
  675. list_add_tail_rcu(&device->global_node, &dma_device_list);
  676. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  677. device->privatecnt++; /* Always private */
  678. dma_channel_rebalance();
  679. mutex_unlock(&dma_list_mutex);
  680. return 0;
  681. err_out:
  682. /* if we never registered a channel just release the idr */
  683. if (atomic_read(idr_ref) == 0) {
  684. mutex_lock(&dma_list_mutex);
  685. idr_remove(&dma_idr, device->dev_id);
  686. mutex_unlock(&dma_list_mutex);
  687. kfree(idr_ref);
  688. return rc;
  689. }
  690. list_for_each_entry(chan, &device->channels, device_node) {
  691. if (chan->local == NULL)
  692. continue;
  693. mutex_lock(&dma_list_mutex);
  694. chan->dev->chan = NULL;
  695. mutex_unlock(&dma_list_mutex);
  696. device_unregister(&chan->dev->device);
  697. free_percpu(chan->local);
  698. }
  699. return rc;
  700. }
  701. EXPORT_SYMBOL(dma_async_device_register);
  702. /**
  703. * dma_async_device_unregister - unregister a DMA device
  704. * @device: &dma_device
  705. *
  706. * This routine is called by dma driver exit routines, dmaengine holds module
  707. * references to prevent it being called while channels are in use.
  708. */
  709. void dma_async_device_unregister(struct dma_device *device)
  710. {
  711. struct dma_chan *chan;
  712. mutex_lock(&dma_list_mutex);
  713. list_del_rcu(&device->global_node);
  714. dma_channel_rebalance();
  715. mutex_unlock(&dma_list_mutex);
  716. list_for_each_entry(chan, &device->channels, device_node) {
  717. WARN_ONCE(chan->client_count,
  718. "%s called while %d clients hold a reference\n",
  719. __func__, chan->client_count);
  720. mutex_lock(&dma_list_mutex);
  721. chan->dev->chan = NULL;
  722. mutex_unlock(&dma_list_mutex);
  723. device_unregister(&chan->dev->device);
  724. free_percpu(chan->local);
  725. }
  726. }
  727. EXPORT_SYMBOL(dma_async_device_unregister);
  728. /**
  729. * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
  730. * @chan: DMA channel to offload copy to
  731. * @dest: destination address (virtual)
  732. * @src: source address (virtual)
  733. * @len: length
  734. *
  735. * Both @dest and @src must be mappable to a bus address according to the
  736. * DMA mapping API rules for streaming mappings.
  737. * Both @dest and @src must stay memory resident (kernel memory or locked
  738. * user space pages).
  739. */
  740. dma_cookie_t
  741. dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest,
  742. void *src, size_t len)
  743. {
  744. struct dma_device *dev = chan->device;
  745. struct dma_async_tx_descriptor *tx;
  746. dma_addr_t dma_dest, dma_src;
  747. dma_cookie_t cookie;
  748. unsigned long flags;
  749. dma_src = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE);
  750. dma_dest = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE);
  751. flags = DMA_CTRL_ACK |
  752. DMA_COMPL_SRC_UNMAP_SINGLE |
  753. DMA_COMPL_DEST_UNMAP_SINGLE;
  754. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  755. if (!tx) {
  756. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  757. dma_unmap_single(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  758. return -ENOMEM;
  759. }
  760. tx->callback = NULL;
  761. cookie = tx->tx_submit(tx);
  762. preempt_disable();
  763. __this_cpu_add(chan->local->bytes_transferred, len);
  764. __this_cpu_inc(chan->local->memcpy_count);
  765. preempt_enable();
  766. return cookie;
  767. }
  768. EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf);
  769. /**
  770. * dma_async_memcpy_buf_to_pg - offloaded copy from address to page
  771. * @chan: DMA channel to offload copy to
  772. * @page: destination page
  773. * @offset: offset in page to copy to
  774. * @kdata: source address (virtual)
  775. * @len: length
  776. *
  777. * Both @page/@offset and @kdata must be mappable to a bus address according
  778. * to the DMA mapping API rules for streaming mappings.
  779. * Both @page/@offset and @kdata must stay memory resident (kernel memory or
  780. * locked user space pages)
  781. */
  782. dma_cookie_t
  783. dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page,
  784. unsigned int offset, void *kdata, size_t len)
  785. {
  786. struct dma_device *dev = chan->device;
  787. struct dma_async_tx_descriptor *tx;
  788. dma_addr_t dma_dest, dma_src;
  789. dma_cookie_t cookie;
  790. unsigned long flags;
  791. dma_src = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE);
  792. dma_dest = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE);
  793. flags = DMA_CTRL_ACK | DMA_COMPL_SRC_UNMAP_SINGLE;
  794. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  795. if (!tx) {
  796. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  797. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  798. return -ENOMEM;
  799. }
  800. tx->callback = NULL;
  801. cookie = tx->tx_submit(tx);
  802. preempt_disable();
  803. __this_cpu_add(chan->local->bytes_transferred, len);
  804. __this_cpu_inc(chan->local->memcpy_count);
  805. preempt_enable();
  806. return cookie;
  807. }
  808. EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg);
  809. /**
  810. * dma_async_memcpy_pg_to_pg - offloaded copy from page to page
  811. * @chan: DMA channel to offload copy to
  812. * @dest_pg: destination page
  813. * @dest_off: offset in page to copy to
  814. * @src_pg: source page
  815. * @src_off: offset in page to copy from
  816. * @len: length
  817. *
  818. * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
  819. * address according to the DMA mapping API rules for streaming mappings.
  820. * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
  821. * (kernel memory or locked user space pages).
  822. */
  823. dma_cookie_t
  824. dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg,
  825. unsigned int dest_off, struct page *src_pg, unsigned int src_off,
  826. size_t len)
  827. {
  828. struct dma_device *dev = chan->device;
  829. struct dma_async_tx_descriptor *tx;
  830. dma_addr_t dma_dest, dma_src;
  831. dma_cookie_t cookie;
  832. unsigned long flags;
  833. dma_src = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE);
  834. dma_dest = dma_map_page(dev->dev, dest_pg, dest_off, len,
  835. DMA_FROM_DEVICE);
  836. flags = DMA_CTRL_ACK;
  837. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  838. if (!tx) {
  839. dma_unmap_page(dev->dev, dma_src, len, DMA_TO_DEVICE);
  840. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  841. return -ENOMEM;
  842. }
  843. tx->callback = NULL;
  844. cookie = tx->tx_submit(tx);
  845. preempt_disable();
  846. __this_cpu_add(chan->local->bytes_transferred, len);
  847. __this_cpu_inc(chan->local->memcpy_count);
  848. preempt_enable();
  849. return cookie;
  850. }
  851. EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg);
  852. void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
  853. struct dma_chan *chan)
  854. {
  855. tx->chan = chan;
  856. spin_lock_init(&tx->lock);
  857. }
  858. EXPORT_SYMBOL(dma_async_tx_descriptor_init);
  859. /* dma_wait_for_async_tx - spin wait for a transaction to complete
  860. * @tx: in-flight transaction to wait on
  861. */
  862. enum dma_status
  863. dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
  864. {
  865. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  866. if (!tx)
  867. return DMA_SUCCESS;
  868. while (tx->cookie == -EBUSY) {
  869. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  870. pr_err("%s timeout waiting for descriptor submission\n",
  871. __func__);
  872. return DMA_ERROR;
  873. }
  874. cpu_relax();
  875. }
  876. return dma_sync_wait(tx->chan, tx->cookie);
  877. }
  878. EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
  879. /* dma_run_dependencies - helper routine for dma drivers to process
  880. * (start) dependent operations on their target channel
  881. * @tx: transaction with dependencies
  882. */
  883. void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
  884. {
  885. struct dma_async_tx_descriptor *dep = tx->next;
  886. struct dma_async_tx_descriptor *dep_next;
  887. struct dma_chan *chan;
  888. if (!dep)
  889. return;
  890. /* we'll submit tx->next now, so clear the link */
  891. tx->next = NULL;
  892. chan = dep->chan;
  893. /* keep submitting up until a channel switch is detected
  894. * in that case we will be called again as a result of
  895. * processing the interrupt from async_tx_channel_switch
  896. */
  897. for (; dep; dep = dep_next) {
  898. spin_lock_bh(&dep->lock);
  899. dep->parent = NULL;
  900. dep_next = dep->next;
  901. if (dep_next && dep_next->chan == chan)
  902. dep->next = NULL; /* ->next will be submitted */
  903. else
  904. dep_next = NULL; /* submit current dep and terminate */
  905. spin_unlock_bh(&dep->lock);
  906. dep->tx_submit(dep);
  907. }
  908. chan->device->device_issue_pending(chan);
  909. }
  910. EXPORT_SYMBOL_GPL(dma_run_dependencies);
  911. static int __init dma_bus_init(void)
  912. {
  913. idr_init(&dma_idr);
  914. mutex_init(&dma_list_mutex);
  915. return class_register(&dma_devclass);
  916. }
  917. arch_initcall(dma_bus_init);