radeon_object.c 13 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30. * Dave Airlie
  31. */
  32. #include <linux/list.h>
  33. #include <drm/drmP.h>
  34. #include "radeon_drm.h"
  35. #include "radeon.h"
  36. struct radeon_object {
  37. struct ttm_buffer_object tobj;
  38. struct list_head list;
  39. struct radeon_device *rdev;
  40. struct drm_gem_object *gobj;
  41. struct ttm_bo_kmap_obj kmap;
  42. unsigned pin_count;
  43. uint64_t gpu_addr;
  44. void *kptr;
  45. bool is_iomem;
  46. };
  47. int radeon_ttm_init(struct radeon_device *rdev);
  48. void radeon_ttm_fini(struct radeon_device *rdev);
  49. /*
  50. * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  51. * function are calling it.
  52. */
  53. static int radeon_object_reserve(struct radeon_object *robj, bool interruptible)
  54. {
  55. return ttm_bo_reserve(&robj->tobj, interruptible, false, false, 0);
  56. }
  57. static void radeon_object_unreserve(struct radeon_object *robj)
  58. {
  59. ttm_bo_unreserve(&robj->tobj);
  60. }
  61. static void radeon_ttm_object_object_destroy(struct ttm_buffer_object *tobj)
  62. {
  63. struct radeon_object *robj;
  64. robj = container_of(tobj, struct radeon_object, tobj);
  65. list_del_init(&robj->list);
  66. kfree(robj);
  67. }
  68. static inline void radeon_object_gpu_addr(struct radeon_object *robj)
  69. {
  70. /* Default gpu address */
  71. robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL;
  72. if (robj->tobj.mem.mm_node == NULL) {
  73. return;
  74. }
  75. robj->gpu_addr = ((u64)robj->tobj.mem.mm_node->start) << PAGE_SHIFT;
  76. switch (robj->tobj.mem.mem_type) {
  77. case TTM_PL_VRAM:
  78. robj->gpu_addr += (u64)robj->rdev->mc.vram_location;
  79. break;
  80. case TTM_PL_TT:
  81. robj->gpu_addr += (u64)robj->rdev->mc.gtt_location;
  82. break;
  83. default:
  84. DRM_ERROR("Unknown placement %d\n", robj->tobj.mem.mem_type);
  85. robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL;
  86. return;
  87. }
  88. }
  89. static inline uint32_t radeon_object_flags_from_domain(uint32_t domain)
  90. {
  91. uint32_t flags = 0;
  92. if (domain & RADEON_GEM_DOMAIN_VRAM) {
  93. flags |= TTM_PL_FLAG_VRAM;
  94. }
  95. if (domain & RADEON_GEM_DOMAIN_GTT) {
  96. flags |= TTM_PL_FLAG_TT;
  97. }
  98. if (domain & RADEON_GEM_DOMAIN_CPU) {
  99. flags |= TTM_PL_FLAG_SYSTEM;
  100. }
  101. if (!flags) {
  102. flags |= TTM_PL_FLAG_SYSTEM;
  103. }
  104. return flags;
  105. }
  106. int radeon_object_create(struct radeon_device *rdev,
  107. struct drm_gem_object *gobj,
  108. unsigned long size,
  109. bool kernel,
  110. uint32_t domain,
  111. bool interruptible,
  112. struct radeon_object **robj_ptr)
  113. {
  114. struct radeon_object *robj;
  115. enum ttm_bo_type type;
  116. uint32_t flags;
  117. int r;
  118. if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
  119. rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
  120. }
  121. if (kernel) {
  122. type = ttm_bo_type_kernel;
  123. } else {
  124. type = ttm_bo_type_device;
  125. }
  126. *robj_ptr = NULL;
  127. robj = kzalloc(sizeof(struct radeon_object), GFP_KERNEL);
  128. if (robj == NULL) {
  129. return -ENOMEM;
  130. }
  131. robj->rdev = rdev;
  132. robj->gobj = gobj;
  133. INIT_LIST_HEAD(&robj->list);
  134. flags = radeon_object_flags_from_domain(domain);
  135. r = ttm_buffer_object_init(&rdev->mman.bdev, &robj->tobj, size, type, flags,
  136. 0, 0, false, NULL, size,
  137. &radeon_ttm_object_object_destroy);
  138. if (unlikely(r != 0)) {
  139. /* ttm call radeon_ttm_object_object_destroy if error happen */
  140. DRM_ERROR("Failed to allocate TTM object (%ld, 0x%08X, %u)\n",
  141. size, flags, 0);
  142. return r;
  143. }
  144. *robj_ptr = robj;
  145. if (gobj) {
  146. list_add_tail(&robj->list, &rdev->gem.objects);
  147. }
  148. return 0;
  149. }
  150. int radeon_object_kmap(struct radeon_object *robj, void **ptr)
  151. {
  152. int r;
  153. spin_lock(&robj->tobj.lock);
  154. if (robj->kptr) {
  155. if (ptr) {
  156. *ptr = robj->kptr;
  157. }
  158. spin_unlock(&robj->tobj.lock);
  159. return 0;
  160. }
  161. spin_unlock(&robj->tobj.lock);
  162. r = ttm_bo_kmap(&robj->tobj, 0, robj->tobj.num_pages, &robj->kmap);
  163. if (r) {
  164. return r;
  165. }
  166. spin_lock(&robj->tobj.lock);
  167. robj->kptr = ttm_kmap_obj_virtual(&robj->kmap, &robj->is_iomem);
  168. spin_unlock(&robj->tobj.lock);
  169. if (ptr) {
  170. *ptr = robj->kptr;
  171. }
  172. return 0;
  173. }
  174. void radeon_object_kunmap(struct radeon_object *robj)
  175. {
  176. spin_lock(&robj->tobj.lock);
  177. if (robj->kptr == NULL) {
  178. spin_unlock(&robj->tobj.lock);
  179. return;
  180. }
  181. robj->kptr = NULL;
  182. spin_unlock(&robj->tobj.lock);
  183. ttm_bo_kunmap(&robj->kmap);
  184. }
  185. void radeon_object_unref(struct radeon_object **robj)
  186. {
  187. struct ttm_buffer_object *tobj;
  188. if ((*robj) == NULL) {
  189. return;
  190. }
  191. tobj = &((*robj)->tobj);
  192. ttm_bo_unref(&tobj);
  193. if (tobj == NULL) {
  194. *robj = NULL;
  195. }
  196. }
  197. int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset)
  198. {
  199. *offset = robj->tobj.addr_space_offset;
  200. return 0;
  201. }
  202. int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
  203. uint64_t *gpu_addr)
  204. {
  205. uint32_t flags;
  206. uint32_t tmp;
  207. void *fbptr;
  208. int r;
  209. flags = radeon_object_flags_from_domain(domain);
  210. spin_lock(&robj->tobj.lock);
  211. if (robj->pin_count) {
  212. robj->pin_count++;
  213. if (gpu_addr != NULL) {
  214. *gpu_addr = robj->gpu_addr;
  215. }
  216. spin_unlock(&robj->tobj.lock);
  217. return 0;
  218. }
  219. spin_unlock(&robj->tobj.lock);
  220. r = radeon_object_reserve(robj, false);
  221. if (unlikely(r != 0)) {
  222. DRM_ERROR("radeon: failed to reserve object for pinning it.\n");
  223. return r;
  224. }
  225. if (robj->rdev->fbdev_robj == robj) {
  226. mutex_lock(&robj->rdev->fbdev_info->lock);
  227. radeon_object_kunmap(robj);
  228. }
  229. tmp = robj->tobj.mem.placement;
  230. ttm_flag_masked(&tmp, flags, TTM_PL_MASK_MEM);
  231. robj->tobj.proposed_placement = tmp | TTM_PL_FLAG_NO_EVICT | TTM_PL_MASK_CACHING;
  232. r = ttm_buffer_object_validate(&robj->tobj,
  233. robj->tobj.proposed_placement,
  234. false, false);
  235. radeon_object_gpu_addr(robj);
  236. if (gpu_addr != NULL) {
  237. *gpu_addr = robj->gpu_addr;
  238. }
  239. robj->pin_count = 1;
  240. if (unlikely(r != 0)) {
  241. DRM_ERROR("radeon: failed to pin object.\n");
  242. }
  243. radeon_object_unreserve(robj);
  244. if (robj->rdev->fbdev_robj == robj) {
  245. if (!r) {
  246. r = radeon_object_kmap(robj, &fbptr);
  247. }
  248. if (!r) {
  249. robj->rdev->fbdev_info->screen_base = fbptr;
  250. robj->rdev->fbdev_info->fix.smem_start = (unsigned long)fbptr;
  251. }
  252. mutex_unlock(&robj->rdev->fbdev_info->lock);
  253. }
  254. return r;
  255. }
  256. void radeon_object_unpin(struct radeon_object *robj)
  257. {
  258. uint32_t flags;
  259. void *fbptr;
  260. int r;
  261. spin_lock(&robj->tobj.lock);
  262. if (!robj->pin_count) {
  263. spin_unlock(&robj->tobj.lock);
  264. printk(KERN_WARNING "Unpin not necessary for %p !\n", robj);
  265. return;
  266. }
  267. robj->pin_count--;
  268. if (robj->pin_count) {
  269. spin_unlock(&robj->tobj.lock);
  270. return;
  271. }
  272. spin_unlock(&robj->tobj.lock);
  273. r = radeon_object_reserve(robj, false);
  274. if (unlikely(r != 0)) {
  275. DRM_ERROR("radeon: failed to reserve object for unpinning it.\n");
  276. return;
  277. }
  278. if (robj->rdev->fbdev_robj == robj) {
  279. mutex_lock(&robj->rdev->fbdev_info->lock);
  280. radeon_object_kunmap(robj);
  281. }
  282. flags = robj->tobj.mem.placement;
  283. robj->tobj.proposed_placement = flags & ~TTM_PL_FLAG_NO_EVICT;
  284. r = ttm_buffer_object_validate(&robj->tobj,
  285. robj->tobj.proposed_placement,
  286. false, false);
  287. if (unlikely(r != 0)) {
  288. DRM_ERROR("radeon: failed to unpin buffer.\n");
  289. }
  290. radeon_object_unreserve(robj);
  291. if (robj->rdev->fbdev_robj == robj) {
  292. if (!r) {
  293. r = radeon_object_kmap(robj, &fbptr);
  294. }
  295. if (!r) {
  296. robj->rdev->fbdev_info->screen_base = fbptr;
  297. robj->rdev->fbdev_info->fix.smem_start = (unsigned long)fbptr;
  298. }
  299. mutex_unlock(&robj->rdev->fbdev_info->lock);
  300. }
  301. }
  302. int radeon_object_wait(struct radeon_object *robj)
  303. {
  304. int r = 0;
  305. /* FIXME: should use block reservation instead */
  306. r = radeon_object_reserve(robj, true);
  307. if (unlikely(r != 0)) {
  308. DRM_ERROR("radeon: failed to reserve object for waiting.\n");
  309. return r;
  310. }
  311. spin_lock(&robj->tobj.lock);
  312. if (robj->tobj.sync_obj) {
  313. r = ttm_bo_wait(&robj->tobj, true, false, false);
  314. }
  315. spin_unlock(&robj->tobj.lock);
  316. radeon_object_unreserve(robj);
  317. return r;
  318. }
  319. int radeon_object_evict_vram(struct radeon_device *rdev)
  320. {
  321. if (rdev->flags & RADEON_IS_IGP) {
  322. /* Useless to evict on IGP chips */
  323. return 0;
  324. }
  325. return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
  326. }
  327. void radeon_object_force_delete(struct radeon_device *rdev)
  328. {
  329. struct radeon_object *robj, *n;
  330. struct drm_gem_object *gobj;
  331. if (list_empty(&rdev->gem.objects)) {
  332. return;
  333. }
  334. DRM_ERROR("Userspace still has active objects !\n");
  335. list_for_each_entry_safe(robj, n, &rdev->gem.objects, list) {
  336. mutex_lock(&rdev->ddev->struct_mutex);
  337. gobj = robj->gobj;
  338. DRM_ERROR("Force free for (%p,%p,%lu,%lu)\n",
  339. gobj, robj, (unsigned long)gobj->size,
  340. *((unsigned long *)&gobj->refcount));
  341. list_del_init(&robj->list);
  342. radeon_object_unref(&robj);
  343. gobj->driver_private = NULL;
  344. drm_gem_object_unreference(gobj);
  345. mutex_unlock(&rdev->ddev->struct_mutex);
  346. }
  347. }
  348. int radeon_object_init(struct radeon_device *rdev)
  349. {
  350. return radeon_ttm_init(rdev);
  351. }
  352. void radeon_object_fini(struct radeon_device *rdev)
  353. {
  354. radeon_ttm_fini(rdev);
  355. }
  356. void radeon_object_list_add_object(struct radeon_object_list *lobj,
  357. struct list_head *head)
  358. {
  359. if (lobj->wdomain) {
  360. list_add(&lobj->list, head);
  361. } else {
  362. list_add_tail(&lobj->list, head);
  363. }
  364. }
  365. int radeon_object_list_reserve(struct list_head *head)
  366. {
  367. struct radeon_object_list *lobj;
  368. struct list_head *i;
  369. int r;
  370. list_for_each(i, head) {
  371. lobj = list_entry(i, struct radeon_object_list, list);
  372. if (!lobj->robj->pin_count) {
  373. r = radeon_object_reserve(lobj->robj, true);
  374. if (unlikely(r != 0)) {
  375. DRM_ERROR("radeon: failed to reserve object.\n");
  376. return r;
  377. }
  378. } else {
  379. }
  380. }
  381. return 0;
  382. }
  383. void radeon_object_list_unreserve(struct list_head *head)
  384. {
  385. struct radeon_object_list *lobj;
  386. struct list_head *i;
  387. list_for_each(i, head) {
  388. lobj = list_entry(i, struct radeon_object_list, list);
  389. if (!lobj->robj->pin_count) {
  390. radeon_object_unreserve(lobj->robj);
  391. } else {
  392. }
  393. }
  394. }
  395. int radeon_object_list_validate(struct list_head *head, void *fence)
  396. {
  397. struct radeon_object_list *lobj;
  398. struct radeon_object *robj;
  399. struct radeon_fence *old_fence = NULL;
  400. struct list_head *i;
  401. uint32_t flags;
  402. int r;
  403. r = radeon_object_list_reserve(head);
  404. if (unlikely(r != 0)) {
  405. radeon_object_list_unreserve(head);
  406. return r;
  407. }
  408. list_for_each(i, head) {
  409. lobj = list_entry(i, struct radeon_object_list, list);
  410. robj = lobj->robj;
  411. if (lobj->wdomain) {
  412. flags = radeon_object_flags_from_domain(lobj->wdomain);
  413. flags |= TTM_PL_FLAG_TT;
  414. } else {
  415. flags = radeon_object_flags_from_domain(lobj->rdomain);
  416. flags |= TTM_PL_FLAG_TT;
  417. flags |= TTM_PL_FLAG_VRAM;
  418. }
  419. if (!robj->pin_count) {
  420. robj->tobj.proposed_placement = flags | TTM_PL_MASK_CACHING;
  421. r = ttm_buffer_object_validate(&robj->tobj,
  422. robj->tobj.proposed_placement,
  423. true, false);
  424. if (unlikely(r)) {
  425. radeon_object_list_unreserve(head);
  426. DRM_ERROR("radeon: failed to validate.\n");
  427. return r;
  428. }
  429. radeon_object_gpu_addr(robj);
  430. }
  431. lobj->gpu_offset = robj->gpu_addr;
  432. if (fence) {
  433. old_fence = (struct radeon_fence *)robj->tobj.sync_obj;
  434. robj->tobj.sync_obj = radeon_fence_ref(fence);
  435. robj->tobj.sync_obj_arg = NULL;
  436. }
  437. if (old_fence) {
  438. radeon_fence_unref(&old_fence);
  439. }
  440. }
  441. return 0;
  442. }
  443. void radeon_object_list_unvalidate(struct list_head *head)
  444. {
  445. struct radeon_object_list *lobj;
  446. struct radeon_fence *old_fence = NULL;
  447. struct list_head *i;
  448. list_for_each(i, head) {
  449. lobj = list_entry(i, struct radeon_object_list, list);
  450. old_fence = (struct radeon_fence *)lobj->robj->tobj.sync_obj;
  451. lobj->robj->tobj.sync_obj = NULL;
  452. if (old_fence) {
  453. radeon_fence_unref(&old_fence);
  454. }
  455. }
  456. radeon_object_list_unreserve(head);
  457. }
  458. void radeon_object_list_clean(struct list_head *head)
  459. {
  460. radeon_object_list_unreserve(head);
  461. }
  462. int radeon_object_fbdev_mmap(struct radeon_object *robj,
  463. struct vm_area_struct *vma)
  464. {
  465. return ttm_fbdev_mmap(vma, &robj->tobj);
  466. }
  467. unsigned long radeon_object_size(struct radeon_object *robj)
  468. {
  469. return robj->tobj.num_pages << PAGE_SHIFT;
  470. }