phy_n.c 118 KB

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  1. /*
  2. Broadcom B43 wireless driver
  3. IEEE 802.11n PHY support
  4. Copyright (c) 2008 Michael Buesch <m@bues.ch>
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; see the file COPYING. If not, write to
  15. the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  16. Boston, MA 02110-1301, USA.
  17. */
  18. #include <linux/delay.h>
  19. #include <linux/slab.h>
  20. #include <linux/types.h>
  21. #include "b43.h"
  22. #include "phy_n.h"
  23. #include "tables_nphy.h"
  24. #include "radio_2055.h"
  25. #include "radio_2056.h"
  26. #include "main.h"
  27. struct nphy_txgains {
  28. u16 txgm[2];
  29. u16 pga[2];
  30. u16 pad[2];
  31. u16 ipa[2];
  32. };
  33. struct nphy_iqcal_params {
  34. u16 txgm;
  35. u16 pga;
  36. u16 pad;
  37. u16 ipa;
  38. u16 cal_gain;
  39. u16 ncorr[5];
  40. };
  41. struct nphy_iq_est {
  42. s32 iq0_prod;
  43. u32 i0_pwr;
  44. u32 q0_pwr;
  45. s32 iq1_prod;
  46. u32 i1_pwr;
  47. u32 q1_pwr;
  48. };
  49. enum b43_nphy_rf_sequence {
  50. B43_RFSEQ_RX2TX,
  51. B43_RFSEQ_TX2RX,
  52. B43_RFSEQ_RESET2RX,
  53. B43_RFSEQ_UPDATE_GAINH,
  54. B43_RFSEQ_UPDATE_GAINL,
  55. B43_RFSEQ_UPDATE_GAINU,
  56. };
  57. enum b43_nphy_rssi_type {
  58. B43_NPHY_RSSI_X = 0,
  59. B43_NPHY_RSSI_Y,
  60. B43_NPHY_RSSI_Z,
  61. B43_NPHY_RSSI_PWRDET,
  62. B43_NPHY_RSSI_TSSI_I,
  63. B43_NPHY_RSSI_TSSI_Q,
  64. B43_NPHY_RSSI_TBD,
  65. };
  66. static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev,
  67. bool enable);
  68. static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
  69. u8 *events, u8 *delays, u8 length);
  70. static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
  71. enum b43_nphy_rf_sequence seq);
  72. static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
  73. u16 value, u8 core, bool off);
  74. static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
  75. u16 value, u8 core);
  76. void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  77. {//TODO
  78. }
  79. static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  80. {//TODO
  81. }
  82. static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
  83. bool ignore_tssi)
  84. {//TODO
  85. return B43_TXPWR_RES_DONE;
  86. }
  87. static void b43_chantab_radio_upload(struct b43_wldev *dev,
  88. const struct b43_nphy_channeltab_entry_rev2 *e)
  89. {
  90. b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
  91. b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
  92. b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
  93. b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
  94. b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
  95. b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
  96. b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
  97. b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
  98. b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
  99. b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
  100. b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
  101. b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
  102. b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
  103. b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
  104. b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
  105. b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
  106. b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
  107. b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
  108. b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
  109. b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
  110. b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
  111. b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
  112. b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
  113. b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
  114. b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
  115. b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
  116. b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
  117. }
  118. static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
  119. const struct b43_nphy_channeltab_entry_rev3 *e)
  120. {
  121. b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
  122. b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
  123. b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
  124. b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
  125. b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
  126. b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
  127. e->radio_syn_pll_loopfilter1);
  128. b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
  129. e->radio_syn_pll_loopfilter2);
  130. b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
  131. e->radio_syn_pll_loopfilter3);
  132. b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
  133. e->radio_syn_pll_loopfilter4);
  134. b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
  135. e->radio_syn_pll_loopfilter5);
  136. b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
  137. e->radio_syn_reserved_addr27);
  138. b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
  139. e->radio_syn_reserved_addr28);
  140. b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
  141. e->radio_syn_reserved_addr29);
  142. b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
  143. e->radio_syn_logen_vcobuf1);
  144. b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
  145. b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
  146. b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
  147. b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
  148. e->radio_rx0_lnaa_tune);
  149. b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
  150. e->radio_rx0_lnag_tune);
  151. b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
  152. e->radio_tx0_intpaa_boost_tune);
  153. b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
  154. e->radio_tx0_intpag_boost_tune);
  155. b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
  156. e->radio_tx0_pada_boost_tune);
  157. b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
  158. e->radio_tx0_padg_boost_tune);
  159. b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
  160. e->radio_tx0_pgaa_boost_tune);
  161. b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
  162. e->radio_tx0_pgag_boost_tune);
  163. b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
  164. e->radio_tx0_mixa_boost_tune);
  165. b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
  166. e->radio_tx0_mixg_boost_tune);
  167. b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
  168. e->radio_rx1_lnaa_tune);
  169. b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
  170. e->radio_rx1_lnag_tune);
  171. b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
  172. e->radio_tx1_intpaa_boost_tune);
  173. b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
  174. e->radio_tx1_intpag_boost_tune);
  175. b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
  176. e->radio_tx1_pada_boost_tune);
  177. b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
  178. e->radio_tx1_padg_boost_tune);
  179. b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
  180. e->radio_tx1_pgaa_boost_tune);
  181. b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
  182. e->radio_tx1_pgag_boost_tune);
  183. b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
  184. e->radio_tx1_mixa_boost_tune);
  185. b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
  186. e->radio_tx1_mixg_boost_tune);
  187. }
  188. /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
  189. static void b43_radio_2056_setup(struct b43_wldev *dev,
  190. const struct b43_nphy_channeltab_entry_rev3 *e)
  191. {
  192. B43_WARN_ON(dev->phy.rev < 3);
  193. b43_chantab_radio_2056_upload(dev, e);
  194. /* TODO */
  195. udelay(50);
  196. /* VCO calibration */
  197. b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
  198. b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
  199. b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
  200. b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
  201. b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
  202. udelay(300);
  203. }
  204. static void b43_chantab_phy_upload(struct b43_wldev *dev,
  205. const struct b43_phy_n_sfo_cfg *e)
  206. {
  207. b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
  208. b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
  209. b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
  210. b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
  211. b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
  212. b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
  213. }
  214. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
  215. static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
  216. {
  217. struct b43_phy_n *nphy = dev->phy.n;
  218. u8 i;
  219. u16 tmp;
  220. if (nphy->hang_avoid)
  221. b43_nphy_stay_in_carrier_search(dev, 1);
  222. nphy->txpwrctrl = enable;
  223. if (!enable) {
  224. if (dev->phy.rev >= 3)
  225. ; /* TODO */
  226. b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
  227. for (i = 0; i < 84; i++)
  228. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
  229. b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
  230. for (i = 0; i < 84; i++)
  231. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
  232. tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
  233. if (dev->phy.rev >= 3)
  234. tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
  235. b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
  236. if (dev->phy.rev >= 3) {
  237. b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
  238. b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
  239. } else {
  240. b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
  241. }
  242. if (dev->phy.rev == 2)
  243. b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
  244. ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
  245. else if (dev->phy.rev < 2)
  246. b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
  247. ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
  248. if (dev->phy.rev < 2 && 0)
  249. ; /* TODO */
  250. } else {
  251. b43err(dev->wl, "enabling tx pwr ctrl not implemented yet\n");
  252. }
  253. if (nphy->hang_avoid)
  254. b43_nphy_stay_in_carrier_search(dev, 0);
  255. }
  256. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
  257. static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
  258. {
  259. struct b43_phy_n *nphy = dev->phy.n;
  260. struct ssb_sprom *sprom = dev->dev->bus_sprom;
  261. u8 txpi[2], bbmult, i;
  262. u16 tmp, radio_gain, dac_gain;
  263. u16 freq = dev->phy.channel_freq;
  264. u32 txgain;
  265. /* u32 gaintbl; rev3+ */
  266. if (nphy->hang_avoid)
  267. b43_nphy_stay_in_carrier_search(dev, 1);
  268. if (dev->phy.rev >= 3) {
  269. txpi[0] = 40;
  270. txpi[1] = 40;
  271. } else if (sprom->revision < 4) {
  272. txpi[0] = 72;
  273. txpi[1] = 72;
  274. } else {
  275. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  276. txpi[0] = sprom->txpid2g[0];
  277. txpi[1] = sprom->txpid2g[1];
  278. } else if (freq >= 4900 && freq < 5100) {
  279. txpi[0] = sprom->txpid5gl[0];
  280. txpi[1] = sprom->txpid5gl[1];
  281. } else if (freq >= 5100 && freq < 5500) {
  282. txpi[0] = sprom->txpid5g[0];
  283. txpi[1] = sprom->txpid5g[1];
  284. } else if (freq >= 5500) {
  285. txpi[0] = sprom->txpid5gh[0];
  286. txpi[1] = sprom->txpid5gh[1];
  287. } else {
  288. txpi[0] = 91;
  289. txpi[1] = 91;
  290. }
  291. }
  292. /*
  293. for (i = 0; i < 2; i++) {
  294. nphy->txpwrindex[i].index_internal = txpi[i];
  295. nphy->txpwrindex[i].index_internal_save = txpi[i];
  296. }
  297. */
  298. for (i = 0; i < 2; i++) {
  299. if (dev->phy.rev >= 3) {
  300. /* FIXME: support 5GHz */
  301. txgain = b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
  302. radio_gain = (txgain >> 16) & 0x1FFFF;
  303. } else {
  304. txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
  305. radio_gain = (txgain >> 16) & 0x1FFF;
  306. }
  307. dac_gain = (txgain >> 8) & 0x3F;
  308. bbmult = txgain & 0xFF;
  309. if (dev->phy.rev >= 3) {
  310. if (i == 0)
  311. b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
  312. else
  313. b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
  314. } else {
  315. b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
  316. }
  317. if (i == 0)
  318. b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
  319. else
  320. b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
  321. b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D10 + i);
  322. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, radio_gain);
  323. b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
  324. tmp = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
  325. if (i == 0)
  326. tmp = (tmp & 0x00FF) | (bbmult << 8);
  327. else
  328. tmp = (tmp & 0xFF00) | bbmult;
  329. b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
  330. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, tmp);
  331. if (0)
  332. ; /* TODO */
  333. }
  334. b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
  335. if (nphy->hang_avoid)
  336. b43_nphy_stay_in_carrier_search(dev, 0);
  337. }
  338. /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
  339. static void b43_radio_2055_setup(struct b43_wldev *dev,
  340. const struct b43_nphy_channeltab_entry_rev2 *e)
  341. {
  342. B43_WARN_ON(dev->phy.rev >= 3);
  343. b43_chantab_radio_upload(dev, e);
  344. udelay(50);
  345. b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
  346. b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
  347. b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
  348. b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
  349. udelay(300);
  350. }
  351. static void b43_radio_init2055_pre(struct b43_wldev *dev)
  352. {
  353. b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
  354. ~B43_NPHY_RFCTL_CMD_PORFORCE);
  355. b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
  356. B43_NPHY_RFCTL_CMD_CHIP0PU |
  357. B43_NPHY_RFCTL_CMD_OEPORFORCE);
  358. b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
  359. B43_NPHY_RFCTL_CMD_PORFORCE);
  360. }
  361. static void b43_radio_init2055_post(struct b43_wldev *dev)
  362. {
  363. struct b43_phy_n *nphy = dev->phy.n;
  364. struct ssb_sprom *sprom = dev->dev->bus_sprom;
  365. int i;
  366. u16 val;
  367. bool workaround = false;
  368. if (sprom->revision < 4)
  369. workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
  370. && dev->dev->board_type == 0x46D
  371. && dev->dev->board_rev >= 0x41);
  372. else
  373. workaround =
  374. !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
  375. b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
  376. if (workaround) {
  377. b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
  378. b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
  379. }
  380. b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
  381. b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
  382. b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
  383. b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
  384. b43_radio_set(dev, B2055_CAL_MISC, 0x1);
  385. msleep(1);
  386. b43_radio_set(dev, B2055_CAL_MISC, 0x40);
  387. for (i = 0; i < 200; i++) {
  388. val = b43_radio_read(dev, B2055_CAL_COUT2);
  389. if (val & 0x80) {
  390. i = 0;
  391. break;
  392. }
  393. udelay(10);
  394. }
  395. if (i)
  396. b43err(dev->wl, "radio post init timeout\n");
  397. b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
  398. b43_switch_channel(dev, dev->phy.channel);
  399. b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
  400. b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
  401. b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
  402. b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
  403. b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
  404. b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
  405. if (!nphy->gain_boost) {
  406. b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
  407. b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
  408. } else {
  409. b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
  410. b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
  411. }
  412. udelay(2);
  413. }
  414. /*
  415. * Initialize a Broadcom 2055 N-radio
  416. * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
  417. */
  418. static void b43_radio_init2055(struct b43_wldev *dev)
  419. {
  420. b43_radio_init2055_pre(dev);
  421. if (b43_status(dev) < B43_STAT_INITIALIZED) {
  422. /* Follow wl, not specs. Do not force uploading all regs */
  423. b2055_upload_inittab(dev, 0, 0);
  424. } else {
  425. bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
  426. b2055_upload_inittab(dev, ghz5, 0);
  427. }
  428. b43_radio_init2055_post(dev);
  429. }
  430. static void b43_radio_init2056_pre(struct b43_wldev *dev)
  431. {
  432. b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
  433. ~B43_NPHY_RFCTL_CMD_CHIP0PU);
  434. /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
  435. b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
  436. B43_NPHY_RFCTL_CMD_OEPORFORCE);
  437. b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
  438. ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
  439. b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
  440. B43_NPHY_RFCTL_CMD_CHIP0PU);
  441. }
  442. static void b43_radio_init2056_post(struct b43_wldev *dev)
  443. {
  444. b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
  445. b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
  446. b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
  447. msleep(1);
  448. b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
  449. b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
  450. b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
  451. /*
  452. if (nphy->init_por)
  453. Call Radio 2056 Recalibrate
  454. */
  455. }
  456. /*
  457. * Initialize a Broadcom 2056 N-radio
  458. * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
  459. */
  460. static void b43_radio_init2056(struct b43_wldev *dev)
  461. {
  462. b43_radio_init2056_pre(dev);
  463. b2056_upload_inittabs(dev, 0, 0);
  464. b43_radio_init2056_post(dev);
  465. }
  466. /*
  467. * Upload the N-PHY tables.
  468. * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
  469. */
  470. static void b43_nphy_tables_init(struct b43_wldev *dev)
  471. {
  472. if (dev->phy.rev < 3)
  473. b43_nphy_rev0_1_2_tables_init(dev);
  474. else
  475. b43_nphy_rev3plus_tables_init(dev);
  476. }
  477. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
  478. static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
  479. {
  480. struct b43_phy_n *nphy = dev->phy.n;
  481. enum ieee80211_band band;
  482. u16 tmp;
  483. if (!enable) {
  484. nphy->rfctrl_intc1_save = b43_phy_read(dev,
  485. B43_NPHY_RFCTL_INTC1);
  486. nphy->rfctrl_intc2_save = b43_phy_read(dev,
  487. B43_NPHY_RFCTL_INTC2);
  488. band = b43_current_band(dev->wl);
  489. if (dev->phy.rev >= 3) {
  490. if (band == IEEE80211_BAND_5GHZ)
  491. tmp = 0x600;
  492. else
  493. tmp = 0x480;
  494. } else {
  495. if (band == IEEE80211_BAND_5GHZ)
  496. tmp = 0x180;
  497. else
  498. tmp = 0x120;
  499. }
  500. b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
  501. b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
  502. } else {
  503. b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
  504. nphy->rfctrl_intc1_save);
  505. b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
  506. nphy->rfctrl_intc2_save);
  507. }
  508. }
  509. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
  510. static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
  511. {
  512. struct b43_phy_n *nphy = dev->phy.n;
  513. u16 tmp;
  514. enum ieee80211_band band = b43_current_band(dev->wl);
  515. bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
  516. (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
  517. if (dev->phy.rev >= 3) {
  518. if (ipa) {
  519. tmp = 4;
  520. b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
  521. (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
  522. }
  523. tmp = 1;
  524. b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
  525. (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
  526. }
  527. }
  528. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
  529. static void b43_nphy_reset_cca(struct b43_wldev *dev)
  530. {
  531. u16 bbcfg;
  532. b43_phy_force_clock(dev, 1);
  533. bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
  534. b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
  535. udelay(1);
  536. b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
  537. b43_phy_force_clock(dev, 0);
  538. b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
  539. }
  540. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
  541. static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
  542. {
  543. u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
  544. mimocfg |= B43_NPHY_MIMOCFG_AUTO;
  545. if (preamble == 1)
  546. mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
  547. else
  548. mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
  549. b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
  550. }
  551. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
  552. static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
  553. {
  554. struct b43_phy_n *nphy = dev->phy.n;
  555. bool override = false;
  556. u16 chain = 0x33;
  557. if (nphy->txrx_chain == 0) {
  558. chain = 0x11;
  559. override = true;
  560. } else if (nphy->txrx_chain == 1) {
  561. chain = 0x22;
  562. override = true;
  563. }
  564. b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
  565. ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
  566. chain);
  567. if (override)
  568. b43_phy_set(dev, B43_NPHY_RFSEQMODE,
  569. B43_NPHY_RFSEQMODE_CAOVER);
  570. else
  571. b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
  572. ~B43_NPHY_RFSEQMODE_CAOVER);
  573. }
  574. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
  575. static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
  576. u16 samps, u8 time, bool wait)
  577. {
  578. int i;
  579. u16 tmp;
  580. b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
  581. b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
  582. if (wait)
  583. b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
  584. else
  585. b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
  586. b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
  587. for (i = 1000; i; i--) {
  588. tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
  589. if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
  590. est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
  591. b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
  592. est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
  593. b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
  594. est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
  595. b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
  596. est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
  597. b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
  598. est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
  599. b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
  600. est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
  601. b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
  602. return;
  603. }
  604. udelay(10);
  605. }
  606. memset(est, 0, sizeof(*est));
  607. }
  608. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
  609. static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
  610. struct b43_phy_n_iq_comp *pcomp)
  611. {
  612. if (write) {
  613. b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
  614. b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
  615. b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
  616. b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
  617. } else {
  618. pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
  619. pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
  620. pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
  621. pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
  622. }
  623. }
  624. #if 0
  625. /* Ready but not used anywhere */
  626. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
  627. static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
  628. {
  629. u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
  630. b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
  631. if (core == 0) {
  632. b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
  633. b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
  634. } else {
  635. b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
  636. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
  637. }
  638. b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
  639. b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
  640. b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
  641. b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
  642. b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
  643. b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
  644. b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
  645. b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
  646. }
  647. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
  648. static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
  649. {
  650. u8 rxval, txval;
  651. u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
  652. regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
  653. if (core == 0) {
  654. regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
  655. regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
  656. } else {
  657. regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
  658. regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
  659. }
  660. regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
  661. regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
  662. regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
  663. regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
  664. regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
  665. regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
  666. regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
  667. regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
  668. b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
  669. b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
  670. b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
  671. ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
  672. ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
  673. b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
  674. ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
  675. b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
  676. (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
  677. b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
  678. (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
  679. if (core == 0) {
  680. b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
  681. b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
  682. } else {
  683. b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
  684. b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
  685. }
  686. b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
  687. b43_nphy_rf_control_override(dev, 8, 0, 3, false);
  688. b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
  689. if (core == 0) {
  690. rxval = 1;
  691. txval = 8;
  692. } else {
  693. rxval = 4;
  694. txval = 2;
  695. }
  696. b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
  697. b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
  698. }
  699. #endif
  700. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
  701. static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
  702. {
  703. int i;
  704. s32 iq;
  705. u32 ii;
  706. u32 qq;
  707. int iq_nbits, qq_nbits;
  708. int arsh, brsh;
  709. u16 tmp, a, b;
  710. struct nphy_iq_est est;
  711. struct b43_phy_n_iq_comp old;
  712. struct b43_phy_n_iq_comp new = { };
  713. bool error = false;
  714. if (mask == 0)
  715. return;
  716. b43_nphy_rx_iq_coeffs(dev, false, &old);
  717. b43_nphy_rx_iq_coeffs(dev, true, &new);
  718. b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
  719. new = old;
  720. for (i = 0; i < 2; i++) {
  721. if (i == 0 && (mask & 1)) {
  722. iq = est.iq0_prod;
  723. ii = est.i0_pwr;
  724. qq = est.q0_pwr;
  725. } else if (i == 1 && (mask & 2)) {
  726. iq = est.iq1_prod;
  727. ii = est.i1_pwr;
  728. qq = est.q1_pwr;
  729. } else {
  730. continue;
  731. }
  732. if (ii + qq < 2) {
  733. error = true;
  734. break;
  735. }
  736. iq_nbits = fls(abs(iq));
  737. qq_nbits = fls(qq);
  738. arsh = iq_nbits - 20;
  739. if (arsh >= 0) {
  740. a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
  741. tmp = ii >> arsh;
  742. } else {
  743. a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
  744. tmp = ii << -arsh;
  745. }
  746. if (tmp == 0) {
  747. error = true;
  748. break;
  749. }
  750. a /= tmp;
  751. brsh = qq_nbits - 11;
  752. if (brsh >= 0) {
  753. b = (qq << (31 - qq_nbits));
  754. tmp = ii >> brsh;
  755. } else {
  756. b = (qq << (31 - qq_nbits));
  757. tmp = ii << -brsh;
  758. }
  759. if (tmp == 0) {
  760. error = true;
  761. break;
  762. }
  763. b = int_sqrt(b / tmp - a * a) - (1 << 10);
  764. if (i == 0 && (mask & 0x1)) {
  765. if (dev->phy.rev >= 3) {
  766. new.a0 = a & 0x3FF;
  767. new.b0 = b & 0x3FF;
  768. } else {
  769. new.a0 = b & 0x3FF;
  770. new.b0 = a & 0x3FF;
  771. }
  772. } else if (i == 1 && (mask & 0x2)) {
  773. if (dev->phy.rev >= 3) {
  774. new.a1 = a & 0x3FF;
  775. new.b1 = b & 0x3FF;
  776. } else {
  777. new.a1 = b & 0x3FF;
  778. new.b1 = a & 0x3FF;
  779. }
  780. }
  781. }
  782. if (error)
  783. new = old;
  784. b43_nphy_rx_iq_coeffs(dev, true, &new);
  785. }
  786. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
  787. static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
  788. {
  789. u16 array[4];
  790. int i;
  791. b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
  792. for (i = 0; i < 4; i++)
  793. array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
  794. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
  795. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
  796. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
  797. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
  798. }
  799. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
  800. static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
  801. const u16 *clip_st)
  802. {
  803. b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
  804. b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
  805. }
  806. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
  807. static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
  808. {
  809. clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
  810. clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
  811. }
  812. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
  813. static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
  814. {
  815. if (dev->phy.rev >= 3) {
  816. if (!init)
  817. return;
  818. if (0 /* FIXME */) {
  819. b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
  820. b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
  821. b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
  822. b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
  823. }
  824. } else {
  825. b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
  826. b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
  827. switch (dev->dev->bus_type) {
  828. #ifdef CONFIG_B43_BCMA
  829. case B43_BUS_BCMA:
  830. bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
  831. 0xFC00, 0xFC00);
  832. break;
  833. #endif
  834. #ifdef CONFIG_B43_SSB
  835. case B43_BUS_SSB:
  836. ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
  837. 0xFC00, 0xFC00);
  838. break;
  839. #endif
  840. }
  841. b43_write32(dev, B43_MMIO_MACCTL,
  842. b43_read32(dev, B43_MMIO_MACCTL) &
  843. ~B43_MACCTL_GPOUTSMSK);
  844. b43_write16(dev, B43_MMIO_GPIO_MASK,
  845. b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
  846. b43_write16(dev, B43_MMIO_GPIO_CONTROL,
  847. b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
  848. if (init) {
  849. b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
  850. b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
  851. b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
  852. b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
  853. }
  854. }
  855. }
  856. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
  857. static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
  858. {
  859. u16 tmp;
  860. if (dev->dev->core_rev == 16)
  861. b43_mac_suspend(dev);
  862. tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
  863. tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
  864. B43_NPHY_CLASSCTL_WAITEDEN);
  865. tmp &= ~mask;
  866. tmp |= (val & mask);
  867. b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
  868. if (dev->dev->core_rev == 16)
  869. b43_mac_enable(dev);
  870. return tmp;
  871. }
  872. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
  873. static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
  874. {
  875. struct b43_phy *phy = &dev->phy;
  876. struct b43_phy_n *nphy = phy->n;
  877. if (enable) {
  878. static const u16 clip[] = { 0xFFFF, 0xFFFF };
  879. if (nphy->deaf_count++ == 0) {
  880. nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
  881. b43_nphy_classifier(dev, 0x7, 0);
  882. b43_nphy_read_clip_detection(dev, nphy->clip_state);
  883. b43_nphy_write_clip_detection(dev, clip);
  884. }
  885. b43_nphy_reset_cca(dev);
  886. } else {
  887. if (--nphy->deaf_count == 0) {
  888. b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
  889. b43_nphy_write_clip_detection(dev, nphy->clip_state);
  890. }
  891. }
  892. }
  893. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
  894. static void b43_nphy_stop_playback(struct b43_wldev *dev)
  895. {
  896. struct b43_phy_n *nphy = dev->phy.n;
  897. u16 tmp;
  898. if (nphy->hang_avoid)
  899. b43_nphy_stay_in_carrier_search(dev, 1);
  900. tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
  901. if (tmp & 0x1)
  902. b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
  903. else if (tmp & 0x2)
  904. b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
  905. b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
  906. if (nphy->bb_mult_save & 0x80000000) {
  907. tmp = nphy->bb_mult_save & 0xFFFF;
  908. b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
  909. nphy->bb_mult_save = 0;
  910. }
  911. if (nphy->hang_avoid)
  912. b43_nphy_stay_in_carrier_search(dev, 0);
  913. }
  914. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
  915. static void b43_nphy_spur_workaround(struct b43_wldev *dev)
  916. {
  917. struct b43_phy_n *nphy = dev->phy.n;
  918. u8 channel = dev->phy.channel;
  919. int tone[2] = { 57, 58 };
  920. u32 noise[2] = { 0x3FF, 0x3FF };
  921. B43_WARN_ON(dev->phy.rev < 3);
  922. if (nphy->hang_avoid)
  923. b43_nphy_stay_in_carrier_search(dev, 1);
  924. if (nphy->gband_spurwar_en) {
  925. /* TODO: N PHY Adjust Analog Pfbw (7) */
  926. if (channel == 11 && dev->phy.is_40mhz)
  927. ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
  928. else
  929. ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
  930. /* TODO: N PHY Adjust CRS Min Power (0x1E) */
  931. }
  932. if (nphy->aband_spurwar_en) {
  933. if (channel == 54) {
  934. tone[0] = 0x20;
  935. noise[0] = 0x25F;
  936. } else if (channel == 38 || channel == 102 || channel == 118) {
  937. if (0 /* FIXME */) {
  938. tone[0] = 0x20;
  939. noise[0] = 0x21F;
  940. } else {
  941. tone[0] = 0;
  942. noise[0] = 0;
  943. }
  944. } else if (channel == 134) {
  945. tone[0] = 0x20;
  946. noise[0] = 0x21F;
  947. } else if (channel == 151) {
  948. tone[0] = 0x10;
  949. noise[0] = 0x23F;
  950. } else if (channel == 153 || channel == 161) {
  951. tone[0] = 0x30;
  952. noise[0] = 0x23F;
  953. } else {
  954. tone[0] = 0;
  955. noise[0] = 0;
  956. }
  957. if (!tone[0] && !noise[0])
  958. ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
  959. else
  960. ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
  961. }
  962. if (nphy->hang_avoid)
  963. b43_nphy_stay_in_carrier_search(dev, 0);
  964. }
  965. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
  966. static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
  967. {
  968. struct b43_phy_n *nphy = dev->phy.n;
  969. u8 i;
  970. s16 tmp;
  971. u16 data[4];
  972. s16 gain[2];
  973. u16 minmax[2];
  974. static const u16 lna_gain[4] = { -2, 10, 19, 25 };
  975. if (nphy->hang_avoid)
  976. b43_nphy_stay_in_carrier_search(dev, 1);
  977. if (nphy->gain_boost) {
  978. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  979. gain[0] = 6;
  980. gain[1] = 6;
  981. } else {
  982. tmp = 40370 - 315 * dev->phy.channel;
  983. gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
  984. tmp = 23242 - 224 * dev->phy.channel;
  985. gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
  986. }
  987. } else {
  988. gain[0] = 0;
  989. gain[1] = 0;
  990. }
  991. for (i = 0; i < 2; i++) {
  992. if (nphy->elna_gain_config) {
  993. data[0] = 19 + gain[i];
  994. data[1] = 25 + gain[i];
  995. data[2] = 25 + gain[i];
  996. data[3] = 25 + gain[i];
  997. } else {
  998. data[0] = lna_gain[0] + gain[i];
  999. data[1] = lna_gain[1] + gain[i];
  1000. data[2] = lna_gain[2] + gain[i];
  1001. data[3] = lna_gain[3] + gain[i];
  1002. }
  1003. b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
  1004. minmax[i] = 23 + gain[i];
  1005. }
  1006. b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
  1007. minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
  1008. b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
  1009. minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
  1010. if (nphy->hang_avoid)
  1011. b43_nphy_stay_in_carrier_search(dev, 0);
  1012. }
  1013. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
  1014. static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
  1015. {
  1016. struct b43_phy_n *nphy = dev->phy.n;
  1017. struct ssb_sprom *sprom = dev->dev->bus_sprom;
  1018. /* PHY rev 0, 1, 2 */
  1019. u8 i, j;
  1020. u8 code;
  1021. u16 tmp;
  1022. u8 rfseq_events[3] = { 6, 8, 7 };
  1023. u8 rfseq_delays[3] = { 10, 30, 1 };
  1024. /* PHY rev >= 3 */
  1025. bool ghz5;
  1026. bool ext_lna;
  1027. u16 rssi_gain;
  1028. struct nphy_gain_ctl_workaround_entry *e;
  1029. u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
  1030. u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
  1031. if (dev->phy.rev >= 3) {
  1032. /* Prepare values */
  1033. ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
  1034. & B43_NPHY_BANDCTL_5GHZ;
  1035. ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
  1036. e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
  1037. if (ghz5 && dev->phy.rev >= 5)
  1038. rssi_gain = 0x90;
  1039. else
  1040. rssi_gain = 0x50;
  1041. b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
  1042. /* Set Clip 2 detect */
  1043. b43_phy_set(dev, B43_NPHY_C1_CGAINI,
  1044. B43_NPHY_C1_CGAINI_CL2DETECT);
  1045. b43_phy_set(dev, B43_NPHY_C2_CGAINI,
  1046. B43_NPHY_C2_CGAINI_CL2DETECT);
  1047. b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
  1048. 0x17);
  1049. b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
  1050. 0x17);
  1051. b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
  1052. b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
  1053. b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
  1054. b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
  1055. b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
  1056. rssi_gain);
  1057. b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
  1058. rssi_gain);
  1059. b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
  1060. 0x17);
  1061. b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
  1062. 0x17);
  1063. b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
  1064. b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
  1065. b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
  1066. b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
  1067. b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
  1068. b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
  1069. b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
  1070. b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
  1071. b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
  1072. b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
  1073. b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
  1074. b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
  1075. b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
  1076. b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
  1077. b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
  1078. b43_phy_write(dev, 0x2A7, e->init_gain);
  1079. b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
  1080. e->rfseq_init);
  1081. b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
  1082. /* TODO: check defines. Do not match variables names */
  1083. b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
  1084. b43_phy_write(dev, 0x2A9, e->cliphi_gain);
  1085. b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
  1086. b43_phy_write(dev, 0x2AB, e->clipmd_gain);
  1087. b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
  1088. b43_phy_write(dev, 0x2AD, e->cliplo_gain);
  1089. b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
  1090. b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
  1091. b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
  1092. b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
  1093. b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
  1094. b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
  1095. ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
  1096. b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
  1097. ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
  1098. b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
  1099. } else {
  1100. /* Set Clip 2 detect */
  1101. b43_phy_set(dev, B43_NPHY_C1_CGAINI,
  1102. B43_NPHY_C1_CGAINI_CL2DETECT);
  1103. b43_phy_set(dev, B43_NPHY_C2_CGAINI,
  1104. B43_NPHY_C2_CGAINI_CL2DETECT);
  1105. /* Set narrowband clip threshold */
  1106. b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
  1107. b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
  1108. if (!dev->phy.is_40mhz) {
  1109. /* Set dwell lengths */
  1110. b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
  1111. b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
  1112. b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
  1113. b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
  1114. }
  1115. /* Set wideband clip 2 threshold */
  1116. b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
  1117. ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
  1118. 21);
  1119. b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
  1120. ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
  1121. 21);
  1122. if (!dev->phy.is_40mhz) {
  1123. b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
  1124. ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
  1125. b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
  1126. ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
  1127. b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
  1128. ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
  1129. b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
  1130. ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
  1131. }
  1132. b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
  1133. if (nphy->gain_boost) {
  1134. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
  1135. dev->phy.is_40mhz)
  1136. code = 4;
  1137. else
  1138. code = 5;
  1139. } else {
  1140. code = dev->phy.is_40mhz ? 6 : 7;
  1141. }
  1142. /* Set HPVGA2 index */
  1143. b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
  1144. ~B43_NPHY_C1_INITGAIN_HPVGA2,
  1145. code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
  1146. b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
  1147. ~B43_NPHY_C2_INITGAIN_HPVGA2,
  1148. code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
  1149. b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
  1150. /* specs say about 2 loops, but wl does 4 */
  1151. for (i = 0; i < 4; i++)
  1152. b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
  1153. (code << 8 | 0x7C));
  1154. b43_nphy_adjust_lna_gain_table(dev);
  1155. if (nphy->elna_gain_config) {
  1156. b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
  1157. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
  1158. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
  1159. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
  1160. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
  1161. b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
  1162. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
  1163. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
  1164. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
  1165. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
  1166. b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
  1167. /* specs say about 2 loops, but wl does 4 */
  1168. for (i = 0; i < 4; i++)
  1169. b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
  1170. (code << 8 | 0x74));
  1171. }
  1172. if (dev->phy.rev == 2) {
  1173. for (i = 0; i < 4; i++) {
  1174. b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
  1175. (0x0400 * i) + 0x0020);
  1176. for (j = 0; j < 21; j++) {
  1177. tmp = j * (i < 2 ? 3 : 1);
  1178. b43_phy_write(dev,
  1179. B43_NPHY_TABLE_DATALO, tmp);
  1180. }
  1181. }
  1182. }
  1183. b43_nphy_set_rf_sequence(dev, 5,
  1184. rfseq_events, rfseq_delays, 3);
  1185. b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
  1186. ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
  1187. 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
  1188. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
  1189. b43_phy_maskset(dev, B43_PHY_N(0xC5D),
  1190. 0xFF80, 4);
  1191. }
  1192. }
  1193. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
  1194. static void b43_nphy_workarounds(struct b43_wldev *dev)
  1195. {
  1196. struct ssb_sprom *sprom = dev->dev->bus_sprom;
  1197. struct b43_phy *phy = &dev->phy;
  1198. struct b43_phy_n *nphy = phy->n;
  1199. u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
  1200. u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
  1201. u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
  1202. u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
  1203. u16 tmp16;
  1204. u32 tmp32;
  1205. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
  1206. b43_nphy_classifier(dev, 1, 0);
  1207. else
  1208. b43_nphy_classifier(dev, 1, 1);
  1209. if (nphy->hang_avoid)
  1210. b43_nphy_stay_in_carrier_search(dev, 1);
  1211. b43_phy_set(dev, B43_NPHY_IQFLIP,
  1212. B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
  1213. if (dev->phy.rev >= 3) {
  1214. tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
  1215. tmp32 &= 0xffffff;
  1216. b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
  1217. b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
  1218. b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
  1219. b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
  1220. b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
  1221. b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
  1222. b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
  1223. b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
  1224. b43_phy_write(dev, 0x2AE, 0x000C);
  1225. /* TODO */
  1226. tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
  1227. 0x2 : 0x9C40;
  1228. b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
  1229. b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
  1230. b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
  1231. b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
  1232. b43_nphy_gain_ctrl_workarounds(dev);
  1233. b43_ntab_write(dev, B43_NTAB32(8, 0), 2);
  1234. b43_ntab_write(dev, B43_NTAB32(8, 16), 2);
  1235. /* TODO */
  1236. b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
  1237. b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
  1238. b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
  1239. b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
  1240. b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
  1241. b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
  1242. b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
  1243. b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
  1244. b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
  1245. b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
  1246. /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
  1247. if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
  1248. b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
  1249. (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
  1250. b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
  1251. tmp32 = 0x00088888;
  1252. else
  1253. tmp32 = 0x88888888;
  1254. b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
  1255. b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
  1256. b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
  1257. if (dev->phy.rev == 4 &&
  1258. b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
  1259. b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
  1260. 0x70);
  1261. b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
  1262. 0x70);
  1263. }
  1264. b43_phy_write(dev, 0x224, 0x039C);
  1265. b43_phy_write(dev, 0x225, 0x0357);
  1266. b43_phy_write(dev, 0x226, 0x0317);
  1267. b43_phy_write(dev, 0x227, 0x02D7);
  1268. b43_phy_write(dev, 0x228, 0x039C);
  1269. b43_phy_write(dev, 0x229, 0x0357);
  1270. b43_phy_write(dev, 0x22A, 0x0317);
  1271. b43_phy_write(dev, 0x22B, 0x02D7);
  1272. b43_phy_write(dev, 0x22C, 0x039C);
  1273. b43_phy_write(dev, 0x22D, 0x0357);
  1274. b43_phy_write(dev, 0x22E, 0x0317);
  1275. b43_phy_write(dev, 0x22F, 0x02D7);
  1276. } else {
  1277. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
  1278. nphy->band5g_pwrgain) {
  1279. b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
  1280. b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
  1281. } else {
  1282. b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
  1283. b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
  1284. }
  1285. b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
  1286. b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
  1287. b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
  1288. b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
  1289. if (dev->phy.rev < 2) {
  1290. b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
  1291. b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
  1292. b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
  1293. b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
  1294. b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
  1295. b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
  1296. }
  1297. b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
  1298. b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
  1299. b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
  1300. b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
  1301. if (sprom->boardflags2_lo & 0x100 &&
  1302. dev->dev->board_type == 0x8B) {
  1303. delays1[0] = 0x1;
  1304. delays1[5] = 0x14;
  1305. }
  1306. b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
  1307. b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
  1308. b43_nphy_gain_ctrl_workarounds(dev);
  1309. if (dev->phy.rev < 2) {
  1310. if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
  1311. b43_hf_write(dev, b43_hf_read(dev) |
  1312. B43_HF_MLADVW);
  1313. } else if (dev->phy.rev == 2) {
  1314. b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
  1315. b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
  1316. }
  1317. if (dev->phy.rev < 2)
  1318. b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
  1319. ~B43_NPHY_SCRAM_SIGCTL_SCM);
  1320. /* Set phase track alpha and beta */
  1321. b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
  1322. b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
  1323. b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
  1324. b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
  1325. b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
  1326. b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
  1327. b43_phy_mask(dev, B43_NPHY_PIL_DW1,
  1328. ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
  1329. b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
  1330. b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
  1331. b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
  1332. if (dev->phy.rev == 2)
  1333. b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
  1334. B43_NPHY_FINERX2_CGC_DECGC);
  1335. }
  1336. if (nphy->hang_avoid)
  1337. b43_nphy_stay_in_carrier_search(dev, 0);
  1338. }
  1339. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
  1340. static int b43_nphy_load_samples(struct b43_wldev *dev,
  1341. struct b43_c32 *samples, u16 len) {
  1342. struct b43_phy_n *nphy = dev->phy.n;
  1343. u16 i;
  1344. u32 *data;
  1345. data = kzalloc(len * sizeof(u32), GFP_KERNEL);
  1346. if (!data) {
  1347. b43err(dev->wl, "allocation for samples loading failed\n");
  1348. return -ENOMEM;
  1349. }
  1350. if (nphy->hang_avoid)
  1351. b43_nphy_stay_in_carrier_search(dev, 1);
  1352. for (i = 0; i < len; i++) {
  1353. data[i] = (samples[i].i & 0x3FF << 10);
  1354. data[i] |= samples[i].q & 0x3FF;
  1355. }
  1356. b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
  1357. kfree(data);
  1358. if (nphy->hang_avoid)
  1359. b43_nphy_stay_in_carrier_search(dev, 0);
  1360. return 0;
  1361. }
  1362. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
  1363. static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
  1364. bool test)
  1365. {
  1366. int i;
  1367. u16 bw, len, rot, angle;
  1368. struct b43_c32 *samples;
  1369. bw = (dev->phy.is_40mhz) ? 40 : 20;
  1370. len = bw << 3;
  1371. if (test) {
  1372. if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
  1373. bw = 82;
  1374. else
  1375. bw = 80;
  1376. if (dev->phy.is_40mhz)
  1377. bw <<= 1;
  1378. len = bw << 1;
  1379. }
  1380. samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
  1381. if (!samples) {
  1382. b43err(dev->wl, "allocation for samples generation failed\n");
  1383. return 0;
  1384. }
  1385. rot = (((freq * 36) / bw) << 16) / 100;
  1386. angle = 0;
  1387. for (i = 0; i < len; i++) {
  1388. samples[i] = b43_cordic(angle);
  1389. angle += rot;
  1390. samples[i].q = CORDIC_CONVERT(samples[i].q * max);
  1391. samples[i].i = CORDIC_CONVERT(samples[i].i * max);
  1392. }
  1393. i = b43_nphy_load_samples(dev, samples, len);
  1394. kfree(samples);
  1395. return (i < 0) ? 0 : len;
  1396. }
  1397. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
  1398. static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
  1399. u16 wait, bool iqmode, bool dac_test)
  1400. {
  1401. struct b43_phy_n *nphy = dev->phy.n;
  1402. int i;
  1403. u16 seq_mode;
  1404. u32 tmp;
  1405. if (nphy->hang_avoid)
  1406. b43_nphy_stay_in_carrier_search(dev, true);
  1407. if ((nphy->bb_mult_save & 0x80000000) == 0) {
  1408. tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
  1409. nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
  1410. }
  1411. if (!dev->phy.is_40mhz)
  1412. tmp = 0x6464;
  1413. else
  1414. tmp = 0x4747;
  1415. b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
  1416. if (nphy->hang_avoid)
  1417. b43_nphy_stay_in_carrier_search(dev, false);
  1418. b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
  1419. if (loops != 0xFFFF)
  1420. b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
  1421. else
  1422. b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
  1423. b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
  1424. seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
  1425. b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
  1426. if (iqmode) {
  1427. b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
  1428. b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
  1429. } else {
  1430. if (dac_test)
  1431. b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
  1432. else
  1433. b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
  1434. }
  1435. for (i = 0; i < 100; i++) {
  1436. if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
  1437. i = 0;
  1438. break;
  1439. }
  1440. udelay(10);
  1441. }
  1442. if (i)
  1443. b43err(dev->wl, "run samples timeout\n");
  1444. b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
  1445. }
  1446. /*
  1447. * Transmits a known value for LO calibration
  1448. * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
  1449. */
  1450. static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
  1451. bool iqmode, bool dac_test)
  1452. {
  1453. u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
  1454. if (samp == 0)
  1455. return -1;
  1456. b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
  1457. return 0;
  1458. }
  1459. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
  1460. static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
  1461. {
  1462. struct b43_phy_n *nphy = dev->phy.n;
  1463. int i, j;
  1464. u32 tmp;
  1465. u32 cur_real, cur_imag, real_part, imag_part;
  1466. u16 buffer[7];
  1467. if (nphy->hang_avoid)
  1468. b43_nphy_stay_in_carrier_search(dev, true);
  1469. b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
  1470. for (i = 0; i < 2; i++) {
  1471. tmp = ((buffer[i * 2] & 0x3FF) << 10) |
  1472. (buffer[i * 2 + 1] & 0x3FF);
  1473. b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
  1474. (((i + 26) << 10) | 320));
  1475. for (j = 0; j < 128; j++) {
  1476. b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
  1477. ((tmp >> 16) & 0xFFFF));
  1478. b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
  1479. (tmp & 0xFFFF));
  1480. }
  1481. }
  1482. for (i = 0; i < 2; i++) {
  1483. tmp = buffer[5 + i];
  1484. real_part = (tmp >> 8) & 0xFF;
  1485. imag_part = (tmp & 0xFF);
  1486. b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
  1487. (((i + 26) << 10) | 448));
  1488. if (dev->phy.rev >= 3) {
  1489. cur_real = real_part;
  1490. cur_imag = imag_part;
  1491. tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
  1492. }
  1493. for (j = 0; j < 128; j++) {
  1494. if (dev->phy.rev < 3) {
  1495. cur_real = (real_part * loscale[j] + 128) >> 8;
  1496. cur_imag = (imag_part * loscale[j] + 128) >> 8;
  1497. tmp = ((cur_real & 0xFF) << 8) |
  1498. (cur_imag & 0xFF);
  1499. }
  1500. b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
  1501. ((tmp >> 16) & 0xFFFF));
  1502. b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
  1503. (tmp & 0xFFFF));
  1504. }
  1505. }
  1506. if (dev->phy.rev >= 3) {
  1507. b43_shm_write16(dev, B43_SHM_SHARED,
  1508. B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
  1509. b43_shm_write16(dev, B43_SHM_SHARED,
  1510. B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
  1511. }
  1512. if (nphy->hang_avoid)
  1513. b43_nphy_stay_in_carrier_search(dev, false);
  1514. }
  1515. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
  1516. static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
  1517. u8 *events, u8 *delays, u8 length)
  1518. {
  1519. struct b43_phy_n *nphy = dev->phy.n;
  1520. u8 i;
  1521. u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
  1522. u16 offset1 = cmd << 4;
  1523. u16 offset2 = offset1 + 0x80;
  1524. if (nphy->hang_avoid)
  1525. b43_nphy_stay_in_carrier_search(dev, true);
  1526. b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
  1527. b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
  1528. for (i = length; i < 16; i++) {
  1529. b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
  1530. b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
  1531. }
  1532. if (nphy->hang_avoid)
  1533. b43_nphy_stay_in_carrier_search(dev, false);
  1534. }
  1535. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
  1536. static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
  1537. enum b43_nphy_rf_sequence seq)
  1538. {
  1539. static const u16 trigger[] = {
  1540. [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
  1541. [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
  1542. [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
  1543. [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
  1544. [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
  1545. [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
  1546. };
  1547. int i;
  1548. u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
  1549. B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
  1550. b43_phy_set(dev, B43_NPHY_RFSEQMODE,
  1551. B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
  1552. b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
  1553. for (i = 0; i < 200; i++) {
  1554. if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
  1555. goto ok;
  1556. msleep(1);
  1557. }
  1558. b43err(dev->wl, "RF sequence status timeout\n");
  1559. ok:
  1560. b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
  1561. }
  1562. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
  1563. static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
  1564. u16 value, u8 core, bool off)
  1565. {
  1566. int i;
  1567. u8 index = fls(field);
  1568. u8 addr, en_addr, val_addr;
  1569. /* we expect only one bit set */
  1570. B43_WARN_ON(field & (~(1 << (index - 1))));
  1571. if (dev->phy.rev >= 3) {
  1572. const struct nphy_rf_control_override_rev3 *rf_ctrl;
  1573. for (i = 0; i < 2; i++) {
  1574. if (index == 0 || index == 16) {
  1575. b43err(dev->wl,
  1576. "Unsupported RF Ctrl Override call\n");
  1577. return;
  1578. }
  1579. rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
  1580. en_addr = B43_PHY_N((i == 0) ?
  1581. rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
  1582. val_addr = B43_PHY_N((i == 0) ?
  1583. rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
  1584. if (off) {
  1585. b43_phy_mask(dev, en_addr, ~(field));
  1586. b43_phy_mask(dev, val_addr,
  1587. ~(rf_ctrl->val_mask));
  1588. } else {
  1589. if (core == 0 || ((1 << core) & i) != 0) {
  1590. b43_phy_set(dev, en_addr, field);
  1591. b43_phy_maskset(dev, val_addr,
  1592. ~(rf_ctrl->val_mask),
  1593. (value << rf_ctrl->val_shift));
  1594. }
  1595. }
  1596. }
  1597. } else {
  1598. const struct nphy_rf_control_override_rev2 *rf_ctrl;
  1599. if (off) {
  1600. b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
  1601. value = 0;
  1602. } else {
  1603. b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
  1604. }
  1605. for (i = 0; i < 2; i++) {
  1606. if (index <= 1 || index == 16) {
  1607. b43err(dev->wl,
  1608. "Unsupported RF Ctrl Override call\n");
  1609. return;
  1610. }
  1611. if (index == 2 || index == 10 ||
  1612. (index >= 13 && index <= 15)) {
  1613. core = 1;
  1614. }
  1615. rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
  1616. addr = B43_PHY_N((i == 0) ?
  1617. rf_ctrl->addr0 : rf_ctrl->addr1);
  1618. if ((core & (1 << i)) != 0)
  1619. b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
  1620. (value << rf_ctrl->shift));
  1621. b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
  1622. b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
  1623. B43_NPHY_RFCTL_CMD_START);
  1624. udelay(1);
  1625. b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
  1626. }
  1627. }
  1628. }
  1629. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
  1630. static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
  1631. u16 value, u8 core)
  1632. {
  1633. u8 i, j;
  1634. u16 reg, tmp, val;
  1635. B43_WARN_ON(dev->phy.rev < 3);
  1636. B43_WARN_ON(field > 4);
  1637. for (i = 0; i < 2; i++) {
  1638. if ((core == 1 && i == 1) || (core == 2 && !i))
  1639. continue;
  1640. reg = (i == 0) ?
  1641. B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
  1642. b43_phy_mask(dev, reg, 0xFBFF);
  1643. switch (field) {
  1644. case 0:
  1645. b43_phy_write(dev, reg, 0);
  1646. b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
  1647. break;
  1648. case 1:
  1649. if (!i) {
  1650. b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
  1651. 0xFC3F, (value << 6));
  1652. b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
  1653. 0xFFFE, 1);
  1654. b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
  1655. B43_NPHY_RFCTL_CMD_START);
  1656. for (j = 0; j < 100; j++) {
  1657. if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
  1658. j = 0;
  1659. break;
  1660. }
  1661. udelay(10);
  1662. }
  1663. if (j)
  1664. b43err(dev->wl,
  1665. "intc override timeout\n");
  1666. b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
  1667. 0xFFFE);
  1668. } else {
  1669. b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
  1670. 0xFC3F, (value << 6));
  1671. b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
  1672. 0xFFFE, 1);
  1673. b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
  1674. B43_NPHY_RFCTL_CMD_RXTX);
  1675. for (j = 0; j < 100; j++) {
  1676. if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
  1677. j = 0;
  1678. break;
  1679. }
  1680. udelay(10);
  1681. }
  1682. if (j)
  1683. b43err(dev->wl,
  1684. "intc override timeout\n");
  1685. b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
  1686. 0xFFFE);
  1687. }
  1688. break;
  1689. case 2:
  1690. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
  1691. tmp = 0x0020;
  1692. val = value << 5;
  1693. } else {
  1694. tmp = 0x0010;
  1695. val = value << 4;
  1696. }
  1697. b43_phy_maskset(dev, reg, ~tmp, val);
  1698. break;
  1699. case 3:
  1700. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
  1701. tmp = 0x0001;
  1702. val = value;
  1703. } else {
  1704. tmp = 0x0004;
  1705. val = value << 2;
  1706. }
  1707. b43_phy_maskset(dev, reg, ~tmp, val);
  1708. break;
  1709. case 4:
  1710. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
  1711. tmp = 0x0002;
  1712. val = value << 1;
  1713. } else {
  1714. tmp = 0x0008;
  1715. val = value << 3;
  1716. }
  1717. b43_phy_maskset(dev, reg, ~tmp, val);
  1718. break;
  1719. }
  1720. }
  1721. }
  1722. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
  1723. static void b43_nphy_bphy_init(struct b43_wldev *dev)
  1724. {
  1725. unsigned int i;
  1726. u16 val;
  1727. val = 0x1E1F;
  1728. for (i = 0; i < 16; i++) {
  1729. b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
  1730. val -= 0x202;
  1731. }
  1732. val = 0x3E3F;
  1733. for (i = 0; i < 16; i++) {
  1734. b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
  1735. val -= 0x202;
  1736. }
  1737. b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
  1738. }
  1739. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
  1740. static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
  1741. s8 offset, u8 core, u8 rail,
  1742. enum b43_nphy_rssi_type type)
  1743. {
  1744. u16 tmp;
  1745. bool core1or5 = (core == 1) || (core == 5);
  1746. bool core2or5 = (core == 2) || (core == 5);
  1747. offset = clamp_val(offset, -32, 31);
  1748. tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
  1749. if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
  1750. b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
  1751. if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
  1752. b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
  1753. if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
  1754. b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
  1755. if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
  1756. b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
  1757. if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
  1758. b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
  1759. if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
  1760. b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
  1761. if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
  1762. b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
  1763. if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
  1764. b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
  1765. if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
  1766. b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
  1767. if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
  1768. b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
  1769. if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
  1770. b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
  1771. if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
  1772. b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
  1773. if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
  1774. b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
  1775. if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
  1776. b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
  1777. if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
  1778. b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
  1779. if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
  1780. b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
  1781. if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
  1782. b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
  1783. if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
  1784. b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
  1785. if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
  1786. b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
  1787. if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
  1788. b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
  1789. if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
  1790. b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
  1791. if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
  1792. b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
  1793. if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
  1794. b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
  1795. if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
  1796. b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
  1797. }
  1798. static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
  1799. {
  1800. u16 val;
  1801. if (type < 3)
  1802. val = 0;
  1803. else if (type == 6)
  1804. val = 1;
  1805. else if (type == 3)
  1806. val = 2;
  1807. else
  1808. val = 3;
  1809. val = (val << 12) | (val << 14);
  1810. b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
  1811. b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
  1812. if (type < 3) {
  1813. b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
  1814. (type + 1) << 4);
  1815. b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
  1816. (type + 1) << 4);
  1817. }
  1818. if (code == 0) {
  1819. b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
  1820. if (type < 3) {
  1821. b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
  1822. ~(B43_NPHY_RFCTL_CMD_RXEN |
  1823. B43_NPHY_RFCTL_CMD_CORESEL));
  1824. b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
  1825. ~(0x1 << 12 |
  1826. 0x1 << 5 |
  1827. 0x1 << 1 |
  1828. 0x1));
  1829. b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
  1830. ~B43_NPHY_RFCTL_CMD_START);
  1831. udelay(20);
  1832. b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
  1833. }
  1834. } else {
  1835. b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
  1836. if (type < 3) {
  1837. b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
  1838. ~(B43_NPHY_RFCTL_CMD_RXEN |
  1839. B43_NPHY_RFCTL_CMD_CORESEL),
  1840. (B43_NPHY_RFCTL_CMD_RXEN |
  1841. code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
  1842. b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
  1843. (0x1 << 12 |
  1844. 0x1 << 5 |
  1845. 0x1 << 1 |
  1846. 0x1));
  1847. b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
  1848. B43_NPHY_RFCTL_CMD_START);
  1849. udelay(20);
  1850. b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
  1851. }
  1852. }
  1853. }
  1854. static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
  1855. {
  1856. struct b43_phy_n *nphy = dev->phy.n;
  1857. u8 i;
  1858. u16 reg, val;
  1859. if (code == 0) {
  1860. b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
  1861. b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
  1862. b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
  1863. b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
  1864. b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
  1865. b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
  1866. b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
  1867. b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
  1868. } else {
  1869. for (i = 0; i < 2; i++) {
  1870. if ((code == 1 && i == 1) || (code == 2 && !i))
  1871. continue;
  1872. reg = (i == 0) ?
  1873. B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
  1874. b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
  1875. if (type < 3) {
  1876. reg = (i == 0) ?
  1877. B43_NPHY_AFECTL_C1 :
  1878. B43_NPHY_AFECTL_C2;
  1879. b43_phy_maskset(dev, reg, 0xFCFF, 0);
  1880. reg = (i == 0) ?
  1881. B43_NPHY_RFCTL_LUT_TRSW_UP1 :
  1882. B43_NPHY_RFCTL_LUT_TRSW_UP2;
  1883. b43_phy_maskset(dev, reg, 0xFFC3, 0);
  1884. if (type == 0)
  1885. val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
  1886. else if (type == 1)
  1887. val = 16;
  1888. else
  1889. val = 32;
  1890. b43_phy_set(dev, reg, val);
  1891. reg = (i == 0) ?
  1892. B43_NPHY_TXF_40CO_B1S0 :
  1893. B43_NPHY_TXF_40CO_B32S1;
  1894. b43_phy_set(dev, reg, 0x0020);
  1895. } else {
  1896. if (type == 6)
  1897. val = 0x0100;
  1898. else if (type == 3)
  1899. val = 0x0200;
  1900. else
  1901. val = 0x0300;
  1902. reg = (i == 0) ?
  1903. B43_NPHY_AFECTL_C1 :
  1904. B43_NPHY_AFECTL_C2;
  1905. b43_phy_maskset(dev, reg, 0xFCFF, val);
  1906. b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
  1907. if (type != 3 && type != 6) {
  1908. enum ieee80211_band band =
  1909. b43_current_band(dev->wl);
  1910. if ((nphy->ipa2g_on &&
  1911. band == IEEE80211_BAND_2GHZ) ||
  1912. (nphy->ipa5g_on &&
  1913. band == IEEE80211_BAND_5GHZ))
  1914. val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
  1915. else
  1916. val = 0x11;
  1917. reg = (i == 0) ? 0x2000 : 0x3000;
  1918. reg |= B2055_PADDRV;
  1919. b43_radio_write16(dev, reg, val);
  1920. reg = (i == 0) ?
  1921. B43_NPHY_AFECTL_OVER1 :
  1922. B43_NPHY_AFECTL_OVER;
  1923. b43_phy_set(dev, reg, 0x0200);
  1924. }
  1925. }
  1926. }
  1927. }
  1928. }
  1929. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
  1930. static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
  1931. {
  1932. if (dev->phy.rev >= 3)
  1933. b43_nphy_rev3_rssi_select(dev, code, type);
  1934. else
  1935. b43_nphy_rev2_rssi_select(dev, code, type);
  1936. }
  1937. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
  1938. static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
  1939. {
  1940. int i;
  1941. for (i = 0; i < 2; i++) {
  1942. if (type == 2) {
  1943. if (i == 0) {
  1944. b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
  1945. 0xFC, buf[0]);
  1946. b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
  1947. 0xFC, buf[1]);
  1948. } else {
  1949. b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
  1950. 0xFC, buf[2 * i]);
  1951. b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
  1952. 0xFC, buf[2 * i + 1]);
  1953. }
  1954. } else {
  1955. if (i == 0)
  1956. b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
  1957. 0xF3, buf[0] << 2);
  1958. else
  1959. b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
  1960. 0xF3, buf[2 * i + 1] << 2);
  1961. }
  1962. }
  1963. }
  1964. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
  1965. static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
  1966. u8 nsamp)
  1967. {
  1968. int i;
  1969. int out;
  1970. u16 save_regs_phy[9];
  1971. u16 s[2];
  1972. if (dev->phy.rev >= 3) {
  1973. save_regs_phy[0] = b43_phy_read(dev,
  1974. B43_NPHY_RFCTL_LUT_TRSW_UP1);
  1975. save_regs_phy[1] = b43_phy_read(dev,
  1976. B43_NPHY_RFCTL_LUT_TRSW_UP2);
  1977. save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
  1978. save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
  1979. save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
  1980. save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
  1981. save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
  1982. save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
  1983. save_regs_phy[8] = 0;
  1984. } else {
  1985. save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
  1986. save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
  1987. save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
  1988. save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
  1989. save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
  1990. save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
  1991. save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
  1992. save_regs_phy[7] = 0;
  1993. save_regs_phy[8] = 0;
  1994. }
  1995. b43_nphy_rssi_select(dev, 5, type);
  1996. if (dev->phy.rev < 2) {
  1997. save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
  1998. b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
  1999. }
  2000. for (i = 0; i < 4; i++)
  2001. buf[i] = 0;
  2002. for (i = 0; i < nsamp; i++) {
  2003. if (dev->phy.rev < 2) {
  2004. s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
  2005. s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
  2006. } else {
  2007. s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
  2008. s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
  2009. }
  2010. buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
  2011. buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
  2012. buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
  2013. buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
  2014. }
  2015. out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
  2016. (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
  2017. if (dev->phy.rev < 2)
  2018. b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
  2019. if (dev->phy.rev >= 3) {
  2020. b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
  2021. save_regs_phy[0]);
  2022. b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
  2023. save_regs_phy[1]);
  2024. b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
  2025. b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
  2026. b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
  2027. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
  2028. b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
  2029. b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
  2030. } else {
  2031. b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
  2032. b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
  2033. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
  2034. b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
  2035. b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
  2036. b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
  2037. b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
  2038. }
  2039. return out;
  2040. }
  2041. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
  2042. static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
  2043. {
  2044. int i, j;
  2045. u8 state[4];
  2046. u8 code, val;
  2047. u16 class, override;
  2048. u8 regs_save_radio[2];
  2049. u16 regs_save_phy[2];
  2050. s8 offset[4];
  2051. u8 core;
  2052. u8 rail;
  2053. u16 clip_state[2];
  2054. u16 clip_off[2] = { 0xFFFF, 0xFFFF };
  2055. s32 results_min[4] = { };
  2056. u8 vcm_final[4] = { };
  2057. s32 results[4][4] = { };
  2058. s32 miniq[4][2] = { };
  2059. if (type == 2) {
  2060. code = 0;
  2061. val = 6;
  2062. } else if (type < 2) {
  2063. code = 25;
  2064. val = 4;
  2065. } else {
  2066. B43_WARN_ON(1);
  2067. return;
  2068. }
  2069. class = b43_nphy_classifier(dev, 0, 0);
  2070. b43_nphy_classifier(dev, 7, 4);
  2071. b43_nphy_read_clip_detection(dev, clip_state);
  2072. b43_nphy_write_clip_detection(dev, clip_off);
  2073. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
  2074. override = 0x140;
  2075. else
  2076. override = 0x110;
  2077. regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
  2078. regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
  2079. b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
  2080. b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
  2081. regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
  2082. regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
  2083. b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
  2084. b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
  2085. state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
  2086. state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
  2087. b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
  2088. b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
  2089. state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
  2090. state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
  2091. b43_nphy_rssi_select(dev, 5, type);
  2092. b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
  2093. b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
  2094. for (i = 0; i < 4; i++) {
  2095. u8 tmp[4];
  2096. for (j = 0; j < 4; j++)
  2097. tmp[j] = i;
  2098. if (type != 1)
  2099. b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
  2100. b43_nphy_poll_rssi(dev, type, results[i], 8);
  2101. if (type < 2)
  2102. for (j = 0; j < 2; j++)
  2103. miniq[i][j] = min(results[i][2 * j],
  2104. results[i][2 * j + 1]);
  2105. }
  2106. for (i = 0; i < 4; i++) {
  2107. s32 mind = 40;
  2108. u8 minvcm = 0;
  2109. s32 minpoll = 249;
  2110. s32 curr;
  2111. for (j = 0; j < 4; j++) {
  2112. if (type == 2)
  2113. curr = abs(results[j][i]);
  2114. else
  2115. curr = abs(miniq[j][i / 2] - code * 8);
  2116. if (curr < mind) {
  2117. mind = curr;
  2118. minvcm = j;
  2119. }
  2120. if (results[j][i] < minpoll)
  2121. minpoll = results[j][i];
  2122. }
  2123. results_min[i] = minpoll;
  2124. vcm_final[i] = minvcm;
  2125. }
  2126. if (type != 1)
  2127. b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
  2128. for (i = 0; i < 4; i++) {
  2129. offset[i] = (code * 8) - results[vcm_final[i]][i];
  2130. if (offset[i] < 0)
  2131. offset[i] = -((abs(offset[i]) + 4) / 8);
  2132. else
  2133. offset[i] = (offset[i] + 4) / 8;
  2134. if (results_min[i] == 248)
  2135. offset[i] = code - 32;
  2136. core = (i / 2) ? 2 : 1;
  2137. rail = (i % 2) ? 1 : 0;
  2138. b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
  2139. type);
  2140. }
  2141. b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
  2142. b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
  2143. switch (state[2]) {
  2144. case 1:
  2145. b43_nphy_rssi_select(dev, 1, 2);
  2146. break;
  2147. case 4:
  2148. b43_nphy_rssi_select(dev, 1, 0);
  2149. break;
  2150. case 2:
  2151. b43_nphy_rssi_select(dev, 1, 1);
  2152. break;
  2153. default:
  2154. b43_nphy_rssi_select(dev, 1, 1);
  2155. break;
  2156. }
  2157. switch (state[3]) {
  2158. case 1:
  2159. b43_nphy_rssi_select(dev, 2, 2);
  2160. break;
  2161. case 4:
  2162. b43_nphy_rssi_select(dev, 2, 0);
  2163. break;
  2164. default:
  2165. b43_nphy_rssi_select(dev, 2, 1);
  2166. break;
  2167. }
  2168. b43_nphy_rssi_select(dev, 0, type);
  2169. b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
  2170. b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
  2171. b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
  2172. b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
  2173. b43_nphy_classifier(dev, 7, class);
  2174. b43_nphy_write_clip_detection(dev, clip_state);
  2175. /* Specs don't say about reset here, but it makes wl and b43 dumps
  2176. identical, it really seems wl performs this */
  2177. b43_nphy_reset_cca(dev);
  2178. }
  2179. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
  2180. static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
  2181. {
  2182. /* TODO */
  2183. }
  2184. /*
  2185. * RSSI Calibration
  2186. * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
  2187. */
  2188. static void b43_nphy_rssi_cal(struct b43_wldev *dev)
  2189. {
  2190. if (dev->phy.rev >= 3) {
  2191. b43_nphy_rev3_rssi_cal(dev);
  2192. } else {
  2193. b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
  2194. b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
  2195. b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
  2196. }
  2197. }
  2198. /*
  2199. * Restore RSSI Calibration
  2200. * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
  2201. */
  2202. static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
  2203. {
  2204. struct b43_phy_n *nphy = dev->phy.n;
  2205. u16 *rssical_radio_regs = NULL;
  2206. u16 *rssical_phy_regs = NULL;
  2207. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  2208. if (!nphy->rssical_chanspec_2G.center_freq)
  2209. return;
  2210. rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
  2211. rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
  2212. } else {
  2213. if (!nphy->rssical_chanspec_5G.center_freq)
  2214. return;
  2215. rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
  2216. rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
  2217. }
  2218. /* TODO use some definitions */
  2219. b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
  2220. b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
  2221. b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
  2222. b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
  2223. b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
  2224. b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
  2225. b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
  2226. b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
  2227. b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
  2228. b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
  2229. b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
  2230. b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
  2231. b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
  2232. b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
  2233. }
  2234. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
  2235. static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
  2236. {
  2237. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  2238. if (dev->phy.rev >= 6) {
  2239. /* TODO If the chip is 47162
  2240. return txpwrctrl_tx_gain_ipa_rev5 */
  2241. return txpwrctrl_tx_gain_ipa_rev6;
  2242. } else if (dev->phy.rev >= 5) {
  2243. return txpwrctrl_tx_gain_ipa_rev5;
  2244. } else {
  2245. return txpwrctrl_tx_gain_ipa;
  2246. }
  2247. } else {
  2248. return txpwrctrl_tx_gain_ipa_5g;
  2249. }
  2250. }
  2251. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
  2252. static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
  2253. {
  2254. struct b43_phy_n *nphy = dev->phy.n;
  2255. u16 *save = nphy->tx_rx_cal_radio_saveregs;
  2256. u16 tmp;
  2257. u8 offset, i;
  2258. if (dev->phy.rev >= 3) {
  2259. for (i = 0; i < 2; i++) {
  2260. tmp = (i == 0) ? 0x2000 : 0x3000;
  2261. offset = i * 11;
  2262. save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
  2263. save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
  2264. save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
  2265. save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
  2266. save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
  2267. save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
  2268. save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
  2269. save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
  2270. save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
  2271. save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
  2272. save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
  2273. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
  2274. b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
  2275. b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
  2276. b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
  2277. b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
  2278. b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
  2279. if (nphy->ipa5g_on) {
  2280. b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
  2281. b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
  2282. } else {
  2283. b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
  2284. b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
  2285. }
  2286. b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
  2287. } else {
  2288. b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
  2289. b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
  2290. b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
  2291. b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
  2292. b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
  2293. b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
  2294. if (nphy->ipa2g_on) {
  2295. b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
  2296. b43_radio_write16(dev, tmp | B2055_XOCTL2,
  2297. (dev->phy.rev < 5) ? 0x11 : 0x01);
  2298. } else {
  2299. b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
  2300. b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
  2301. }
  2302. }
  2303. b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
  2304. b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
  2305. b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
  2306. }
  2307. } else {
  2308. save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
  2309. b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
  2310. save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
  2311. b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
  2312. save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
  2313. b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
  2314. save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
  2315. b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
  2316. save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
  2317. save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
  2318. if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
  2319. B43_NPHY_BANDCTL_5GHZ)) {
  2320. b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
  2321. b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
  2322. } else {
  2323. b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
  2324. b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
  2325. }
  2326. if (dev->phy.rev < 2) {
  2327. b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
  2328. b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
  2329. } else {
  2330. b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
  2331. b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
  2332. }
  2333. }
  2334. }
  2335. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
  2336. static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
  2337. struct nphy_txgains target,
  2338. struct nphy_iqcal_params *params)
  2339. {
  2340. int i, j, indx;
  2341. u16 gain;
  2342. if (dev->phy.rev >= 3) {
  2343. params->txgm = target.txgm[core];
  2344. params->pga = target.pga[core];
  2345. params->pad = target.pad[core];
  2346. params->ipa = target.ipa[core];
  2347. params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
  2348. (params->pad << 4) | (params->ipa);
  2349. for (j = 0; j < 5; j++)
  2350. params->ncorr[j] = 0x79;
  2351. } else {
  2352. gain = (target.pad[core]) | (target.pga[core] << 4) |
  2353. (target.txgm[core] << 8);
  2354. indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
  2355. 1 : 0;
  2356. for (i = 0; i < 9; i++)
  2357. if (tbl_iqcal_gainparams[indx][i][0] == gain)
  2358. break;
  2359. i = min(i, 8);
  2360. params->txgm = tbl_iqcal_gainparams[indx][i][1];
  2361. params->pga = tbl_iqcal_gainparams[indx][i][2];
  2362. params->pad = tbl_iqcal_gainparams[indx][i][3];
  2363. params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
  2364. (params->pad << 2);
  2365. for (j = 0; j < 4; j++)
  2366. params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
  2367. }
  2368. }
  2369. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
  2370. static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
  2371. {
  2372. struct b43_phy_n *nphy = dev->phy.n;
  2373. int i;
  2374. u16 scale, entry;
  2375. u16 tmp = nphy->txcal_bbmult;
  2376. if (core == 0)
  2377. tmp >>= 8;
  2378. tmp &= 0xff;
  2379. for (i = 0; i < 18; i++) {
  2380. scale = (ladder_lo[i].percent * tmp) / 100;
  2381. entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
  2382. b43_ntab_write(dev, B43_NTAB16(15, i), entry);
  2383. scale = (ladder_iq[i].percent * tmp) / 100;
  2384. entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
  2385. b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
  2386. }
  2387. }
  2388. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
  2389. static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
  2390. {
  2391. int i;
  2392. for (i = 0; i < 15; i++)
  2393. b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
  2394. tbl_tx_filter_coef_rev4[2][i]);
  2395. }
  2396. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
  2397. static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
  2398. {
  2399. int i, j;
  2400. /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
  2401. static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
  2402. for (i = 0; i < 3; i++)
  2403. for (j = 0; j < 15; j++)
  2404. b43_phy_write(dev, B43_PHY_N(offset[i] + j),
  2405. tbl_tx_filter_coef_rev4[i][j]);
  2406. if (dev->phy.is_40mhz) {
  2407. for (j = 0; j < 15; j++)
  2408. b43_phy_write(dev, B43_PHY_N(offset[0] + j),
  2409. tbl_tx_filter_coef_rev4[3][j]);
  2410. } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
  2411. for (j = 0; j < 15; j++)
  2412. b43_phy_write(dev, B43_PHY_N(offset[0] + j),
  2413. tbl_tx_filter_coef_rev4[5][j]);
  2414. }
  2415. if (dev->phy.channel == 14)
  2416. for (j = 0; j < 15; j++)
  2417. b43_phy_write(dev, B43_PHY_N(offset[0] + j),
  2418. tbl_tx_filter_coef_rev4[6][j]);
  2419. }
  2420. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
  2421. static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
  2422. {
  2423. struct b43_phy_n *nphy = dev->phy.n;
  2424. u16 curr_gain[2];
  2425. struct nphy_txgains target;
  2426. const u32 *table = NULL;
  2427. if (!nphy->txpwrctrl) {
  2428. int i;
  2429. if (nphy->hang_avoid)
  2430. b43_nphy_stay_in_carrier_search(dev, true);
  2431. b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
  2432. if (nphy->hang_avoid)
  2433. b43_nphy_stay_in_carrier_search(dev, false);
  2434. for (i = 0; i < 2; ++i) {
  2435. if (dev->phy.rev >= 3) {
  2436. target.ipa[i] = curr_gain[i] & 0x000F;
  2437. target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
  2438. target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
  2439. target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
  2440. } else {
  2441. target.ipa[i] = curr_gain[i] & 0x0003;
  2442. target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
  2443. target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
  2444. target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
  2445. }
  2446. }
  2447. } else {
  2448. int i;
  2449. u16 index[2];
  2450. index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
  2451. B43_NPHY_TXPCTL_STAT_BIDX) >>
  2452. B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
  2453. index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
  2454. B43_NPHY_TXPCTL_STAT_BIDX) >>
  2455. B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
  2456. for (i = 0; i < 2; ++i) {
  2457. if (dev->phy.rev >= 3) {
  2458. enum ieee80211_band band =
  2459. b43_current_band(dev->wl);
  2460. if ((nphy->ipa2g_on &&
  2461. band == IEEE80211_BAND_2GHZ) ||
  2462. (nphy->ipa5g_on &&
  2463. band == IEEE80211_BAND_5GHZ)) {
  2464. table = b43_nphy_get_ipa_gain_table(dev);
  2465. } else {
  2466. if (band == IEEE80211_BAND_5GHZ) {
  2467. if (dev->phy.rev == 3)
  2468. table = b43_ntab_tx_gain_rev3_5ghz;
  2469. else if (dev->phy.rev == 4)
  2470. table = b43_ntab_tx_gain_rev4_5ghz;
  2471. else
  2472. table = b43_ntab_tx_gain_rev5plus_5ghz;
  2473. } else {
  2474. table = b43_ntab_tx_gain_rev3plus_2ghz;
  2475. }
  2476. }
  2477. target.ipa[i] = (table[index[i]] >> 16) & 0xF;
  2478. target.pad[i] = (table[index[i]] >> 20) & 0xF;
  2479. target.pga[i] = (table[index[i]] >> 24) & 0xF;
  2480. target.txgm[i] = (table[index[i]] >> 28) & 0xF;
  2481. } else {
  2482. table = b43_ntab_tx_gain_rev0_1_2;
  2483. target.ipa[i] = (table[index[i]] >> 16) & 0x3;
  2484. target.pad[i] = (table[index[i]] >> 18) & 0x3;
  2485. target.pga[i] = (table[index[i]] >> 20) & 0x7;
  2486. target.txgm[i] = (table[index[i]] >> 23) & 0x7;
  2487. }
  2488. }
  2489. }
  2490. return target;
  2491. }
  2492. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
  2493. static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
  2494. {
  2495. u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
  2496. if (dev->phy.rev >= 3) {
  2497. b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
  2498. b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
  2499. b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
  2500. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
  2501. b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
  2502. b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
  2503. b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
  2504. b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
  2505. b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
  2506. b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
  2507. b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
  2508. b43_nphy_reset_cca(dev);
  2509. } else {
  2510. b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
  2511. b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
  2512. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
  2513. b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
  2514. b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
  2515. b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
  2516. b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
  2517. }
  2518. }
  2519. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
  2520. static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
  2521. {
  2522. u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
  2523. u16 tmp;
  2524. regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
  2525. regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
  2526. if (dev->phy.rev >= 3) {
  2527. b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
  2528. b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
  2529. tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
  2530. regs[2] = tmp;
  2531. b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
  2532. tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
  2533. regs[3] = tmp;
  2534. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
  2535. regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
  2536. b43_phy_mask(dev, B43_NPHY_BBCFG,
  2537. ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
  2538. tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
  2539. regs[5] = tmp;
  2540. b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
  2541. tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
  2542. regs[6] = tmp;
  2543. b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
  2544. regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
  2545. regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
  2546. b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
  2547. b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
  2548. b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
  2549. regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
  2550. regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
  2551. b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
  2552. b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
  2553. } else {
  2554. b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
  2555. b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
  2556. tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
  2557. regs[2] = tmp;
  2558. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
  2559. tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
  2560. regs[3] = tmp;
  2561. tmp |= 0x2000;
  2562. b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
  2563. tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
  2564. regs[4] = tmp;
  2565. tmp |= 0x2000;
  2566. b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
  2567. regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
  2568. regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
  2569. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
  2570. tmp = 0x0180;
  2571. else
  2572. tmp = 0x0120;
  2573. b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
  2574. b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
  2575. }
  2576. }
  2577. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
  2578. static void b43_nphy_save_cal(struct b43_wldev *dev)
  2579. {
  2580. struct b43_phy_n *nphy = dev->phy.n;
  2581. struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
  2582. u16 *txcal_radio_regs = NULL;
  2583. struct b43_chanspec *iqcal_chanspec;
  2584. u16 *table = NULL;
  2585. if (nphy->hang_avoid)
  2586. b43_nphy_stay_in_carrier_search(dev, 1);
  2587. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  2588. rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
  2589. txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
  2590. iqcal_chanspec = &nphy->iqcal_chanspec_2G;
  2591. table = nphy->cal_cache.txcal_coeffs_2G;
  2592. } else {
  2593. rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
  2594. txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
  2595. iqcal_chanspec = &nphy->iqcal_chanspec_5G;
  2596. table = nphy->cal_cache.txcal_coeffs_5G;
  2597. }
  2598. b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
  2599. /* TODO use some definitions */
  2600. if (dev->phy.rev >= 3) {
  2601. txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
  2602. txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
  2603. txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
  2604. txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
  2605. txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
  2606. txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
  2607. txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
  2608. txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
  2609. } else {
  2610. txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
  2611. txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
  2612. txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
  2613. txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
  2614. }
  2615. iqcal_chanspec->center_freq = dev->phy.channel_freq;
  2616. iqcal_chanspec->channel_type = dev->phy.channel_type;
  2617. b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
  2618. if (nphy->hang_avoid)
  2619. b43_nphy_stay_in_carrier_search(dev, 0);
  2620. }
  2621. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
  2622. static void b43_nphy_restore_cal(struct b43_wldev *dev)
  2623. {
  2624. struct b43_phy_n *nphy = dev->phy.n;
  2625. u16 coef[4];
  2626. u16 *loft = NULL;
  2627. u16 *table = NULL;
  2628. int i;
  2629. u16 *txcal_radio_regs = NULL;
  2630. struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
  2631. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  2632. if (!nphy->iqcal_chanspec_2G.center_freq)
  2633. return;
  2634. table = nphy->cal_cache.txcal_coeffs_2G;
  2635. loft = &nphy->cal_cache.txcal_coeffs_2G[5];
  2636. } else {
  2637. if (!nphy->iqcal_chanspec_5G.center_freq)
  2638. return;
  2639. table = nphy->cal_cache.txcal_coeffs_5G;
  2640. loft = &nphy->cal_cache.txcal_coeffs_5G[5];
  2641. }
  2642. b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
  2643. for (i = 0; i < 4; i++) {
  2644. if (dev->phy.rev >= 3)
  2645. table[i] = coef[i];
  2646. else
  2647. coef[i] = 0;
  2648. }
  2649. b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
  2650. b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
  2651. b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
  2652. if (dev->phy.rev < 2)
  2653. b43_nphy_tx_iq_workaround(dev);
  2654. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  2655. txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
  2656. rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
  2657. } else {
  2658. txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
  2659. rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
  2660. }
  2661. /* TODO use some definitions */
  2662. if (dev->phy.rev >= 3) {
  2663. b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
  2664. b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
  2665. b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
  2666. b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
  2667. b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
  2668. b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
  2669. b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
  2670. b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
  2671. } else {
  2672. b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
  2673. b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
  2674. b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
  2675. b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
  2676. }
  2677. b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
  2678. }
  2679. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
  2680. static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
  2681. struct nphy_txgains target,
  2682. bool full, bool mphase)
  2683. {
  2684. struct b43_phy_n *nphy = dev->phy.n;
  2685. int i;
  2686. int error = 0;
  2687. int freq;
  2688. bool avoid = false;
  2689. u8 length;
  2690. u16 tmp, core, type, count, max, numb, last = 0, cmd;
  2691. const u16 *table;
  2692. bool phy6or5x;
  2693. u16 buffer[11];
  2694. u16 diq_start = 0;
  2695. u16 save[2];
  2696. u16 gain[2];
  2697. struct nphy_iqcal_params params[2];
  2698. bool updated[2] = { };
  2699. b43_nphy_stay_in_carrier_search(dev, true);
  2700. if (dev->phy.rev >= 4) {
  2701. avoid = nphy->hang_avoid;
  2702. nphy->hang_avoid = 0;
  2703. }
  2704. b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
  2705. for (i = 0; i < 2; i++) {
  2706. b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
  2707. gain[i] = params[i].cal_gain;
  2708. }
  2709. b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
  2710. b43_nphy_tx_cal_radio_setup(dev);
  2711. b43_nphy_tx_cal_phy_setup(dev);
  2712. phy6or5x = dev->phy.rev >= 6 ||
  2713. (dev->phy.rev == 5 && nphy->ipa2g_on &&
  2714. b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
  2715. if (phy6or5x) {
  2716. if (dev->phy.is_40mhz) {
  2717. b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
  2718. tbl_tx_iqlo_cal_loft_ladder_40);
  2719. b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
  2720. tbl_tx_iqlo_cal_iqimb_ladder_40);
  2721. } else {
  2722. b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
  2723. tbl_tx_iqlo_cal_loft_ladder_20);
  2724. b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
  2725. tbl_tx_iqlo_cal_iqimb_ladder_20);
  2726. }
  2727. }
  2728. b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
  2729. if (!dev->phy.is_40mhz)
  2730. freq = 2500;
  2731. else
  2732. freq = 5000;
  2733. if (nphy->mphase_cal_phase_id > 2)
  2734. b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
  2735. 0xFFFF, 0, true, false);
  2736. else
  2737. error = b43_nphy_tx_tone(dev, freq, 250, true, false);
  2738. if (error == 0) {
  2739. if (nphy->mphase_cal_phase_id > 2) {
  2740. table = nphy->mphase_txcal_bestcoeffs;
  2741. length = 11;
  2742. if (dev->phy.rev < 3)
  2743. length -= 2;
  2744. } else {
  2745. if (!full && nphy->txiqlocal_coeffsvalid) {
  2746. table = nphy->txiqlocal_bestc;
  2747. length = 11;
  2748. if (dev->phy.rev < 3)
  2749. length -= 2;
  2750. } else {
  2751. full = true;
  2752. if (dev->phy.rev >= 3) {
  2753. table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
  2754. length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
  2755. } else {
  2756. table = tbl_tx_iqlo_cal_startcoefs;
  2757. length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
  2758. }
  2759. }
  2760. }
  2761. b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
  2762. if (full) {
  2763. if (dev->phy.rev >= 3)
  2764. max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
  2765. else
  2766. max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
  2767. } else {
  2768. if (dev->phy.rev >= 3)
  2769. max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
  2770. else
  2771. max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
  2772. }
  2773. if (mphase) {
  2774. count = nphy->mphase_txcal_cmdidx;
  2775. numb = min(max,
  2776. (u16)(count + nphy->mphase_txcal_numcmds));
  2777. } else {
  2778. count = 0;
  2779. numb = max;
  2780. }
  2781. for (; count < numb; count++) {
  2782. if (full) {
  2783. if (dev->phy.rev >= 3)
  2784. cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
  2785. else
  2786. cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
  2787. } else {
  2788. if (dev->phy.rev >= 3)
  2789. cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
  2790. else
  2791. cmd = tbl_tx_iqlo_cal_cmds_recal[count];
  2792. }
  2793. core = (cmd & 0x3000) >> 12;
  2794. type = (cmd & 0x0F00) >> 8;
  2795. if (phy6or5x && updated[core] == 0) {
  2796. b43_nphy_update_tx_cal_ladder(dev, core);
  2797. updated[core] = 1;
  2798. }
  2799. tmp = (params[core].ncorr[type] << 8) | 0x66;
  2800. b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
  2801. if (type == 1 || type == 3 || type == 4) {
  2802. buffer[0] = b43_ntab_read(dev,
  2803. B43_NTAB16(15, 69 + core));
  2804. diq_start = buffer[0];
  2805. buffer[0] = 0;
  2806. b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
  2807. 0);
  2808. }
  2809. b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
  2810. for (i = 0; i < 2000; i++) {
  2811. tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
  2812. if (tmp & 0xC000)
  2813. break;
  2814. udelay(10);
  2815. }
  2816. b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
  2817. buffer);
  2818. b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
  2819. buffer);
  2820. if (type == 1 || type == 3 || type == 4)
  2821. buffer[0] = diq_start;
  2822. }
  2823. if (mphase)
  2824. nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
  2825. last = (dev->phy.rev < 3) ? 6 : 7;
  2826. if (!mphase || nphy->mphase_cal_phase_id == last) {
  2827. b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
  2828. b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
  2829. if (dev->phy.rev < 3) {
  2830. buffer[0] = 0;
  2831. buffer[1] = 0;
  2832. buffer[2] = 0;
  2833. buffer[3] = 0;
  2834. }
  2835. b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
  2836. buffer);
  2837. b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
  2838. buffer);
  2839. b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
  2840. buffer);
  2841. b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
  2842. buffer);
  2843. length = 11;
  2844. if (dev->phy.rev < 3)
  2845. length -= 2;
  2846. b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
  2847. nphy->txiqlocal_bestc);
  2848. nphy->txiqlocal_coeffsvalid = true;
  2849. nphy->txiqlocal_chanspec.center_freq =
  2850. dev->phy.channel_freq;
  2851. nphy->txiqlocal_chanspec.channel_type =
  2852. dev->phy.channel_type;
  2853. } else {
  2854. length = 11;
  2855. if (dev->phy.rev < 3)
  2856. length -= 2;
  2857. b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
  2858. nphy->mphase_txcal_bestcoeffs);
  2859. }
  2860. b43_nphy_stop_playback(dev);
  2861. b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
  2862. }
  2863. b43_nphy_tx_cal_phy_cleanup(dev);
  2864. b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
  2865. if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
  2866. b43_nphy_tx_iq_workaround(dev);
  2867. if (dev->phy.rev >= 4)
  2868. nphy->hang_avoid = avoid;
  2869. b43_nphy_stay_in_carrier_search(dev, false);
  2870. return error;
  2871. }
  2872. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
  2873. static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
  2874. {
  2875. struct b43_phy_n *nphy = dev->phy.n;
  2876. u8 i;
  2877. u16 buffer[7];
  2878. bool equal = true;
  2879. if (!nphy->txiqlocal_coeffsvalid ||
  2880. nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
  2881. nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
  2882. return;
  2883. b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
  2884. for (i = 0; i < 4; i++) {
  2885. if (buffer[i] != nphy->txiqlocal_bestc[i]) {
  2886. equal = false;
  2887. break;
  2888. }
  2889. }
  2890. if (!equal) {
  2891. b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
  2892. nphy->txiqlocal_bestc);
  2893. for (i = 0; i < 4; i++)
  2894. buffer[i] = 0;
  2895. b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
  2896. buffer);
  2897. b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
  2898. &nphy->txiqlocal_bestc[5]);
  2899. b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
  2900. &nphy->txiqlocal_bestc[5]);
  2901. }
  2902. }
  2903. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
  2904. static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
  2905. struct nphy_txgains target, u8 type, bool debug)
  2906. {
  2907. struct b43_phy_n *nphy = dev->phy.n;
  2908. int i, j, index;
  2909. u8 rfctl[2];
  2910. u8 afectl_core;
  2911. u16 tmp[6];
  2912. u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
  2913. u32 real, imag;
  2914. enum ieee80211_band band;
  2915. u8 use;
  2916. u16 cur_hpf;
  2917. u16 lna[3] = { 3, 3, 1 };
  2918. u16 hpf1[3] = { 7, 2, 0 };
  2919. u16 hpf2[3] = { 2, 0, 0 };
  2920. u32 power[3] = { };
  2921. u16 gain_save[2];
  2922. u16 cal_gain[2];
  2923. struct nphy_iqcal_params cal_params[2];
  2924. struct nphy_iq_est est;
  2925. int ret = 0;
  2926. bool playtone = true;
  2927. int desired = 13;
  2928. b43_nphy_stay_in_carrier_search(dev, 1);
  2929. if (dev->phy.rev < 2)
  2930. b43_nphy_reapply_tx_cal_coeffs(dev);
  2931. b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
  2932. for (i = 0; i < 2; i++) {
  2933. b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
  2934. cal_gain[i] = cal_params[i].cal_gain;
  2935. }
  2936. b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
  2937. for (i = 0; i < 2; i++) {
  2938. if (i == 0) {
  2939. rfctl[0] = B43_NPHY_RFCTL_INTC1;
  2940. rfctl[1] = B43_NPHY_RFCTL_INTC2;
  2941. afectl_core = B43_NPHY_AFECTL_C1;
  2942. } else {
  2943. rfctl[0] = B43_NPHY_RFCTL_INTC2;
  2944. rfctl[1] = B43_NPHY_RFCTL_INTC1;
  2945. afectl_core = B43_NPHY_AFECTL_C2;
  2946. }
  2947. tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
  2948. tmp[2] = b43_phy_read(dev, afectl_core);
  2949. tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
  2950. tmp[4] = b43_phy_read(dev, rfctl[0]);
  2951. tmp[5] = b43_phy_read(dev, rfctl[1]);
  2952. b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
  2953. ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
  2954. ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
  2955. b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
  2956. (1 - i));
  2957. b43_phy_set(dev, afectl_core, 0x0006);
  2958. b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
  2959. band = b43_current_band(dev->wl);
  2960. if (nphy->rxcalparams & 0xFF000000) {
  2961. if (band == IEEE80211_BAND_5GHZ)
  2962. b43_phy_write(dev, rfctl[0], 0x140);
  2963. else
  2964. b43_phy_write(dev, rfctl[0], 0x110);
  2965. } else {
  2966. if (band == IEEE80211_BAND_5GHZ)
  2967. b43_phy_write(dev, rfctl[0], 0x180);
  2968. else
  2969. b43_phy_write(dev, rfctl[0], 0x120);
  2970. }
  2971. if (band == IEEE80211_BAND_5GHZ)
  2972. b43_phy_write(dev, rfctl[1], 0x148);
  2973. else
  2974. b43_phy_write(dev, rfctl[1], 0x114);
  2975. if (nphy->rxcalparams & 0x10000) {
  2976. b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
  2977. (i + 1));
  2978. b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
  2979. (2 - i));
  2980. }
  2981. for (j = 0; j < 4; j++) {
  2982. if (j < 3) {
  2983. cur_lna = lna[j];
  2984. cur_hpf1 = hpf1[j];
  2985. cur_hpf2 = hpf2[j];
  2986. } else {
  2987. if (power[1] > 10000) {
  2988. use = 1;
  2989. cur_hpf = cur_hpf1;
  2990. index = 2;
  2991. } else {
  2992. if (power[0] > 10000) {
  2993. use = 1;
  2994. cur_hpf = cur_hpf1;
  2995. index = 1;
  2996. } else {
  2997. index = 0;
  2998. use = 2;
  2999. cur_hpf = cur_hpf2;
  3000. }
  3001. }
  3002. cur_lna = lna[index];
  3003. cur_hpf1 = hpf1[index];
  3004. cur_hpf2 = hpf2[index];
  3005. cur_hpf += desired - hweight32(power[index]);
  3006. cur_hpf = clamp_val(cur_hpf, 0, 10);
  3007. if (use == 1)
  3008. cur_hpf1 = cur_hpf;
  3009. else
  3010. cur_hpf2 = cur_hpf;
  3011. }
  3012. tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
  3013. (cur_lna << 2));
  3014. b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
  3015. false);
  3016. b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
  3017. b43_nphy_stop_playback(dev);
  3018. if (playtone) {
  3019. ret = b43_nphy_tx_tone(dev, 4000,
  3020. (nphy->rxcalparams & 0xFFFF),
  3021. false, false);
  3022. playtone = false;
  3023. } else {
  3024. b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
  3025. false, false);
  3026. }
  3027. if (ret == 0) {
  3028. if (j < 3) {
  3029. b43_nphy_rx_iq_est(dev, &est, 1024, 32,
  3030. false);
  3031. if (i == 0) {
  3032. real = est.i0_pwr;
  3033. imag = est.q0_pwr;
  3034. } else {
  3035. real = est.i1_pwr;
  3036. imag = est.q1_pwr;
  3037. }
  3038. power[i] = ((real + imag) / 1024) + 1;
  3039. } else {
  3040. b43_nphy_calc_rx_iq_comp(dev, 1 << i);
  3041. }
  3042. b43_nphy_stop_playback(dev);
  3043. }
  3044. if (ret != 0)
  3045. break;
  3046. }
  3047. b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
  3048. b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
  3049. b43_phy_write(dev, rfctl[1], tmp[5]);
  3050. b43_phy_write(dev, rfctl[0], tmp[4]);
  3051. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
  3052. b43_phy_write(dev, afectl_core, tmp[2]);
  3053. b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
  3054. if (ret != 0)
  3055. break;
  3056. }
  3057. b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
  3058. b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
  3059. b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
  3060. b43_nphy_stay_in_carrier_search(dev, 0);
  3061. return ret;
  3062. }
  3063. static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
  3064. struct nphy_txgains target, u8 type, bool debug)
  3065. {
  3066. return -1;
  3067. }
  3068. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
  3069. static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
  3070. struct nphy_txgains target, u8 type, bool debug)
  3071. {
  3072. if (dev->phy.rev >= 3)
  3073. return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
  3074. else
  3075. return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
  3076. }
  3077. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
  3078. static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
  3079. {
  3080. struct b43_phy *phy = &dev->phy;
  3081. struct b43_phy_n *nphy = phy->n;
  3082. /* u16 buf[16]; it's rev3+ */
  3083. nphy->phyrxchain = mask;
  3084. if (0 /* FIXME clk */)
  3085. return;
  3086. b43_mac_suspend(dev);
  3087. if (nphy->hang_avoid)
  3088. b43_nphy_stay_in_carrier_search(dev, true);
  3089. b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
  3090. (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
  3091. if ((mask & 0x3) != 0x3) {
  3092. b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
  3093. if (dev->phy.rev >= 3) {
  3094. /* TODO */
  3095. }
  3096. } else {
  3097. b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
  3098. if (dev->phy.rev >= 3) {
  3099. /* TODO */
  3100. }
  3101. }
  3102. b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
  3103. if (nphy->hang_avoid)
  3104. b43_nphy_stay_in_carrier_search(dev, false);
  3105. b43_mac_enable(dev);
  3106. }
  3107. /*
  3108. * Init N-PHY
  3109. * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
  3110. */
  3111. int b43_phy_initn(struct b43_wldev *dev)
  3112. {
  3113. struct ssb_sprom *sprom = dev->dev->bus_sprom;
  3114. struct b43_phy *phy = &dev->phy;
  3115. struct b43_phy_n *nphy = phy->n;
  3116. u8 tx_pwr_state;
  3117. struct nphy_txgains target;
  3118. u16 tmp;
  3119. enum ieee80211_band tmp2;
  3120. bool do_rssi_cal;
  3121. u16 clip[2];
  3122. bool do_cal = false;
  3123. if ((dev->phy.rev >= 3) &&
  3124. (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
  3125. (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
  3126. switch (dev->dev->bus_type) {
  3127. #ifdef CONFIG_B43_BCMA
  3128. case B43_BUS_BCMA:
  3129. bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
  3130. BCMA_CC_CHIPCTL, 0x40);
  3131. break;
  3132. #endif
  3133. #ifdef CONFIG_B43_SSB
  3134. case B43_BUS_SSB:
  3135. chipco_set32(&dev->dev->sdev->bus->chipco,
  3136. SSB_CHIPCO_CHIPCTL, 0x40);
  3137. break;
  3138. #endif
  3139. }
  3140. }
  3141. nphy->deaf_count = 0;
  3142. b43_nphy_tables_init(dev);
  3143. nphy->crsminpwr_adjusted = false;
  3144. nphy->noisevars_adjusted = false;
  3145. /* Clear all overrides */
  3146. if (dev->phy.rev >= 3) {
  3147. b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
  3148. b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
  3149. b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
  3150. b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
  3151. } else {
  3152. b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
  3153. }
  3154. b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
  3155. b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
  3156. if (dev->phy.rev < 6) {
  3157. b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
  3158. b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
  3159. }
  3160. b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
  3161. ~(B43_NPHY_RFSEQMODE_CAOVER |
  3162. B43_NPHY_RFSEQMODE_TROVER));
  3163. if (dev->phy.rev >= 3)
  3164. b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
  3165. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
  3166. if (dev->phy.rev <= 2) {
  3167. tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
  3168. b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
  3169. ~B43_NPHY_BPHY_CTL3_SCALE,
  3170. tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
  3171. }
  3172. b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
  3173. b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
  3174. if (sprom->boardflags2_lo & 0x100 ||
  3175. (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
  3176. dev->dev->board_type == 0x8B))
  3177. b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
  3178. else
  3179. b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
  3180. b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
  3181. b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
  3182. b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
  3183. b43_nphy_update_mimo_config(dev, nphy->preamble_override);
  3184. b43_nphy_update_txrx_chain(dev);
  3185. if (phy->rev < 2) {
  3186. b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
  3187. b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
  3188. }
  3189. tmp2 = b43_current_band(dev->wl);
  3190. if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
  3191. (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
  3192. b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
  3193. b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
  3194. nphy->papd_epsilon_offset[0] << 7);
  3195. b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
  3196. b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
  3197. nphy->papd_epsilon_offset[1] << 7);
  3198. b43_nphy_int_pa_set_tx_dig_filters(dev);
  3199. } else if (phy->rev >= 5) {
  3200. b43_nphy_ext_pa_set_tx_dig_filters(dev);
  3201. }
  3202. b43_nphy_workarounds(dev);
  3203. /* Reset CCA, in init code it differs a little from standard way */
  3204. b43_phy_force_clock(dev, 1);
  3205. tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
  3206. b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
  3207. b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
  3208. b43_phy_force_clock(dev, 0);
  3209. b43_mac_phy_clock_set(dev, true);
  3210. b43_nphy_pa_override(dev, false);
  3211. b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
  3212. b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
  3213. b43_nphy_pa_override(dev, true);
  3214. b43_nphy_classifier(dev, 0, 0);
  3215. b43_nphy_read_clip_detection(dev, clip);
  3216. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
  3217. b43_nphy_bphy_init(dev);
  3218. tx_pwr_state = nphy->txpwrctrl;
  3219. b43_nphy_tx_power_ctrl(dev, false);
  3220. b43_nphy_tx_power_fix(dev);
  3221. /* TODO N PHY TX Power Control Idle TSSI */
  3222. /* TODO N PHY TX Power Control Setup */
  3223. if (phy->rev >= 3) {
  3224. /* TODO */
  3225. } else {
  3226. b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
  3227. b43_ntab_tx_gain_rev0_1_2);
  3228. b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
  3229. b43_ntab_tx_gain_rev0_1_2);
  3230. }
  3231. if (nphy->phyrxchain != 3)
  3232. b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
  3233. if (nphy->mphase_cal_phase_id > 0)
  3234. ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
  3235. do_rssi_cal = false;
  3236. if (phy->rev >= 3) {
  3237. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
  3238. do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
  3239. else
  3240. do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
  3241. if (do_rssi_cal)
  3242. b43_nphy_rssi_cal(dev);
  3243. else
  3244. b43_nphy_restore_rssi_cal(dev);
  3245. } else {
  3246. b43_nphy_rssi_cal(dev);
  3247. }
  3248. if (!((nphy->measure_hold & 0x6) != 0)) {
  3249. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
  3250. do_cal = !nphy->iqcal_chanspec_2G.center_freq;
  3251. else
  3252. do_cal = !nphy->iqcal_chanspec_5G.center_freq;
  3253. if (nphy->mute)
  3254. do_cal = false;
  3255. if (do_cal) {
  3256. target = b43_nphy_get_tx_gains(dev);
  3257. if (nphy->antsel_type == 2)
  3258. b43_nphy_superswitch_init(dev, true);
  3259. if (nphy->perical != 2) {
  3260. b43_nphy_rssi_cal(dev);
  3261. if (phy->rev >= 3) {
  3262. nphy->cal_orig_pwr_idx[0] =
  3263. nphy->txpwrindex[0].index_internal;
  3264. nphy->cal_orig_pwr_idx[1] =
  3265. nphy->txpwrindex[1].index_internal;
  3266. /* TODO N PHY Pre Calibrate TX Gain */
  3267. target = b43_nphy_get_tx_gains(dev);
  3268. }
  3269. if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
  3270. if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
  3271. b43_nphy_save_cal(dev);
  3272. } else if (nphy->mphase_cal_phase_id == 0)
  3273. ;/* N PHY Periodic Calibration with arg 3 */
  3274. } else {
  3275. b43_nphy_restore_cal(dev);
  3276. }
  3277. }
  3278. b43_nphy_tx_pwr_ctrl_coef_setup(dev);
  3279. b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
  3280. b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
  3281. b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
  3282. if (phy->rev >= 3 && phy->rev <= 6)
  3283. b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
  3284. b43_nphy_tx_lp_fbw(dev);
  3285. if (phy->rev >= 3)
  3286. b43_nphy_spur_workaround(dev);
  3287. return 0;
  3288. }
  3289. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
  3290. static void b43_nphy_channel_setup(struct b43_wldev *dev,
  3291. const struct b43_phy_n_sfo_cfg *e,
  3292. struct ieee80211_channel *new_channel)
  3293. {
  3294. struct b43_phy *phy = &dev->phy;
  3295. struct b43_phy_n *nphy = dev->phy.n;
  3296. u16 old_band_5ghz;
  3297. u32 tmp32;
  3298. old_band_5ghz =
  3299. b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
  3300. if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
  3301. tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
  3302. b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
  3303. b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
  3304. b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
  3305. b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
  3306. } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
  3307. b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
  3308. tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
  3309. b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
  3310. b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
  3311. b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
  3312. }
  3313. b43_chantab_phy_upload(dev, e);
  3314. if (new_channel->hw_value == 14) {
  3315. b43_nphy_classifier(dev, 2, 0);
  3316. b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
  3317. } else {
  3318. b43_nphy_classifier(dev, 2, 2);
  3319. if (new_channel->band == IEEE80211_BAND_2GHZ)
  3320. b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
  3321. }
  3322. if (!nphy->txpwrctrl)
  3323. b43_nphy_tx_power_fix(dev);
  3324. if (dev->phy.rev < 3)
  3325. b43_nphy_adjust_lna_gain_table(dev);
  3326. b43_nphy_tx_lp_fbw(dev);
  3327. if (dev->phy.rev >= 3 && 0) {
  3328. /* TODO */
  3329. }
  3330. b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
  3331. if (phy->rev >= 3)
  3332. b43_nphy_spur_workaround(dev);
  3333. }
  3334. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
  3335. static int b43_nphy_set_channel(struct b43_wldev *dev,
  3336. struct ieee80211_channel *channel,
  3337. enum nl80211_channel_type channel_type)
  3338. {
  3339. struct b43_phy *phy = &dev->phy;
  3340. const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
  3341. const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
  3342. u8 tmp;
  3343. if (dev->phy.rev >= 3) {
  3344. tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
  3345. channel->center_freq);
  3346. if (!tabent_r3)
  3347. return -ESRCH;
  3348. } else {
  3349. tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
  3350. channel->hw_value);
  3351. if (!tabent_r2)
  3352. return -ESRCH;
  3353. }
  3354. /* Channel is set later in common code, but we need to set it on our
  3355. own to let this function's subcalls work properly. */
  3356. phy->channel = channel->hw_value;
  3357. phy->channel_freq = channel->center_freq;
  3358. if (b43_channel_type_is_40mhz(phy->channel_type) !=
  3359. b43_channel_type_is_40mhz(channel_type))
  3360. ; /* TODO: BMAC BW Set (channel_type) */
  3361. if (channel_type == NL80211_CHAN_HT40PLUS)
  3362. b43_phy_set(dev, B43_NPHY_RXCTL,
  3363. B43_NPHY_RXCTL_BSELU20);
  3364. else if (channel_type == NL80211_CHAN_HT40MINUS)
  3365. b43_phy_mask(dev, B43_NPHY_RXCTL,
  3366. ~B43_NPHY_RXCTL_BSELU20);
  3367. if (dev->phy.rev >= 3) {
  3368. tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
  3369. b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
  3370. b43_radio_2056_setup(dev, tabent_r3);
  3371. b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
  3372. } else {
  3373. tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
  3374. b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
  3375. b43_radio_2055_setup(dev, tabent_r2);
  3376. b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
  3377. }
  3378. return 0;
  3379. }
  3380. static int b43_nphy_op_allocate(struct b43_wldev *dev)
  3381. {
  3382. struct b43_phy_n *nphy;
  3383. nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
  3384. if (!nphy)
  3385. return -ENOMEM;
  3386. dev->phy.n = nphy;
  3387. return 0;
  3388. }
  3389. static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
  3390. {
  3391. struct b43_phy *phy = &dev->phy;
  3392. struct b43_phy_n *nphy = phy->n;
  3393. memset(nphy, 0, sizeof(*nphy));
  3394. nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
  3395. nphy->gain_boost = true; /* this way we follow wl, assume it is true */
  3396. nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
  3397. nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
  3398. nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
  3399. }
  3400. static void b43_nphy_op_free(struct b43_wldev *dev)
  3401. {
  3402. struct b43_phy *phy = &dev->phy;
  3403. struct b43_phy_n *nphy = phy->n;
  3404. kfree(nphy);
  3405. phy->n = NULL;
  3406. }
  3407. static int b43_nphy_op_init(struct b43_wldev *dev)
  3408. {
  3409. return b43_phy_initn(dev);
  3410. }
  3411. static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
  3412. {
  3413. #if B43_DEBUG
  3414. if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
  3415. /* OFDM registers are onnly available on A/G-PHYs */
  3416. b43err(dev->wl, "Invalid OFDM PHY access at "
  3417. "0x%04X on N-PHY\n", offset);
  3418. dump_stack();
  3419. }
  3420. if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
  3421. /* Ext-G registers are only available on G-PHYs */
  3422. b43err(dev->wl, "Invalid EXT-G PHY access at "
  3423. "0x%04X on N-PHY\n", offset);
  3424. dump_stack();
  3425. }
  3426. #endif /* B43_DEBUG */
  3427. }
  3428. static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
  3429. {
  3430. check_phyreg(dev, reg);
  3431. b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
  3432. return b43_read16(dev, B43_MMIO_PHY_DATA);
  3433. }
  3434. static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
  3435. {
  3436. check_phyreg(dev, reg);
  3437. b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
  3438. b43_write16(dev, B43_MMIO_PHY_DATA, value);
  3439. }
  3440. static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
  3441. u16 set)
  3442. {
  3443. check_phyreg(dev, reg);
  3444. b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
  3445. b43_write16(dev, B43_MMIO_PHY_DATA,
  3446. (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
  3447. }
  3448. static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
  3449. {
  3450. /* Register 1 is a 32-bit register. */
  3451. B43_WARN_ON(reg == 1);
  3452. /* N-PHY needs 0x100 for read access */
  3453. reg |= 0x100;
  3454. b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
  3455. return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
  3456. }
  3457. static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
  3458. {
  3459. /* Register 1 is a 32-bit register. */
  3460. B43_WARN_ON(reg == 1);
  3461. b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
  3462. b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
  3463. }
  3464. /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
  3465. static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
  3466. bool blocked)
  3467. {
  3468. if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
  3469. b43err(dev->wl, "MAC not suspended\n");
  3470. if (blocked) {
  3471. b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
  3472. ~B43_NPHY_RFCTL_CMD_CHIP0PU);
  3473. if (dev->phy.rev >= 3) {
  3474. b43_radio_mask(dev, 0x09, ~0x2);
  3475. b43_radio_write(dev, 0x204D, 0);
  3476. b43_radio_write(dev, 0x2053, 0);
  3477. b43_radio_write(dev, 0x2058, 0);
  3478. b43_radio_write(dev, 0x205E, 0);
  3479. b43_radio_mask(dev, 0x2062, ~0xF0);
  3480. b43_radio_write(dev, 0x2064, 0);
  3481. b43_radio_write(dev, 0x304D, 0);
  3482. b43_radio_write(dev, 0x3053, 0);
  3483. b43_radio_write(dev, 0x3058, 0);
  3484. b43_radio_write(dev, 0x305E, 0);
  3485. b43_radio_mask(dev, 0x3062, ~0xF0);
  3486. b43_radio_write(dev, 0x3064, 0);
  3487. }
  3488. } else {
  3489. if (dev->phy.rev >= 3) {
  3490. b43_radio_init2056(dev);
  3491. b43_switch_channel(dev, dev->phy.channel);
  3492. } else {
  3493. b43_radio_init2055(dev);
  3494. }
  3495. }
  3496. }
  3497. /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
  3498. static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
  3499. {
  3500. u16 override = on ? 0x0 : 0x7FFF;
  3501. u16 core = on ? 0xD : 0x00FD;
  3502. if (dev->phy.rev >= 3) {
  3503. if (on) {
  3504. b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
  3505. b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
  3506. b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
  3507. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
  3508. } else {
  3509. b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
  3510. b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
  3511. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
  3512. b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
  3513. }
  3514. } else {
  3515. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
  3516. }
  3517. }
  3518. static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
  3519. unsigned int new_channel)
  3520. {
  3521. struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
  3522. enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
  3523. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  3524. if ((new_channel < 1) || (new_channel > 14))
  3525. return -EINVAL;
  3526. } else {
  3527. if (new_channel > 200)
  3528. return -EINVAL;
  3529. }
  3530. return b43_nphy_set_channel(dev, channel, channel_type);
  3531. }
  3532. static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
  3533. {
  3534. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
  3535. return 1;
  3536. return 36;
  3537. }
  3538. const struct b43_phy_operations b43_phyops_n = {
  3539. .allocate = b43_nphy_op_allocate,
  3540. .free = b43_nphy_op_free,
  3541. .prepare_structs = b43_nphy_op_prepare_structs,
  3542. .init = b43_nphy_op_init,
  3543. .phy_read = b43_nphy_op_read,
  3544. .phy_write = b43_nphy_op_write,
  3545. .phy_maskset = b43_nphy_op_maskset,
  3546. .radio_read = b43_nphy_op_radio_read,
  3547. .radio_write = b43_nphy_op_radio_write,
  3548. .software_rfkill = b43_nphy_op_software_rfkill,
  3549. .switch_analog = b43_nphy_op_switch_analog,
  3550. .switch_channel = b43_nphy_op_switch_channel,
  3551. .get_default_chan = b43_nphy_op_get_default_chan,
  3552. .recalc_txpower = b43_nphy_op_recalc_txpower,
  3553. .adjust_txpower = b43_nphy_op_adjust_txpower,
  3554. };