phy_ht.c 17 KB

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  1. /*
  2. Broadcom B43 wireless driver
  3. IEEE 802.11n HT-PHY support
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; see the file COPYING. If not, write to
  14. the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  15. Boston, MA 02110-1301, USA.
  16. */
  17. #include <linux/slab.h>
  18. #include "b43.h"
  19. #include "phy_ht.h"
  20. #include "tables_phy_ht.h"
  21. #include "radio_2059.h"
  22. #include "main.h"
  23. /**************************************************
  24. * Radio 2059.
  25. **************************************************/
  26. static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
  27. const struct b43_phy_ht_channeltab_e_radio2059 *e)
  28. {
  29. u8 i;
  30. u16 routing;
  31. b43_radio_write(dev, 0x16, e->radio_syn16);
  32. b43_radio_write(dev, 0x17, e->radio_syn17);
  33. b43_radio_write(dev, 0x22, e->radio_syn22);
  34. b43_radio_write(dev, 0x25, e->radio_syn25);
  35. b43_radio_write(dev, 0x27, e->radio_syn27);
  36. b43_radio_write(dev, 0x28, e->radio_syn28);
  37. b43_radio_write(dev, 0x29, e->radio_syn29);
  38. b43_radio_write(dev, 0x2c, e->radio_syn2c);
  39. b43_radio_write(dev, 0x2d, e->radio_syn2d);
  40. b43_radio_write(dev, 0x37, e->radio_syn37);
  41. b43_radio_write(dev, 0x41, e->radio_syn41);
  42. b43_radio_write(dev, 0x43, e->radio_syn43);
  43. b43_radio_write(dev, 0x47, e->radio_syn47);
  44. b43_radio_write(dev, 0x4a, e->radio_syn4a);
  45. b43_radio_write(dev, 0x58, e->radio_syn58);
  46. b43_radio_write(dev, 0x5a, e->radio_syn5a);
  47. b43_radio_write(dev, 0x6a, e->radio_syn6a);
  48. b43_radio_write(dev, 0x6d, e->radio_syn6d);
  49. b43_radio_write(dev, 0x6e, e->radio_syn6e);
  50. b43_radio_write(dev, 0x92, e->radio_syn92);
  51. b43_radio_write(dev, 0x98, e->radio_syn98);
  52. for (i = 0; i < 2; i++) {
  53. routing = i ? R2059_RXRX1 : R2059_TXRX0;
  54. b43_radio_write(dev, routing | 0x4a, e->radio_rxtx4a);
  55. b43_radio_write(dev, routing | 0x58, e->radio_rxtx58);
  56. b43_radio_write(dev, routing | 0x5a, e->radio_rxtx5a);
  57. b43_radio_write(dev, routing | 0x6a, e->radio_rxtx6a);
  58. b43_radio_write(dev, routing | 0x6d, e->radio_rxtx6d);
  59. b43_radio_write(dev, routing | 0x6e, e->radio_rxtx6e);
  60. b43_radio_write(dev, routing | 0x92, e->radio_rxtx92);
  61. b43_radio_write(dev, routing | 0x98, e->radio_rxtx98);
  62. }
  63. udelay(50);
  64. /* Calibration */
  65. b43_radio_mask(dev, 0x2b, ~0x1);
  66. b43_radio_mask(dev, 0x2e, ~0x4);
  67. b43_radio_set(dev, 0x2e, 0x4);
  68. b43_radio_set(dev, 0x2b, 0x1);
  69. udelay(300);
  70. }
  71. static void b43_radio_2059_init(struct b43_wldev *dev)
  72. {
  73. const u16 routing[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1 };
  74. const u16 radio_values[3][2] = {
  75. { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 },
  76. };
  77. u16 i, j;
  78. b43_radio_write(dev, R2059_ALL | 0x51, 0x0070);
  79. b43_radio_write(dev, R2059_ALL | 0x5a, 0x0003);
  80. for (i = 0; i < ARRAY_SIZE(routing); i++)
  81. b43_radio_set(dev, routing[i] | 0x146, 0x3);
  82. b43_radio_set(dev, 0x2e, 0x0078);
  83. b43_radio_set(dev, 0xc0, 0x0080);
  84. msleep(2);
  85. b43_radio_mask(dev, 0x2e, ~0x0078);
  86. b43_radio_mask(dev, 0xc0, ~0x0080);
  87. if (1) { /* FIXME */
  88. b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x1);
  89. udelay(10);
  90. b43_radio_set(dev, R2059_RXRX1 | 0x0BF, 0x1);
  91. b43_radio_maskset(dev, R2059_RXRX1 | 0x19B, 0x3, 0x2);
  92. b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x2);
  93. udelay(100);
  94. b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x2);
  95. for (i = 0; i < 10000; i++) {
  96. if (b43_radio_read(dev, R2059_RXRX1 | 0x145) & 1) {
  97. i = 0;
  98. break;
  99. }
  100. udelay(100);
  101. }
  102. if (i)
  103. b43err(dev->wl, "radio 0x945 timeout\n");
  104. b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x1);
  105. b43_radio_set(dev, 0xa, 0x60);
  106. for (i = 0; i < 3; i++) {
  107. b43_radio_write(dev, 0x17F, radio_values[i][0]);
  108. b43_radio_write(dev, 0x13D, 0x6E);
  109. b43_radio_write(dev, 0x13E, radio_values[i][1]);
  110. b43_radio_write(dev, 0x13C, 0x55);
  111. for (j = 0; j < 10000; j++) {
  112. if (b43_radio_read(dev, 0x140) & 2) {
  113. j = 0;
  114. break;
  115. }
  116. udelay(500);
  117. }
  118. if (j)
  119. b43err(dev->wl, "radio 0x140 timeout\n");
  120. b43_radio_write(dev, 0x13C, 0x15);
  121. }
  122. b43_radio_mask(dev, 0x17F, ~0x1);
  123. }
  124. b43_radio_mask(dev, 0x11, ~0x0008);
  125. }
  126. /**************************************************
  127. * Various PHY ops
  128. **************************************************/
  129. static void b43_phy_ht_zero_extg(struct b43_wldev *dev)
  130. {
  131. u8 i, j;
  132. u16 base[] = { 0x40, 0x60, 0x80 };
  133. for (i = 0; i < ARRAY_SIZE(base); i++) {
  134. for (j = 0; j < 4; j++)
  135. b43_phy_write(dev, B43_PHY_EXTG(base[i] + j), 0);
  136. }
  137. for (i = 0; i < ARRAY_SIZE(base); i++)
  138. b43_phy_write(dev, B43_PHY_EXTG(base[i] + 0xc), 0);
  139. }
  140. /* Some unknown AFE (Analog Frondned) op */
  141. static void b43_phy_ht_afe_unk1(struct b43_wldev *dev)
  142. {
  143. u8 i;
  144. const u16 ctl_regs[3][2] = {
  145. { B43_PHY_HT_AFE_CTL1, B43_PHY_HT_AFE_CTL2 },
  146. { B43_PHY_HT_AFE_CTL3, B43_PHY_HT_AFE_CTL4 },
  147. { B43_PHY_HT_AFE_CTL5, B43_PHY_HT_AFE_CTL6},
  148. };
  149. for (i = 0; i < 3; i++) {
  150. /* TODO: verify masks&sets */
  151. b43_phy_set(dev, ctl_regs[i][1], 0x4);
  152. b43_phy_set(dev, ctl_regs[i][0], 0x4);
  153. b43_phy_mask(dev, ctl_regs[i][1], ~0x1);
  154. b43_phy_set(dev, ctl_regs[i][0], 0x1);
  155. b43_httab_write(dev, B43_HTTAB16(8, 5 + (i * 0x10)), 0);
  156. b43_phy_mask(dev, ctl_regs[i][0], ~0x4);
  157. }
  158. }
  159. static void b43_phy_ht_bphy_init(struct b43_wldev *dev)
  160. {
  161. unsigned int i;
  162. u16 val;
  163. val = 0x1E1F;
  164. for (i = 0; i < 16; i++) {
  165. b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
  166. val -= 0x202;
  167. }
  168. val = 0x3E3F;
  169. for (i = 0; i < 16; i++) {
  170. b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
  171. val -= 0x202;
  172. }
  173. b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
  174. }
  175. /**************************************************
  176. * Channel switching ops.
  177. **************************************************/
  178. static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
  179. const struct b43_phy_ht_channeltab_e_phy *e,
  180. struct ieee80211_channel *new_channel)
  181. {
  182. bool old_band_5ghz;
  183. u8 i;
  184. old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */
  185. if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
  186. /* TODO */
  187. } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
  188. /* TODO */
  189. }
  190. b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);
  191. b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2);
  192. b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3);
  193. b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4);
  194. b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);
  195. b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);
  196. /* TODO: some ops on PHY regs 0x0B0 and 0xC0A */
  197. /* TODO: separated function? */
  198. for (i = 0; i < 3; i++) {
  199. u16 mask;
  200. u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8));
  201. if (0) /* FIXME */
  202. mask = 0x2 << (i * 4);
  203. else
  204. mask = 0;
  205. b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask);
  206. b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16);
  207. b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),
  208. tmp & 0xFF);
  209. b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),
  210. tmp & 0xFF);
  211. }
  212. b43_phy_write(dev, 0x017e, 0x3830);
  213. }
  214. static int b43_phy_ht_set_channel(struct b43_wldev *dev,
  215. struct ieee80211_channel *channel,
  216. enum nl80211_channel_type channel_type)
  217. {
  218. struct b43_phy *phy = &dev->phy;
  219. const struct b43_phy_ht_channeltab_e_radio2059 *chent_r2059 = NULL;
  220. if (phy->radio_ver == 0x2059) {
  221. chent_r2059 = b43_phy_ht_get_channeltab_e_r2059(dev,
  222. channel->center_freq);
  223. if (!chent_r2059)
  224. return -ESRCH;
  225. } else {
  226. return -ESRCH;
  227. }
  228. /* TODO: In case of N-PHY some bandwidth switching goes here */
  229. if (phy->radio_ver == 0x2059) {
  230. b43_radio_2059_channel_setup(dev, chent_r2059);
  231. b43_phy_ht_channel_setup(dev, &(chent_r2059->phy_regs),
  232. channel);
  233. } else {
  234. return -ESRCH;
  235. }
  236. return 0;
  237. }
  238. /**************************************************
  239. * Basic PHY ops.
  240. **************************************************/
  241. static int b43_phy_ht_op_allocate(struct b43_wldev *dev)
  242. {
  243. struct b43_phy_ht *phy_ht;
  244. phy_ht = kzalloc(sizeof(*phy_ht), GFP_KERNEL);
  245. if (!phy_ht)
  246. return -ENOMEM;
  247. dev->phy.ht = phy_ht;
  248. return 0;
  249. }
  250. static void b43_phy_ht_op_prepare_structs(struct b43_wldev *dev)
  251. {
  252. struct b43_phy *phy = &dev->phy;
  253. struct b43_phy_ht *phy_ht = phy->ht;
  254. memset(phy_ht, 0, sizeof(*phy_ht));
  255. }
  256. static int b43_phy_ht_op_init(struct b43_wldev *dev)
  257. {
  258. u8 i;
  259. u16 tmp;
  260. b43_phy_ht_tables_init(dev);
  261. b43_phy_mask(dev, 0x0be, ~0x2);
  262. b43_phy_set(dev, 0x23f, 0x7ff);
  263. b43_phy_set(dev, 0x240, 0x7ff);
  264. b43_phy_set(dev, 0x241, 0x7ff);
  265. b43_phy_ht_zero_extg(dev);
  266. b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3);
  267. b43_phy_write(dev, B43_PHY_HT_AFE_CTL1, 0);
  268. b43_phy_write(dev, B43_PHY_HT_AFE_CTL3, 0);
  269. b43_phy_write(dev, B43_PHY_HT_AFE_CTL5, 0);
  270. b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20);
  271. b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20);
  272. b43_phy_write(dev, 0x20d, 0xb8);
  273. b43_phy_write(dev, B43_PHY_EXTG(0x14f), 0xc8);
  274. b43_phy_write(dev, 0x70, 0x50);
  275. b43_phy_write(dev, 0x1ff, 0x30);
  276. if (0) /* TODO: condition */
  277. ; /* TODO: PHY op on reg 0x217 */
  278. b43_phy_read(dev, 0xb0); /* TODO: what for? */
  279. b43_phy_set(dev, 0xb0, 0x1);
  280. b43_phy_set(dev, 0xb1, 0x91);
  281. b43_phy_write(dev, 0x32f, 0x0003);
  282. b43_phy_write(dev, 0x077, 0x0010);
  283. b43_phy_write(dev, 0x0b4, 0x0258);
  284. b43_phy_mask(dev, 0x17e, ~0x4000);
  285. b43_phy_write(dev, 0x0b9, 0x0072);
  286. b43_httab_write_few(dev, B43_HTTAB16(7, 0x14e), 2, 0x010f, 0x010f);
  287. b43_httab_write_few(dev, B43_HTTAB16(7, 0x15e), 2, 0x010f, 0x010f);
  288. b43_httab_write_few(dev, B43_HTTAB16(7, 0x16e), 2, 0x010f, 0x010f);
  289. b43_phy_ht_afe_unk1(dev);
  290. b43_httab_write_few(dev, B43_HTTAB16(7, 0x130), 9, 0x777, 0x111, 0x111,
  291. 0x777, 0x111, 0x111, 0x777, 0x111, 0x111);
  292. b43_httab_write(dev, B43_HTTAB16(7, 0x120), 0x0777);
  293. b43_httab_write(dev, B43_HTTAB16(7, 0x124), 0x0777);
  294. b43_httab_write(dev, B43_HTTAB16(8, 0x00), 0x02);
  295. b43_httab_write(dev, B43_HTTAB16(8, 0x10), 0x02);
  296. b43_httab_write(dev, B43_HTTAB16(8, 0x20), 0x02);
  297. b43_httab_write_few(dev, B43_HTTAB16(8, 0x08), 4,
  298. 0x8e, 0x96, 0x96, 0x96);
  299. b43_httab_write_few(dev, B43_HTTAB16(8, 0x18), 4,
  300. 0x8f, 0x9f, 0x9f, 0x9f);
  301. b43_httab_write_few(dev, B43_HTTAB16(8, 0x28), 4,
  302. 0x8f, 0x9f, 0x9f, 0x9f);
  303. b43_httab_write_few(dev, B43_HTTAB16(8, 0x0c), 4, 0x2, 0x2, 0x2, 0x2);
  304. b43_httab_write_few(dev, B43_HTTAB16(8, 0x1c), 4, 0x2, 0x2, 0x2, 0x2);
  305. b43_httab_write_few(dev, B43_HTTAB16(8, 0x2c), 4, 0x2, 0x2, 0x2, 0x2);
  306. b43_phy_maskset(dev, 0x0280, 0xff00, 0x3e);
  307. b43_phy_maskset(dev, 0x0283, 0xff00, 0x3e);
  308. b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46);
  309. b43_phy_maskset(dev, 0x0283, 0xff00, 0x40);
  310. b43_httab_write_few(dev, B43_HTTAB16(00, 0x8), 4,
  311. 0x09, 0x0e, 0x13, 0x18);
  312. b43_httab_write_few(dev, B43_HTTAB16(01, 0x8), 4,
  313. 0x09, 0x0e, 0x13, 0x18);
  314. /* TODO: Did wl mean 2 instead of 40? */
  315. b43_httab_write_few(dev, B43_HTTAB16(40, 0x8), 4,
  316. 0x09, 0x0e, 0x13, 0x18);
  317. b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd);
  318. b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd);
  319. b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd);
  320. b43_phy_set(dev, B43_PHY_EXTG(0x060), 0x1);
  321. b43_phy_set(dev, B43_PHY_EXTG(0x064), 0x1);
  322. b43_phy_set(dev, B43_PHY_EXTG(0x080), 0x1);
  323. b43_phy_set(dev, B43_PHY_EXTG(0x084), 0x1);
  324. /* Copy some tables entries */
  325. tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x144));
  326. b43_httab_write(dev, B43_HTTAB16(7, 0x14a), tmp);
  327. tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x154));
  328. b43_httab_write(dev, B43_HTTAB16(7, 0x15a), tmp);
  329. tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x164));
  330. b43_httab_write(dev, B43_HTTAB16(7, 0x16a), tmp);
  331. /* Reset CCA */
  332. b43_phy_force_clock(dev, true);
  333. tmp = b43_phy_read(dev, B43_PHY_HT_BBCFG);
  334. b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp | B43_PHY_HT_BBCFG_RSTCCA);
  335. b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp & ~B43_PHY_HT_BBCFG_RSTCCA);
  336. b43_phy_force_clock(dev, false);
  337. b43_mac_phy_clock_set(dev, true);
  338. for (i = 0; i < 2; i++) {
  339. tmp = b43_phy_read(dev, B43_PHY_EXTG(0));
  340. b43_phy_set(dev, B43_PHY_EXTG(0), 0x3);
  341. b43_phy_set(dev, B43_PHY_EXTG(3), i ? 0x20 : 0x1);
  342. /* FIXME: wait for some bit to be cleared (find out which) */
  343. b43_phy_read(dev, B43_PHY_EXTG(4));
  344. b43_phy_write(dev, B43_PHY_EXTG(0), tmp);
  345. }
  346. /* TODO: PHY op on reg 0xb0 */
  347. /* TODO: PHY ops on regs 0x40e, 0x44e, 0x48e */
  348. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
  349. b43_phy_ht_bphy_init(dev);
  350. b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0),
  351. B43_HTTAB_1A_C0_LATE_SIZE, b43_httab_0x1a_0xc0_late);
  352. return 0;
  353. }
  354. static void b43_phy_ht_op_free(struct b43_wldev *dev)
  355. {
  356. struct b43_phy *phy = &dev->phy;
  357. struct b43_phy_ht *phy_ht = phy->ht;
  358. kfree(phy_ht);
  359. phy->ht = NULL;
  360. }
  361. /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
  362. static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev,
  363. bool blocked)
  364. {
  365. if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
  366. b43err(dev->wl, "MAC not suspended\n");
  367. /* In the following PHY ops we copy wl's dummy behaviour.
  368. * TODO: Find out if reads (currently hidden in masks/masksets) are
  369. * needed and replace following ops with just writes or w&r.
  370. * Note: B43_PHY_HT_RF_CTL1 register is tricky, wrong operation can
  371. * cause delayed (!) machine lock up. */
  372. if (blocked) {
  373. b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
  374. } else {
  375. b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
  376. b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x1);
  377. b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
  378. b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x2);
  379. if (dev->phy.radio_ver == 0x2059)
  380. b43_radio_2059_init(dev);
  381. else
  382. B43_WARN_ON(1);
  383. b43_switch_channel(dev, dev->phy.channel);
  384. }
  385. }
  386. static void b43_phy_ht_op_switch_analog(struct b43_wldev *dev, bool on)
  387. {
  388. if (on) {
  389. b43_phy_write(dev, B43_PHY_HT_AFE_CTL2, 0x00cd);
  390. b43_phy_write(dev, B43_PHY_HT_AFE_CTL1, 0x0000);
  391. b43_phy_write(dev, B43_PHY_HT_AFE_CTL4, 0x00cd);
  392. b43_phy_write(dev, B43_PHY_HT_AFE_CTL3, 0x0000);
  393. b43_phy_write(dev, B43_PHY_HT_AFE_CTL6, 0x00cd);
  394. b43_phy_write(dev, B43_PHY_HT_AFE_CTL5, 0x0000);
  395. } else {
  396. b43_phy_write(dev, B43_PHY_HT_AFE_CTL1, 0x07ff);
  397. b43_phy_write(dev, B43_PHY_HT_AFE_CTL2, 0x00fd);
  398. b43_phy_write(dev, B43_PHY_HT_AFE_CTL3, 0x07ff);
  399. b43_phy_write(dev, B43_PHY_HT_AFE_CTL4, 0x00fd);
  400. b43_phy_write(dev, B43_PHY_HT_AFE_CTL5, 0x07ff);
  401. b43_phy_write(dev, B43_PHY_HT_AFE_CTL6, 0x00fd);
  402. }
  403. }
  404. static int b43_phy_ht_op_switch_channel(struct b43_wldev *dev,
  405. unsigned int new_channel)
  406. {
  407. struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
  408. enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
  409. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  410. if ((new_channel < 1) || (new_channel > 14))
  411. return -EINVAL;
  412. } else {
  413. return -EINVAL;
  414. }
  415. return b43_phy_ht_set_channel(dev, channel, channel_type);
  416. }
  417. static unsigned int b43_phy_ht_op_get_default_chan(struct b43_wldev *dev)
  418. {
  419. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
  420. return 11;
  421. return 36;
  422. }
  423. /**************************************************
  424. * R/W ops.
  425. **************************************************/
  426. static u16 b43_phy_ht_op_read(struct b43_wldev *dev, u16 reg)
  427. {
  428. b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
  429. return b43_read16(dev, B43_MMIO_PHY_DATA);
  430. }
  431. static void b43_phy_ht_op_write(struct b43_wldev *dev, u16 reg, u16 value)
  432. {
  433. b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
  434. b43_write16(dev, B43_MMIO_PHY_DATA, value);
  435. }
  436. static void b43_phy_ht_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
  437. u16 set)
  438. {
  439. b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
  440. b43_write16(dev, B43_MMIO_PHY_DATA,
  441. (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
  442. }
  443. static u16 b43_phy_ht_op_radio_read(struct b43_wldev *dev, u16 reg)
  444. {
  445. /* HT-PHY needs 0x200 for read access */
  446. reg |= 0x200;
  447. b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
  448. return b43_read16(dev, B43_MMIO_RADIO24_DATA);
  449. }
  450. static void b43_phy_ht_op_radio_write(struct b43_wldev *dev, u16 reg,
  451. u16 value)
  452. {
  453. b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
  454. b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
  455. }
  456. static enum b43_txpwr_result
  457. b43_phy_ht_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
  458. {
  459. return B43_TXPWR_RES_DONE;
  460. }
  461. static void b43_phy_ht_op_adjust_txpower(struct b43_wldev *dev)
  462. {
  463. }
  464. /**************************************************
  465. * PHY ops struct.
  466. **************************************************/
  467. const struct b43_phy_operations b43_phyops_ht = {
  468. .allocate = b43_phy_ht_op_allocate,
  469. .free = b43_phy_ht_op_free,
  470. .prepare_structs = b43_phy_ht_op_prepare_structs,
  471. .init = b43_phy_ht_op_init,
  472. .phy_read = b43_phy_ht_op_read,
  473. .phy_write = b43_phy_ht_op_write,
  474. .phy_maskset = b43_phy_ht_op_maskset,
  475. .radio_read = b43_phy_ht_op_radio_read,
  476. .radio_write = b43_phy_ht_op_radio_write,
  477. .software_rfkill = b43_phy_ht_op_software_rfkill,
  478. .switch_analog = b43_phy_ht_op_switch_analog,
  479. .switch_channel = b43_phy_ht_op_switch_channel,
  480. .get_default_chan = b43_phy_ht_op_get_default_chan,
  481. .recalc_txpower = b43_phy_ht_op_recalc_txpower,
  482. .adjust_txpower = b43_phy_ht_op_adjust_txpower,
  483. };