cputable.c 28 KB

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  1. /*
  2. * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  3. *
  4. * Modifications for ppc64:
  5. * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/config.h>
  13. #include <linux/string.h>
  14. #include <linux/sched.h>
  15. #include <linux/threads.h>
  16. #include <linux/init.h>
  17. #include <linux/module.h>
  18. #include <asm/oprofile_impl.h>
  19. #include <asm/cputable.h>
  20. struct cpu_spec* cur_cpu_spec = NULL;
  21. EXPORT_SYMBOL(cur_cpu_spec);
  22. /* NOTE:
  23. * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  24. * the responsibility of the appropriate CPU save/restore functions to
  25. * eventually copy these settings over. Those save/restore aren't yet
  26. * part of the cputable though. That has to be fixed for both ppc32
  27. * and ppc64
  28. */
  29. #ifdef CONFIG_PPC64
  30. extern void __setup_cpu_power3(unsigned long offset, struct cpu_spec* spec);
  31. extern void __setup_cpu_power4(unsigned long offset, struct cpu_spec* spec);
  32. extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
  33. #else
  34. extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
  35. extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
  36. extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
  37. extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
  38. extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
  39. extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
  40. extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
  41. extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
  42. #endif /* CONFIG_PPC32 */
  43. extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  44. /* This table only contains "desktop" CPUs, it need to be filled with embedded
  45. * ones as well...
  46. */
  47. #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  48. PPC_FEATURE_HAS_MMU)
  49. #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
  50. #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
  51. #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5)
  52. #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS)
  53. /* We only set the spe features if the kernel was compiled with
  54. * spe support
  55. */
  56. #ifdef CONFIG_SPE
  57. #define PPC_FEATURE_SPE_COMP PPC_FEATURE_HAS_SPE
  58. #else
  59. #define PPC_FEATURE_SPE_COMP 0
  60. #endif
  61. struct cpu_spec cpu_specs[] = {
  62. #ifdef CONFIG_PPC64
  63. { /* Power3 */
  64. .pvr_mask = 0xffff0000,
  65. .pvr_value = 0x00400000,
  66. .cpu_name = "POWER3 (630)",
  67. .cpu_features = CPU_FTRS_POWER3,
  68. .cpu_user_features = COMMON_USER_PPC64,
  69. .icache_bsize = 128,
  70. .dcache_bsize = 128,
  71. .num_pmcs = 8,
  72. .cpu_setup = __setup_cpu_power3,
  73. .oprofile_cpu_type = "ppc64/power3",
  74. .oprofile_type = RS64,
  75. },
  76. { /* Power3+ */
  77. .pvr_mask = 0xffff0000,
  78. .pvr_value = 0x00410000,
  79. .cpu_name = "POWER3 (630+)",
  80. .cpu_features = CPU_FTRS_POWER3,
  81. .cpu_user_features = COMMON_USER_PPC64,
  82. .icache_bsize = 128,
  83. .dcache_bsize = 128,
  84. .num_pmcs = 8,
  85. .cpu_setup = __setup_cpu_power3,
  86. .oprofile_cpu_type = "ppc64/power3",
  87. .oprofile_type = RS64,
  88. },
  89. { /* Northstar */
  90. .pvr_mask = 0xffff0000,
  91. .pvr_value = 0x00330000,
  92. .cpu_name = "RS64-II (northstar)",
  93. .cpu_features = CPU_FTRS_RS64,
  94. .cpu_user_features = COMMON_USER_PPC64,
  95. .icache_bsize = 128,
  96. .dcache_bsize = 128,
  97. .num_pmcs = 8,
  98. .cpu_setup = __setup_cpu_power3,
  99. .oprofile_cpu_type = "ppc64/rs64",
  100. .oprofile_type = RS64,
  101. },
  102. { /* Pulsar */
  103. .pvr_mask = 0xffff0000,
  104. .pvr_value = 0x00340000,
  105. .cpu_name = "RS64-III (pulsar)",
  106. .cpu_features = CPU_FTRS_RS64,
  107. .cpu_user_features = COMMON_USER_PPC64,
  108. .icache_bsize = 128,
  109. .dcache_bsize = 128,
  110. .num_pmcs = 8,
  111. .cpu_setup = __setup_cpu_power3,
  112. .oprofile_cpu_type = "ppc64/rs64",
  113. .oprofile_type = RS64,
  114. },
  115. { /* I-star */
  116. .pvr_mask = 0xffff0000,
  117. .pvr_value = 0x00360000,
  118. .cpu_name = "RS64-III (icestar)",
  119. .cpu_features = CPU_FTRS_RS64,
  120. .cpu_user_features = COMMON_USER_PPC64,
  121. .icache_bsize = 128,
  122. .dcache_bsize = 128,
  123. .num_pmcs = 8,
  124. .cpu_setup = __setup_cpu_power3,
  125. .oprofile_cpu_type = "ppc64/rs64",
  126. .oprofile_type = RS64,
  127. },
  128. { /* S-star */
  129. .pvr_mask = 0xffff0000,
  130. .pvr_value = 0x00370000,
  131. .cpu_name = "RS64-IV (sstar)",
  132. .cpu_features = CPU_FTRS_RS64,
  133. .cpu_user_features = COMMON_USER_PPC64,
  134. .icache_bsize = 128,
  135. .dcache_bsize = 128,
  136. .num_pmcs = 8,
  137. .cpu_setup = __setup_cpu_power3,
  138. .oprofile_cpu_type = "ppc64/rs64",
  139. .oprofile_type = RS64,
  140. },
  141. { /* Power4 */
  142. .pvr_mask = 0xffff0000,
  143. .pvr_value = 0x00350000,
  144. .cpu_name = "POWER4 (gp)",
  145. .cpu_features = CPU_FTRS_POWER4,
  146. .cpu_user_features = COMMON_USER_POWER4,
  147. .icache_bsize = 128,
  148. .dcache_bsize = 128,
  149. .num_pmcs = 8,
  150. .cpu_setup = __setup_cpu_power4,
  151. .oprofile_cpu_type = "ppc64/power4",
  152. .oprofile_type = POWER4,
  153. },
  154. { /* Power4+ */
  155. .pvr_mask = 0xffff0000,
  156. .pvr_value = 0x00380000,
  157. .cpu_name = "POWER4+ (gq)",
  158. .cpu_features = CPU_FTRS_POWER4,
  159. .cpu_user_features = COMMON_USER_POWER4,
  160. .icache_bsize = 128,
  161. .dcache_bsize = 128,
  162. .num_pmcs = 8,
  163. .cpu_setup = __setup_cpu_power4,
  164. .oprofile_cpu_type = "ppc64/power4",
  165. .oprofile_type = POWER4,
  166. },
  167. { /* PPC970 */
  168. .pvr_mask = 0xffff0000,
  169. .pvr_value = 0x00390000,
  170. .cpu_name = "PPC970",
  171. .cpu_features = CPU_FTRS_PPC970,
  172. .cpu_user_features = COMMON_USER_POWER4 |
  173. PPC_FEATURE_HAS_ALTIVEC_COMP,
  174. .icache_bsize = 128,
  175. .dcache_bsize = 128,
  176. .num_pmcs = 8,
  177. .cpu_setup = __setup_cpu_ppc970,
  178. .oprofile_cpu_type = "ppc64/970",
  179. .oprofile_type = POWER4,
  180. },
  181. #endif /* CONFIG_PPC64 */
  182. #if defined(CONFIG_PPC64) || defined(CONFIG_POWER4)
  183. { /* PPC970FX */
  184. .pvr_mask = 0xffff0000,
  185. .pvr_value = 0x003c0000,
  186. .cpu_name = "PPC970FX",
  187. #ifdef CONFIG_PPC32
  188. .cpu_features = CPU_FTRS_970_32,
  189. #else
  190. .cpu_features = CPU_FTRS_PPC970,
  191. #endif
  192. .cpu_user_features = COMMON_USER_POWER4 |
  193. PPC_FEATURE_HAS_ALTIVEC_COMP,
  194. .icache_bsize = 128,
  195. .dcache_bsize = 128,
  196. .num_pmcs = 8,
  197. .cpu_setup = __setup_cpu_ppc970,
  198. .oprofile_cpu_type = "ppc64/970",
  199. .oprofile_type = POWER4,
  200. },
  201. #endif /* defined(CONFIG_PPC64) || defined(CONFIG_POWER4) */
  202. #ifdef CONFIG_PPC64
  203. { /* PPC970MP */
  204. .pvr_mask = 0xffff0000,
  205. .pvr_value = 0x00440000,
  206. .cpu_name = "PPC970MP",
  207. .cpu_features = CPU_FTRS_PPC970,
  208. .cpu_user_features = COMMON_USER_POWER4 |
  209. PPC_FEATURE_HAS_ALTIVEC_COMP,
  210. .icache_bsize = 128,
  211. .dcache_bsize = 128,
  212. .cpu_setup = __setup_cpu_ppc970,
  213. .oprofile_cpu_type = "ppc64/970",
  214. .oprofile_type = POWER4,
  215. },
  216. { /* Power5 GR */
  217. .pvr_mask = 0xffff0000,
  218. .pvr_value = 0x003a0000,
  219. .cpu_name = "POWER5 (gr)",
  220. .cpu_features = CPU_FTRS_POWER5,
  221. .cpu_user_features = COMMON_USER_POWER5,
  222. .icache_bsize = 128,
  223. .dcache_bsize = 128,
  224. .num_pmcs = 6,
  225. .cpu_setup = __setup_cpu_power4,
  226. .oprofile_cpu_type = "ppc64/power5",
  227. .oprofile_type = POWER4,
  228. },
  229. { /* Power5 GS */
  230. .pvr_mask = 0xffff0000,
  231. .pvr_value = 0x003b0000,
  232. .cpu_name = "POWER5+ (gs)",
  233. .cpu_features = CPU_FTRS_POWER5,
  234. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  235. .icache_bsize = 128,
  236. .dcache_bsize = 128,
  237. .num_pmcs = 6,
  238. .cpu_setup = __setup_cpu_power4,
  239. .oprofile_cpu_type = "ppc64/power5+",
  240. .oprofile_type = POWER4,
  241. },
  242. { /* Cell Broadband Engine */
  243. .pvr_mask = 0xffff0000,
  244. .pvr_value = 0x00700000,
  245. .cpu_name = "Cell Broadband Engine",
  246. .cpu_features = CPU_FTRS_CELL,
  247. .cpu_user_features = COMMON_USER_PPC64 |
  248. PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP,
  249. .icache_bsize = 128,
  250. .dcache_bsize = 128,
  251. .cpu_setup = __setup_cpu_be,
  252. },
  253. { /* default match */
  254. .pvr_mask = 0x00000000,
  255. .pvr_value = 0x00000000,
  256. .cpu_name = "POWER4 (compatible)",
  257. .cpu_features = CPU_FTRS_COMPATIBLE,
  258. .cpu_user_features = COMMON_USER_PPC64,
  259. .icache_bsize = 128,
  260. .dcache_bsize = 128,
  261. .num_pmcs = 6,
  262. .cpu_setup = __setup_cpu_power4,
  263. }
  264. #endif /* CONFIG_PPC64 */
  265. #ifdef CONFIG_PPC32
  266. #if CLASSIC_PPC
  267. { /* 601 */
  268. .pvr_mask = 0xffff0000,
  269. .pvr_value = 0x00010000,
  270. .cpu_name = "601",
  271. .cpu_features = CPU_FTRS_PPC601,
  272. .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
  273. PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
  274. .icache_bsize = 32,
  275. .dcache_bsize = 32,
  276. },
  277. { /* 603 */
  278. .pvr_mask = 0xffff0000,
  279. .pvr_value = 0x00030000,
  280. .cpu_name = "603",
  281. .cpu_features = CPU_FTRS_603,
  282. .cpu_user_features = COMMON_USER,
  283. .icache_bsize = 32,
  284. .dcache_bsize = 32,
  285. .cpu_setup = __setup_cpu_603
  286. },
  287. { /* 603e */
  288. .pvr_mask = 0xffff0000,
  289. .pvr_value = 0x00060000,
  290. .cpu_name = "603e",
  291. .cpu_features = CPU_FTRS_603,
  292. .cpu_user_features = COMMON_USER,
  293. .icache_bsize = 32,
  294. .dcache_bsize = 32,
  295. .cpu_setup = __setup_cpu_603
  296. },
  297. { /* 603ev */
  298. .pvr_mask = 0xffff0000,
  299. .pvr_value = 0x00070000,
  300. .cpu_name = "603ev",
  301. .cpu_features = CPU_FTRS_603,
  302. .cpu_user_features = COMMON_USER,
  303. .icache_bsize = 32,
  304. .dcache_bsize = 32,
  305. .cpu_setup = __setup_cpu_603
  306. },
  307. { /* 604 */
  308. .pvr_mask = 0xffff0000,
  309. .pvr_value = 0x00040000,
  310. .cpu_name = "604",
  311. .cpu_features = CPU_FTRS_604,
  312. .cpu_user_features = COMMON_USER,
  313. .icache_bsize = 32,
  314. .dcache_bsize = 32,
  315. .num_pmcs = 2,
  316. .cpu_setup = __setup_cpu_604
  317. },
  318. { /* 604e */
  319. .pvr_mask = 0xfffff000,
  320. .pvr_value = 0x00090000,
  321. .cpu_name = "604e",
  322. .cpu_features = CPU_FTRS_604,
  323. .cpu_user_features = COMMON_USER,
  324. .icache_bsize = 32,
  325. .dcache_bsize = 32,
  326. .num_pmcs = 4,
  327. .cpu_setup = __setup_cpu_604
  328. },
  329. { /* 604r */
  330. .pvr_mask = 0xffff0000,
  331. .pvr_value = 0x00090000,
  332. .cpu_name = "604r",
  333. .cpu_features = CPU_FTRS_604,
  334. .cpu_user_features = COMMON_USER,
  335. .icache_bsize = 32,
  336. .dcache_bsize = 32,
  337. .num_pmcs = 4,
  338. .cpu_setup = __setup_cpu_604
  339. },
  340. { /* 604ev */
  341. .pvr_mask = 0xffff0000,
  342. .pvr_value = 0x000a0000,
  343. .cpu_name = "604ev",
  344. .cpu_features = CPU_FTRS_604,
  345. .cpu_user_features = COMMON_USER,
  346. .icache_bsize = 32,
  347. .dcache_bsize = 32,
  348. .num_pmcs = 4,
  349. .cpu_setup = __setup_cpu_604
  350. },
  351. { /* 740/750 (0x4202, don't support TAU ?) */
  352. .pvr_mask = 0xffffffff,
  353. .pvr_value = 0x00084202,
  354. .cpu_name = "740/750",
  355. .cpu_features = CPU_FTRS_740_NOTAU,
  356. .cpu_user_features = COMMON_USER,
  357. .icache_bsize = 32,
  358. .dcache_bsize = 32,
  359. .num_pmcs = 4,
  360. .cpu_setup = __setup_cpu_750
  361. },
  362. { /* 750CX (80100 and 8010x?) */
  363. .pvr_mask = 0xfffffff0,
  364. .pvr_value = 0x00080100,
  365. .cpu_name = "750CX",
  366. .cpu_features = CPU_FTRS_750,
  367. .cpu_user_features = COMMON_USER,
  368. .icache_bsize = 32,
  369. .dcache_bsize = 32,
  370. .num_pmcs = 4,
  371. .cpu_setup = __setup_cpu_750cx
  372. },
  373. { /* 750CX (82201 and 82202) */
  374. .pvr_mask = 0xfffffff0,
  375. .pvr_value = 0x00082200,
  376. .cpu_name = "750CX",
  377. .cpu_features = CPU_FTRS_750,
  378. .cpu_user_features = COMMON_USER,
  379. .icache_bsize = 32,
  380. .dcache_bsize = 32,
  381. .num_pmcs = 4,
  382. .cpu_setup = __setup_cpu_750cx
  383. },
  384. { /* 750CXe (82214) */
  385. .pvr_mask = 0xfffffff0,
  386. .pvr_value = 0x00082210,
  387. .cpu_name = "750CXe",
  388. .cpu_features = CPU_FTRS_750,
  389. .cpu_user_features = COMMON_USER,
  390. .icache_bsize = 32,
  391. .dcache_bsize = 32,
  392. .num_pmcs = 4,
  393. .cpu_setup = __setup_cpu_750cx
  394. },
  395. { /* 750CXe "Gekko" (83214) */
  396. .pvr_mask = 0xffffffff,
  397. .pvr_value = 0x00083214,
  398. .cpu_name = "750CXe",
  399. .cpu_features = CPU_FTRS_750,
  400. .cpu_user_features = COMMON_USER,
  401. .icache_bsize = 32,
  402. .dcache_bsize = 32,
  403. .num_pmcs = 4,
  404. .cpu_setup = __setup_cpu_750cx
  405. },
  406. { /* 745/755 */
  407. .pvr_mask = 0xfffff000,
  408. .pvr_value = 0x00083000,
  409. .cpu_name = "745/755",
  410. .cpu_features = CPU_FTRS_750,
  411. .cpu_user_features = COMMON_USER,
  412. .icache_bsize = 32,
  413. .dcache_bsize = 32,
  414. .num_pmcs = 4,
  415. .cpu_setup = __setup_cpu_750
  416. },
  417. { /* 750FX rev 1.x */
  418. .pvr_mask = 0xffffff00,
  419. .pvr_value = 0x70000100,
  420. .cpu_name = "750FX",
  421. .cpu_features = CPU_FTRS_750FX1,
  422. .cpu_user_features = COMMON_USER,
  423. .icache_bsize = 32,
  424. .dcache_bsize = 32,
  425. .num_pmcs = 4,
  426. .cpu_setup = __setup_cpu_750
  427. },
  428. { /* 750FX rev 2.0 must disable HID0[DPM] */
  429. .pvr_mask = 0xffffffff,
  430. .pvr_value = 0x70000200,
  431. .cpu_name = "750FX",
  432. .cpu_features = CPU_FTRS_750FX2,
  433. .cpu_user_features = COMMON_USER,
  434. .icache_bsize = 32,
  435. .dcache_bsize = 32,
  436. .num_pmcs = 4,
  437. .cpu_setup = __setup_cpu_750
  438. },
  439. { /* 750FX (All revs except 2.0) */
  440. .pvr_mask = 0xffff0000,
  441. .pvr_value = 0x70000000,
  442. .cpu_name = "750FX",
  443. .cpu_features = CPU_FTRS_750FX,
  444. .cpu_user_features = COMMON_USER,
  445. .icache_bsize = 32,
  446. .dcache_bsize = 32,
  447. .num_pmcs = 4,
  448. .cpu_setup = __setup_cpu_750fx
  449. },
  450. { /* 750GX */
  451. .pvr_mask = 0xffff0000,
  452. .pvr_value = 0x70020000,
  453. .cpu_name = "750GX",
  454. .cpu_features = CPU_FTRS_750GX,
  455. .cpu_user_features = COMMON_USER,
  456. .icache_bsize = 32,
  457. .dcache_bsize = 32,
  458. .num_pmcs = 4,
  459. .cpu_setup = __setup_cpu_750fx
  460. },
  461. { /* 740/750 (L2CR bit need fixup for 740) */
  462. .pvr_mask = 0xffff0000,
  463. .pvr_value = 0x00080000,
  464. .cpu_name = "740/750",
  465. .cpu_features = CPU_FTRS_740,
  466. .cpu_user_features = COMMON_USER,
  467. .icache_bsize = 32,
  468. .dcache_bsize = 32,
  469. .num_pmcs = 4,
  470. .cpu_setup = __setup_cpu_750
  471. },
  472. { /* 7400 rev 1.1 ? (no TAU) */
  473. .pvr_mask = 0xffffffff,
  474. .pvr_value = 0x000c1101,
  475. .cpu_name = "7400 (1.1)",
  476. .cpu_features = CPU_FTRS_7400_NOTAU,
  477. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  478. .icache_bsize = 32,
  479. .dcache_bsize = 32,
  480. .num_pmcs = 4,
  481. .cpu_setup = __setup_cpu_7400
  482. },
  483. { /* 7400 */
  484. .pvr_mask = 0xffff0000,
  485. .pvr_value = 0x000c0000,
  486. .cpu_name = "7400",
  487. .cpu_features = CPU_FTRS_7400,
  488. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  489. .icache_bsize = 32,
  490. .dcache_bsize = 32,
  491. .num_pmcs = 4,
  492. .cpu_setup = __setup_cpu_7400
  493. },
  494. { /* 7410 */
  495. .pvr_mask = 0xffff0000,
  496. .pvr_value = 0x800c0000,
  497. .cpu_name = "7410",
  498. .cpu_features = CPU_FTRS_7400,
  499. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  500. .icache_bsize = 32,
  501. .dcache_bsize = 32,
  502. .num_pmcs = 4,
  503. .cpu_setup = __setup_cpu_7410
  504. },
  505. { /* 7450 2.0 - no doze/nap */
  506. .pvr_mask = 0xffffffff,
  507. .pvr_value = 0x80000200,
  508. .cpu_name = "7450",
  509. .cpu_features = CPU_FTRS_7450_20,
  510. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  511. .icache_bsize = 32,
  512. .dcache_bsize = 32,
  513. .num_pmcs = 6,
  514. .cpu_setup = __setup_cpu_745x,
  515. .oprofile_cpu_type = "ppc/7450",
  516. .oprofile_type = G4,
  517. },
  518. { /* 7450 2.1 */
  519. .pvr_mask = 0xffffffff,
  520. .pvr_value = 0x80000201,
  521. .cpu_name = "7450",
  522. .cpu_features = CPU_FTRS_7450_21,
  523. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  524. .icache_bsize = 32,
  525. .dcache_bsize = 32,
  526. .num_pmcs = 6,
  527. .cpu_setup = __setup_cpu_745x,
  528. .oprofile_cpu_type = "ppc/7450",
  529. .oprofile_type = G4,
  530. },
  531. { /* 7450 2.3 and newer */
  532. .pvr_mask = 0xffff0000,
  533. .pvr_value = 0x80000000,
  534. .cpu_name = "7450",
  535. .cpu_features = CPU_FTRS_7450_23,
  536. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  537. .icache_bsize = 32,
  538. .dcache_bsize = 32,
  539. .num_pmcs = 6,
  540. .cpu_setup = __setup_cpu_745x,
  541. .oprofile_cpu_type = "ppc/7450",
  542. .oprofile_type = G4,
  543. },
  544. { /* 7455 rev 1.x */
  545. .pvr_mask = 0xffffff00,
  546. .pvr_value = 0x80010100,
  547. .cpu_name = "7455",
  548. .cpu_features = CPU_FTRS_7455_1,
  549. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  550. .icache_bsize = 32,
  551. .dcache_bsize = 32,
  552. .num_pmcs = 6,
  553. .cpu_setup = __setup_cpu_745x,
  554. .oprofile_cpu_type = "ppc/7450",
  555. .oprofile_type = G4,
  556. },
  557. { /* 7455 rev 2.0 */
  558. .pvr_mask = 0xffffffff,
  559. .pvr_value = 0x80010200,
  560. .cpu_name = "7455",
  561. .cpu_features = CPU_FTRS_7455_20,
  562. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  563. .icache_bsize = 32,
  564. .dcache_bsize = 32,
  565. .num_pmcs = 6,
  566. .cpu_setup = __setup_cpu_745x,
  567. .oprofile_cpu_type = "ppc/7450",
  568. .oprofile_type = G4,
  569. },
  570. { /* 7455 others */
  571. .pvr_mask = 0xffff0000,
  572. .pvr_value = 0x80010000,
  573. .cpu_name = "7455",
  574. .cpu_features = CPU_FTRS_7455,
  575. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  576. .icache_bsize = 32,
  577. .dcache_bsize = 32,
  578. .num_pmcs = 6,
  579. .cpu_setup = __setup_cpu_745x,
  580. .oprofile_cpu_type = "ppc/7450",
  581. .oprofile_type = G4,
  582. },
  583. { /* 7447/7457 Rev 1.0 */
  584. .pvr_mask = 0xffffffff,
  585. .pvr_value = 0x80020100,
  586. .cpu_name = "7447/7457",
  587. .cpu_features = CPU_FTRS_7447_10,
  588. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  589. .icache_bsize = 32,
  590. .dcache_bsize = 32,
  591. .num_pmcs = 6,
  592. .cpu_setup = __setup_cpu_745x,
  593. .oprofile_cpu_type = "ppc/7450",
  594. .oprofile_type = G4,
  595. },
  596. { /* 7447/7457 Rev 1.1 */
  597. .pvr_mask = 0xffffffff,
  598. .pvr_value = 0x80020101,
  599. .cpu_name = "7447/7457",
  600. .cpu_features = CPU_FTRS_7447_10,
  601. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  602. .icache_bsize = 32,
  603. .dcache_bsize = 32,
  604. .num_pmcs = 6,
  605. .cpu_setup = __setup_cpu_745x,
  606. .oprofile_cpu_type = "ppc/7450",
  607. .oprofile_type = G4,
  608. },
  609. { /* 7447/7457 Rev 1.2 and later */
  610. .pvr_mask = 0xffff0000,
  611. .pvr_value = 0x80020000,
  612. .cpu_name = "7447/7457",
  613. .cpu_features = CPU_FTRS_7447,
  614. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  615. .icache_bsize = 32,
  616. .dcache_bsize = 32,
  617. .num_pmcs = 6,
  618. .cpu_setup = __setup_cpu_745x,
  619. .oprofile_cpu_type = "ppc/7450",
  620. .oprofile_type = G4,
  621. },
  622. { /* 7447A */
  623. .pvr_mask = 0xffff0000,
  624. .pvr_value = 0x80030000,
  625. .cpu_name = "7447A",
  626. .cpu_features = CPU_FTRS_7447A,
  627. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  628. .icache_bsize = 32,
  629. .dcache_bsize = 32,
  630. .num_pmcs = 6,
  631. .cpu_setup = __setup_cpu_745x,
  632. .oprofile_cpu_type = "ppc/7450",
  633. .oprofile_type = G4,
  634. },
  635. { /* 7448 */
  636. .pvr_mask = 0xffff0000,
  637. .pvr_value = 0x80040000,
  638. .cpu_name = "7448",
  639. .cpu_features = CPU_FTRS_7447A,
  640. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  641. .icache_bsize = 32,
  642. .dcache_bsize = 32,
  643. .num_pmcs = 6,
  644. .cpu_setup = __setup_cpu_745x,
  645. .oprofile_cpu_type = "ppc/7450",
  646. .oprofile_type = G4,
  647. },
  648. { /* 82xx (8240, 8245, 8260 are all 603e cores) */
  649. .pvr_mask = 0x7fff0000,
  650. .pvr_value = 0x00810000,
  651. .cpu_name = "82xx",
  652. .cpu_features = CPU_FTRS_82XX,
  653. .cpu_user_features = COMMON_USER,
  654. .icache_bsize = 32,
  655. .dcache_bsize = 32,
  656. .cpu_setup = __setup_cpu_603
  657. },
  658. { /* All G2_LE (603e core, plus some) have the same pvr */
  659. .pvr_mask = 0x7fff0000,
  660. .pvr_value = 0x00820000,
  661. .cpu_name = "G2_LE",
  662. .cpu_features = CPU_FTRS_G2_LE,
  663. .cpu_user_features = COMMON_USER,
  664. .icache_bsize = 32,
  665. .dcache_bsize = 32,
  666. .cpu_setup = __setup_cpu_603
  667. },
  668. { /* e300 (a 603e core, plus some) on 83xx */
  669. .pvr_mask = 0x7fff0000,
  670. .pvr_value = 0x00830000,
  671. .cpu_name = "e300",
  672. .cpu_features = CPU_FTRS_E300,
  673. .cpu_user_features = COMMON_USER,
  674. .icache_bsize = 32,
  675. .dcache_bsize = 32,
  676. .cpu_setup = __setup_cpu_603
  677. },
  678. { /* default match, we assume split I/D cache & TB (non-601)... */
  679. .pvr_mask = 0x00000000,
  680. .pvr_value = 0x00000000,
  681. .cpu_name = "(generic PPC)",
  682. .cpu_features = CPU_FTRS_CLASSIC32,
  683. .cpu_user_features = COMMON_USER,
  684. .icache_bsize = 32,
  685. .dcache_bsize = 32,
  686. },
  687. #endif /* CLASSIC_PPC */
  688. #ifdef CONFIG_8xx
  689. { /* 8xx */
  690. .pvr_mask = 0xffff0000,
  691. .pvr_value = 0x00500000,
  692. .cpu_name = "8xx",
  693. /* CPU_FTR_MAYBE_CAN_DOZE is possible,
  694. * if the 8xx code is there.... */
  695. .cpu_features = CPU_FTRS_8XX,
  696. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  697. .icache_bsize = 16,
  698. .dcache_bsize = 16,
  699. },
  700. #endif /* CONFIG_8xx */
  701. #ifdef CONFIG_40x
  702. { /* 403GC */
  703. .pvr_mask = 0xffffff00,
  704. .pvr_value = 0x00200200,
  705. .cpu_name = "403GC",
  706. .cpu_features = CPU_FTRS_40X,
  707. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  708. .icache_bsize = 16,
  709. .dcache_bsize = 16,
  710. },
  711. { /* 403GCX */
  712. .pvr_mask = 0xffffff00,
  713. .pvr_value = 0x00201400,
  714. .cpu_name = "403GCX",
  715. .cpu_features = CPU_FTRS_40X,
  716. .cpu_user_features = PPC_FEATURE_32 |
  717. PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
  718. .icache_bsize = 16,
  719. .dcache_bsize = 16,
  720. },
  721. { /* 403G ?? */
  722. .pvr_mask = 0xffff0000,
  723. .pvr_value = 0x00200000,
  724. .cpu_name = "403G ??",
  725. .cpu_features = CPU_FTRS_40X,
  726. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  727. .icache_bsize = 16,
  728. .dcache_bsize = 16,
  729. },
  730. { /* 405GP */
  731. .pvr_mask = 0xffff0000,
  732. .pvr_value = 0x40110000,
  733. .cpu_name = "405GP",
  734. .cpu_features = CPU_FTRS_40X,
  735. .cpu_user_features = PPC_FEATURE_32 |
  736. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  737. .icache_bsize = 32,
  738. .dcache_bsize = 32,
  739. },
  740. { /* STB 03xxx */
  741. .pvr_mask = 0xffff0000,
  742. .pvr_value = 0x40130000,
  743. .cpu_name = "STB03xxx",
  744. .cpu_features = CPU_FTRS_40X,
  745. .cpu_user_features = PPC_FEATURE_32 |
  746. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  747. .icache_bsize = 32,
  748. .dcache_bsize = 32,
  749. },
  750. { /* STB 04xxx */
  751. .pvr_mask = 0xffff0000,
  752. .pvr_value = 0x41810000,
  753. .cpu_name = "STB04xxx",
  754. .cpu_features = CPU_FTRS_40X,
  755. .cpu_user_features = PPC_FEATURE_32 |
  756. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  757. .icache_bsize = 32,
  758. .dcache_bsize = 32,
  759. },
  760. { /* NP405L */
  761. .pvr_mask = 0xffff0000,
  762. .pvr_value = 0x41610000,
  763. .cpu_name = "NP405L",
  764. .cpu_features = CPU_FTRS_40X,
  765. .cpu_user_features = PPC_FEATURE_32 |
  766. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  767. .icache_bsize = 32,
  768. .dcache_bsize = 32,
  769. },
  770. { /* NP4GS3 */
  771. .pvr_mask = 0xffff0000,
  772. .pvr_value = 0x40B10000,
  773. .cpu_name = "NP4GS3",
  774. .cpu_features = CPU_FTRS_40X,
  775. .cpu_user_features = PPC_FEATURE_32 |
  776. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  777. .icache_bsize = 32,
  778. .dcache_bsize = 32,
  779. },
  780. { /* NP405H */
  781. .pvr_mask = 0xffff0000,
  782. .pvr_value = 0x41410000,
  783. .cpu_name = "NP405H",
  784. .cpu_features = CPU_FTRS_40X,
  785. .cpu_user_features = PPC_FEATURE_32 |
  786. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  787. .icache_bsize = 32,
  788. .dcache_bsize = 32,
  789. },
  790. { /* 405GPr */
  791. .pvr_mask = 0xffff0000,
  792. .pvr_value = 0x50910000,
  793. .cpu_name = "405GPr",
  794. .cpu_features = CPU_FTRS_40X,
  795. .cpu_user_features = PPC_FEATURE_32 |
  796. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  797. .icache_bsize = 32,
  798. .dcache_bsize = 32,
  799. },
  800. { /* STBx25xx */
  801. .pvr_mask = 0xffff0000,
  802. .pvr_value = 0x51510000,
  803. .cpu_name = "STBx25xx",
  804. .cpu_features = CPU_FTRS_40X,
  805. .cpu_user_features = PPC_FEATURE_32 |
  806. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  807. .icache_bsize = 32,
  808. .dcache_bsize = 32,
  809. },
  810. { /* 405LP */
  811. .pvr_mask = 0xffff0000,
  812. .pvr_value = 0x41F10000,
  813. .cpu_name = "405LP",
  814. .cpu_features = CPU_FTRS_40X,
  815. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  816. .icache_bsize = 32,
  817. .dcache_bsize = 32,
  818. },
  819. { /* Xilinx Virtex-II Pro */
  820. .pvr_mask = 0xffff0000,
  821. .pvr_value = 0x20010000,
  822. .cpu_name = "Virtex-II Pro",
  823. .cpu_features = CPU_FTRS_40X,
  824. .cpu_user_features = PPC_FEATURE_32 |
  825. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  826. .icache_bsize = 32,
  827. .dcache_bsize = 32,
  828. },
  829. { /* 405EP */
  830. .pvr_mask = 0xffff0000,
  831. .pvr_value = 0x51210000,
  832. .cpu_name = "405EP",
  833. .cpu_features = CPU_FTRS_40X,
  834. .cpu_user_features = PPC_FEATURE_32 |
  835. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  836. .icache_bsize = 32,
  837. .dcache_bsize = 32,
  838. },
  839. #endif /* CONFIG_40x */
  840. #ifdef CONFIG_44x
  841. {
  842. .pvr_mask = 0xf0000fff,
  843. .pvr_value = 0x40000850,
  844. .cpu_name = "440EP Rev. A",
  845. .cpu_features = CPU_FTRS_44X,
  846. .cpu_user_features = COMMON_USER, /* 440EP has an FPU */
  847. .icache_bsize = 32,
  848. .dcache_bsize = 32,
  849. },
  850. {
  851. .pvr_mask = 0xf0000fff,
  852. .pvr_value = 0x400008d3,
  853. .cpu_name = "440EP Rev. B",
  854. .cpu_features = CPU_FTRS_44X,
  855. .cpu_user_features = COMMON_USER, /* 440EP has an FPU */
  856. .icache_bsize = 32,
  857. .dcache_bsize = 32,
  858. },
  859. { /* 440GP Rev. B */
  860. .pvr_mask = 0xf0000fff,
  861. .pvr_value = 0x40000440,
  862. .cpu_name = "440GP Rev. B",
  863. .cpu_features = CPU_FTRS_44X,
  864. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  865. .icache_bsize = 32,
  866. .dcache_bsize = 32,
  867. },
  868. { /* 440GP Rev. C */
  869. .pvr_mask = 0xf0000fff,
  870. .pvr_value = 0x40000481,
  871. .cpu_name = "440GP Rev. C",
  872. .cpu_features = CPU_FTRS_44X,
  873. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  874. .icache_bsize = 32,
  875. .dcache_bsize = 32,
  876. },
  877. { /* 440GX Rev. A */
  878. .pvr_mask = 0xf0000fff,
  879. .pvr_value = 0x50000850,
  880. .cpu_name = "440GX Rev. A",
  881. .cpu_features = CPU_FTRS_44X,
  882. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  883. .icache_bsize = 32,
  884. .dcache_bsize = 32,
  885. },
  886. { /* 440GX Rev. B */
  887. .pvr_mask = 0xf0000fff,
  888. .pvr_value = 0x50000851,
  889. .cpu_name = "440GX Rev. B",
  890. .cpu_features = CPU_FTRS_44X,
  891. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  892. .icache_bsize = 32,
  893. .dcache_bsize = 32,
  894. },
  895. { /* 440GX Rev. C */
  896. .pvr_mask = 0xf0000fff,
  897. .pvr_value = 0x50000892,
  898. .cpu_name = "440GX Rev. C",
  899. .cpu_features = CPU_FTRS_44X,
  900. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  901. .icache_bsize = 32,
  902. .dcache_bsize = 32,
  903. },
  904. { /* 440GX Rev. F */
  905. .pvr_mask = 0xf0000fff,
  906. .pvr_value = 0x50000894,
  907. .cpu_name = "440GX Rev. F",
  908. .cpu_features = CPU_FTRS_44X,
  909. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  910. .icache_bsize = 32,
  911. .dcache_bsize = 32,
  912. },
  913. { /* 440SP Rev. A */
  914. .pvr_mask = 0xff000fff,
  915. .pvr_value = 0x53000891,
  916. .cpu_name = "440SP Rev. A",
  917. .cpu_features = CPU_FTRS_44X,
  918. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  919. .icache_bsize = 32,
  920. .dcache_bsize = 32,
  921. },
  922. { /* 440SPe Rev. A */
  923. .pvr_mask = 0xff000fff,
  924. .pvr_value = 0x53000890,
  925. .cpu_name = "440SPe Rev. A",
  926. .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
  927. CPU_FTR_USE_TB,
  928. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  929. .icache_bsize = 32,
  930. .dcache_bsize = 32,
  931. },
  932. #endif /* CONFIG_44x */
  933. #ifdef CONFIG_FSL_BOOKE
  934. { /* e200z5 */
  935. .pvr_mask = 0xfff00000,
  936. .pvr_value = 0x81000000,
  937. .cpu_name = "e200z5",
  938. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  939. .cpu_features = CPU_FTRS_E200,
  940. .cpu_user_features = PPC_FEATURE_32 |
  941. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE |
  942. PPC_FEATURE_UNIFIED_CACHE,
  943. .dcache_bsize = 32,
  944. },
  945. { /* e200z6 */
  946. .pvr_mask = 0xfff00000,
  947. .pvr_value = 0x81100000,
  948. .cpu_name = "e200z6",
  949. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  950. .cpu_features = CPU_FTRS_E200,
  951. .cpu_user_features = PPC_FEATURE_32 |
  952. PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
  953. PPC_FEATURE_HAS_EFP_SINGLE |
  954. PPC_FEATURE_UNIFIED_CACHE,
  955. .dcache_bsize = 32,
  956. },
  957. { /* e500 */
  958. .pvr_mask = 0xffff0000,
  959. .pvr_value = 0x80200000,
  960. .cpu_name = "e500",
  961. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  962. .cpu_features = CPU_FTRS_E500,
  963. .cpu_user_features = PPC_FEATURE_32 |
  964. PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
  965. PPC_FEATURE_HAS_EFP_SINGLE,
  966. .icache_bsize = 32,
  967. .dcache_bsize = 32,
  968. .num_pmcs = 4,
  969. .oprofile_cpu_type = "ppc/e500",
  970. .oprofile_type = BOOKE,
  971. },
  972. { /* e500v2 */
  973. .pvr_mask = 0xffff0000,
  974. .pvr_value = 0x80210000,
  975. .cpu_name = "e500v2",
  976. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  977. .cpu_features = CPU_FTRS_E500_2,
  978. .cpu_user_features = PPC_FEATURE_32 |
  979. PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
  980. PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
  981. .icache_bsize = 32,
  982. .dcache_bsize = 32,
  983. .num_pmcs = 4,
  984. .oprofile_cpu_type = "ppc/e500",
  985. .oprofile_type = BOOKE,
  986. },
  987. #endif
  988. #if !CLASSIC_PPC
  989. { /* default match */
  990. .pvr_mask = 0x00000000,
  991. .pvr_value = 0x00000000,
  992. .cpu_name = "(generic PPC)",
  993. .cpu_features = CPU_FTRS_GENERIC_32,
  994. .cpu_user_features = PPC_FEATURE_32,
  995. .icache_bsize = 32,
  996. .dcache_bsize = 32,
  997. }
  998. #endif /* !CLASSIC_PPC */
  999. #endif /* CONFIG_PPC32 */
  1000. };