patch_hdmi.c 77 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792
  1. /*
  2. *
  3. * patch_hdmi.c - routines for HDMI/DisplayPort codecs
  4. *
  5. * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
  6. * Copyright (c) 2006 ATI Technologies Inc.
  7. * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
  8. * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
  9. *
  10. * Authors:
  11. * Wu Fengguang <wfg@linux.intel.com>
  12. *
  13. * Maintained by:
  14. * Wu Fengguang <wfg@linux.intel.com>
  15. *
  16. * This program is free software; you can redistribute it and/or modify it
  17. * under the terms of the GNU General Public License as published by the Free
  18. * Software Foundation; either version 2 of the License, or (at your option)
  19. * any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful, but
  22. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  23. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  24. * for more details.
  25. *
  26. * You should have received a copy of the GNU General Public License
  27. * along with this program; if not, write to the Free Software Foundation,
  28. * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  29. */
  30. #include <linux/init.h>
  31. #include <linux/delay.h>
  32. #include <linux/slab.h>
  33. #include <linux/module.h>
  34. #include <sound/core.h>
  35. #include <sound/jack.h>
  36. #include <sound/asoundef.h>
  37. #include <sound/tlv.h>
  38. #include "hda_codec.h"
  39. #include "hda_local.h"
  40. #include "hda_jack.h"
  41. static bool static_hdmi_pcm;
  42. module_param(static_hdmi_pcm, bool, 0644);
  43. MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
  44. #define is_haswell(codec) ((codec)->vendor_id == 0x80862807)
  45. struct hdmi_spec_per_cvt {
  46. hda_nid_t cvt_nid;
  47. int assigned;
  48. unsigned int channels_min;
  49. unsigned int channels_max;
  50. u32 rates;
  51. u64 formats;
  52. unsigned int maxbps;
  53. };
  54. /* max. connections to a widget */
  55. #define HDA_MAX_CONNECTIONS 32
  56. struct hdmi_spec_per_pin {
  57. hda_nid_t pin_nid;
  58. int num_mux_nids;
  59. hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
  60. hda_nid_t cvt_nid;
  61. struct hda_codec *codec;
  62. struct hdmi_eld sink_eld;
  63. struct delayed_work work;
  64. struct snd_kcontrol *eld_ctl;
  65. int repoll_count;
  66. bool setup; /* the stream has been set up by prepare callback */
  67. int channels; /* current number of channels */
  68. bool non_pcm;
  69. bool chmap_set; /* channel-map override by ALSA API? */
  70. unsigned char chmap[8]; /* ALSA API channel-map */
  71. char pcm_name[8]; /* filled in build_pcm callbacks */
  72. };
  73. struct hdmi_spec {
  74. int num_cvts;
  75. struct snd_array cvts; /* struct hdmi_spec_per_cvt */
  76. hda_nid_t cvt_nids[4]; /* only for haswell fix */
  77. int num_pins;
  78. struct snd_array pins; /* struct hdmi_spec_per_pin */
  79. struct snd_array pcm_rec; /* struct hda_pcm */
  80. unsigned int channels_max; /* max over all cvts */
  81. struct hdmi_eld temp_eld;
  82. /*
  83. * Non-generic ATI/NVIDIA specific
  84. */
  85. struct hda_multi_out multiout;
  86. struct hda_pcm_stream pcm_playback;
  87. };
  88. struct hdmi_audio_infoframe {
  89. u8 type; /* 0x84 */
  90. u8 ver; /* 0x01 */
  91. u8 len; /* 0x0a */
  92. u8 checksum;
  93. u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
  94. u8 SS01_SF24;
  95. u8 CXT04;
  96. u8 CA;
  97. u8 LFEPBL01_LSV36_DM_INH7;
  98. };
  99. struct dp_audio_infoframe {
  100. u8 type; /* 0x84 */
  101. u8 len; /* 0x1b */
  102. u8 ver; /* 0x11 << 2 */
  103. u8 CC02_CT47; /* match with HDMI infoframe from this on */
  104. u8 SS01_SF24;
  105. u8 CXT04;
  106. u8 CA;
  107. u8 LFEPBL01_LSV36_DM_INH7;
  108. };
  109. union audio_infoframe {
  110. struct hdmi_audio_infoframe hdmi;
  111. struct dp_audio_infoframe dp;
  112. u8 bytes[0];
  113. };
  114. /*
  115. * CEA speaker placement:
  116. *
  117. * FLH FCH FRH
  118. * FLW FL FLC FC FRC FR FRW
  119. *
  120. * LFE
  121. * TC
  122. *
  123. * RL RLC RC RRC RR
  124. *
  125. * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
  126. * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
  127. */
  128. enum cea_speaker_placement {
  129. FL = (1 << 0), /* Front Left */
  130. FC = (1 << 1), /* Front Center */
  131. FR = (1 << 2), /* Front Right */
  132. FLC = (1 << 3), /* Front Left Center */
  133. FRC = (1 << 4), /* Front Right Center */
  134. RL = (1 << 5), /* Rear Left */
  135. RC = (1 << 6), /* Rear Center */
  136. RR = (1 << 7), /* Rear Right */
  137. RLC = (1 << 8), /* Rear Left Center */
  138. RRC = (1 << 9), /* Rear Right Center */
  139. LFE = (1 << 10), /* Low Frequency Effect */
  140. FLW = (1 << 11), /* Front Left Wide */
  141. FRW = (1 << 12), /* Front Right Wide */
  142. FLH = (1 << 13), /* Front Left High */
  143. FCH = (1 << 14), /* Front Center High */
  144. FRH = (1 << 15), /* Front Right High */
  145. TC = (1 << 16), /* Top Center */
  146. };
  147. /*
  148. * ELD SA bits in the CEA Speaker Allocation data block
  149. */
  150. static int eld_speaker_allocation_bits[] = {
  151. [0] = FL | FR,
  152. [1] = LFE,
  153. [2] = FC,
  154. [3] = RL | RR,
  155. [4] = RC,
  156. [5] = FLC | FRC,
  157. [6] = RLC | RRC,
  158. /* the following are not defined in ELD yet */
  159. [7] = FLW | FRW,
  160. [8] = FLH | FRH,
  161. [9] = TC,
  162. [10] = FCH,
  163. };
  164. struct cea_channel_speaker_allocation {
  165. int ca_index;
  166. int speakers[8];
  167. /* derived values, just for convenience */
  168. int channels;
  169. int spk_mask;
  170. };
  171. /*
  172. * ALSA sequence is:
  173. *
  174. * surround40 surround41 surround50 surround51 surround71
  175. * ch0 front left = = = =
  176. * ch1 front right = = = =
  177. * ch2 rear left = = = =
  178. * ch3 rear right = = = =
  179. * ch4 LFE center center center
  180. * ch5 LFE LFE
  181. * ch6 side left
  182. * ch7 side right
  183. *
  184. * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
  185. */
  186. static int hdmi_channel_mapping[0x32][8] = {
  187. /* stereo */
  188. [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
  189. /* 2.1 */
  190. [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
  191. /* Dolby Surround */
  192. [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
  193. /* surround40 */
  194. [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
  195. /* 4ch */
  196. [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
  197. /* surround41 */
  198. [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
  199. /* surround50 */
  200. [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
  201. /* surround51 */
  202. [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
  203. /* 7.1 */
  204. [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
  205. };
  206. /*
  207. * This is an ordered list!
  208. *
  209. * The preceding ones have better chances to be selected by
  210. * hdmi_channel_allocation().
  211. */
  212. static struct cea_channel_speaker_allocation channel_allocations[] = {
  213. /* channel: 7 6 5 4 3 2 1 0 */
  214. { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
  215. /* 2.1 */
  216. { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
  217. /* Dolby Surround */
  218. { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
  219. /* surround40 */
  220. { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
  221. /* surround41 */
  222. { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
  223. /* surround50 */
  224. { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
  225. /* surround51 */
  226. { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
  227. /* 6.1 */
  228. { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
  229. /* surround71 */
  230. { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
  231. { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
  232. { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
  233. { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
  234. { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
  235. { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
  236. { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
  237. { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
  238. { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
  239. { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
  240. { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
  241. { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
  242. { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
  243. { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
  244. { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
  245. { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
  246. { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
  247. { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
  248. { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
  249. { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
  250. { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
  251. { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
  252. { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
  253. { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
  254. { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
  255. { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
  256. { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
  257. { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
  258. { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
  259. { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
  260. { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
  261. { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
  262. { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
  263. { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
  264. { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
  265. { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
  266. { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
  267. { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
  268. { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
  269. { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
  270. { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
  271. { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
  272. };
  273. /*
  274. * HDMI routines
  275. */
  276. #define get_pin(spec, idx) \
  277. ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
  278. #define get_cvt(spec, idx) \
  279. ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
  280. #define get_pcm_rec(spec, idx) \
  281. ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
  282. static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
  283. {
  284. int pin_idx;
  285. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
  286. if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
  287. return pin_idx;
  288. snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
  289. return -EINVAL;
  290. }
  291. static int hinfo_to_pin_index(struct hdmi_spec *spec,
  292. struct hda_pcm_stream *hinfo)
  293. {
  294. int pin_idx;
  295. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
  296. if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
  297. return pin_idx;
  298. snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
  299. return -EINVAL;
  300. }
  301. static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
  302. {
  303. int cvt_idx;
  304. for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
  305. if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
  306. return cvt_idx;
  307. snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
  308. return -EINVAL;
  309. }
  310. static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
  311. struct snd_ctl_elem_info *uinfo)
  312. {
  313. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  314. struct hdmi_spec *spec = codec->spec;
  315. struct hdmi_eld *eld;
  316. int pin_idx;
  317. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  318. pin_idx = kcontrol->private_value;
  319. eld = &get_pin(spec, pin_idx)->sink_eld;
  320. mutex_lock(&eld->lock);
  321. uinfo->count = eld->eld_valid ? eld->eld_size : 0;
  322. mutex_unlock(&eld->lock);
  323. return 0;
  324. }
  325. static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
  326. struct snd_ctl_elem_value *ucontrol)
  327. {
  328. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  329. struct hdmi_spec *spec = codec->spec;
  330. struct hdmi_eld *eld;
  331. int pin_idx;
  332. pin_idx = kcontrol->private_value;
  333. eld = &get_pin(spec, pin_idx)->sink_eld;
  334. mutex_lock(&eld->lock);
  335. if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
  336. mutex_unlock(&eld->lock);
  337. snd_BUG();
  338. return -EINVAL;
  339. }
  340. memset(ucontrol->value.bytes.data, 0,
  341. ARRAY_SIZE(ucontrol->value.bytes.data));
  342. if (eld->eld_valid)
  343. memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
  344. eld->eld_size);
  345. mutex_unlock(&eld->lock);
  346. return 0;
  347. }
  348. static struct snd_kcontrol_new eld_bytes_ctl = {
  349. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  350. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  351. .name = "ELD",
  352. .info = hdmi_eld_ctl_info,
  353. .get = hdmi_eld_ctl_get,
  354. };
  355. static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
  356. int device)
  357. {
  358. struct snd_kcontrol *kctl;
  359. struct hdmi_spec *spec = codec->spec;
  360. int err;
  361. kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
  362. if (!kctl)
  363. return -ENOMEM;
  364. kctl->private_value = pin_idx;
  365. kctl->id.device = device;
  366. err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
  367. if (err < 0)
  368. return err;
  369. get_pin(spec, pin_idx)->eld_ctl = kctl;
  370. return 0;
  371. }
  372. #ifdef BE_PARANOID
  373. static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
  374. int *packet_index, int *byte_index)
  375. {
  376. int val;
  377. val = snd_hda_codec_read(codec, pin_nid, 0,
  378. AC_VERB_GET_HDMI_DIP_INDEX, 0);
  379. *packet_index = val >> 5;
  380. *byte_index = val & 0x1f;
  381. }
  382. #endif
  383. static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
  384. int packet_index, int byte_index)
  385. {
  386. int val;
  387. val = (packet_index << 5) | (byte_index & 0x1f);
  388. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
  389. }
  390. static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
  391. unsigned char val)
  392. {
  393. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
  394. }
  395. static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
  396. {
  397. /* Unmute */
  398. if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
  399. snd_hda_codec_write(codec, pin_nid, 0,
  400. AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
  401. /* Enable pin out: some machines with GM965 gets broken output when
  402. * the pin is disabled or changed while using with HDMI
  403. */
  404. snd_hda_codec_write(codec, pin_nid, 0,
  405. AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
  406. }
  407. static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
  408. {
  409. return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
  410. AC_VERB_GET_CVT_CHAN_COUNT, 0);
  411. }
  412. static void hdmi_set_channel_count(struct hda_codec *codec,
  413. hda_nid_t cvt_nid, int chs)
  414. {
  415. if (chs != hdmi_get_channel_count(codec, cvt_nid))
  416. snd_hda_codec_write(codec, cvt_nid, 0,
  417. AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
  418. }
  419. /*
  420. * Channel mapping routines
  421. */
  422. /*
  423. * Compute derived values in channel_allocations[].
  424. */
  425. static void init_channel_allocations(void)
  426. {
  427. int i, j;
  428. struct cea_channel_speaker_allocation *p;
  429. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  430. p = channel_allocations + i;
  431. p->channels = 0;
  432. p->spk_mask = 0;
  433. for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
  434. if (p->speakers[j]) {
  435. p->channels++;
  436. p->spk_mask |= p->speakers[j];
  437. }
  438. }
  439. }
  440. static int get_channel_allocation_order(int ca)
  441. {
  442. int i;
  443. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  444. if (channel_allocations[i].ca_index == ca)
  445. break;
  446. }
  447. return i;
  448. }
  449. /*
  450. * The transformation takes two steps:
  451. *
  452. * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
  453. * spk_mask => (channel_allocations[]) => ai->CA
  454. *
  455. * TODO: it could select the wrong CA from multiple candidates.
  456. */
  457. static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
  458. {
  459. int i;
  460. int ca = 0;
  461. int spk_mask = 0;
  462. char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
  463. /*
  464. * CA defaults to 0 for basic stereo audio
  465. */
  466. if (channels <= 2)
  467. return 0;
  468. /*
  469. * expand ELD's speaker allocation mask
  470. *
  471. * ELD tells the speaker mask in a compact(paired) form,
  472. * expand ELD's notions to match the ones used by Audio InfoFrame.
  473. */
  474. for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
  475. if (eld->info.spk_alloc & (1 << i))
  476. spk_mask |= eld_speaker_allocation_bits[i];
  477. }
  478. /* search for the first working match in the CA table */
  479. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  480. if (channels == channel_allocations[i].channels &&
  481. (spk_mask & channel_allocations[i].spk_mask) ==
  482. channel_allocations[i].spk_mask) {
  483. ca = channel_allocations[i].ca_index;
  484. break;
  485. }
  486. }
  487. if (!ca) {
  488. /* if there was no match, select the regular ALSA channel
  489. * allocation with the matching number of channels */
  490. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  491. if (channels == channel_allocations[i].channels) {
  492. ca = channel_allocations[i].ca_index;
  493. break;
  494. }
  495. }
  496. }
  497. snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
  498. snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
  499. ca, channels, buf);
  500. return ca;
  501. }
  502. static void hdmi_debug_channel_mapping(struct hda_codec *codec,
  503. hda_nid_t pin_nid)
  504. {
  505. #ifdef CONFIG_SND_DEBUG_VERBOSE
  506. int i;
  507. int slot;
  508. for (i = 0; i < 8; i++) {
  509. slot = snd_hda_codec_read(codec, pin_nid, 0,
  510. AC_VERB_GET_HDMI_CHAN_SLOT, i);
  511. printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
  512. slot >> 4, slot & 0xf);
  513. }
  514. #endif
  515. }
  516. static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
  517. hda_nid_t pin_nid,
  518. bool non_pcm,
  519. int ca)
  520. {
  521. struct cea_channel_speaker_allocation *ch_alloc;
  522. int i;
  523. int err;
  524. int order;
  525. int non_pcm_mapping[8];
  526. order = get_channel_allocation_order(ca);
  527. ch_alloc = &channel_allocations[order];
  528. if (hdmi_channel_mapping[ca][1] == 0) {
  529. int hdmi_slot = 0;
  530. /* fill actual channel mappings in ALSA channel (i) order */
  531. for (i = 0; i < ch_alloc->channels; i++) {
  532. while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
  533. hdmi_slot++; /* skip zero slots */
  534. hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
  535. }
  536. /* fill the rest of the slots with ALSA channel 0xf */
  537. for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
  538. if (!ch_alloc->speakers[7 - hdmi_slot])
  539. hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
  540. }
  541. if (non_pcm) {
  542. for (i = 0; i < ch_alloc->channels; i++)
  543. non_pcm_mapping[i] = (i << 4) | i;
  544. for (; i < 8; i++)
  545. non_pcm_mapping[i] = (0xf << 4) | i;
  546. }
  547. for (i = 0; i < 8; i++) {
  548. err = snd_hda_codec_write(codec, pin_nid, 0,
  549. AC_VERB_SET_HDMI_CHAN_SLOT,
  550. non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i]);
  551. if (err) {
  552. snd_printdd(KERN_NOTICE
  553. "HDMI: channel mapping failed\n");
  554. break;
  555. }
  556. }
  557. }
  558. struct channel_map_table {
  559. unsigned char map; /* ALSA API channel map position */
  560. int spk_mask; /* speaker position bit mask */
  561. };
  562. static struct channel_map_table map_tables[] = {
  563. { SNDRV_CHMAP_FL, FL },
  564. { SNDRV_CHMAP_FR, FR },
  565. { SNDRV_CHMAP_RL, RL },
  566. { SNDRV_CHMAP_RR, RR },
  567. { SNDRV_CHMAP_LFE, LFE },
  568. { SNDRV_CHMAP_FC, FC },
  569. { SNDRV_CHMAP_RLC, RLC },
  570. { SNDRV_CHMAP_RRC, RRC },
  571. { SNDRV_CHMAP_RC, RC },
  572. { SNDRV_CHMAP_FLC, FLC },
  573. { SNDRV_CHMAP_FRC, FRC },
  574. { SNDRV_CHMAP_FLH, FLH },
  575. { SNDRV_CHMAP_FRH, FRH },
  576. { SNDRV_CHMAP_FLW, FLW },
  577. { SNDRV_CHMAP_FRW, FRW },
  578. { SNDRV_CHMAP_TC, TC },
  579. { SNDRV_CHMAP_FCH, FCH },
  580. {} /* terminator */
  581. };
  582. /* from ALSA API channel position to speaker bit mask */
  583. static int to_spk_mask(unsigned char c)
  584. {
  585. struct channel_map_table *t = map_tables;
  586. for (; t->map; t++) {
  587. if (t->map == c)
  588. return t->spk_mask;
  589. }
  590. return 0;
  591. }
  592. /* from ALSA API channel position to CEA slot */
  593. static int to_cea_slot(int ordered_ca, unsigned char pos)
  594. {
  595. int mask = to_spk_mask(pos);
  596. int i;
  597. if (mask) {
  598. for (i = 0; i < 8; i++) {
  599. if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
  600. return i;
  601. }
  602. }
  603. return -1;
  604. }
  605. /* from speaker bit mask to ALSA API channel position */
  606. static int spk_to_chmap(int spk)
  607. {
  608. struct channel_map_table *t = map_tables;
  609. for (; t->map; t++) {
  610. if (t->spk_mask == spk)
  611. return t->map;
  612. }
  613. return 0;
  614. }
  615. /* from CEA slot to ALSA API channel position */
  616. static int from_cea_slot(int ordered_ca, unsigned char slot)
  617. {
  618. int mask = channel_allocations[ordered_ca].speakers[7 - slot];
  619. return spk_to_chmap(mask);
  620. }
  621. /* get the CA index corresponding to the given ALSA API channel map */
  622. static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
  623. {
  624. int i, spks = 0, spk_mask = 0;
  625. for (i = 0; i < chs; i++) {
  626. int mask = to_spk_mask(map[i]);
  627. if (mask) {
  628. spk_mask |= mask;
  629. spks++;
  630. }
  631. }
  632. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  633. if ((chs == channel_allocations[i].channels ||
  634. spks == channel_allocations[i].channels) &&
  635. (spk_mask & channel_allocations[i].spk_mask) ==
  636. channel_allocations[i].spk_mask)
  637. return channel_allocations[i].ca_index;
  638. }
  639. return -1;
  640. }
  641. /* set up the channel slots for the given ALSA API channel map */
  642. static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
  643. hda_nid_t pin_nid,
  644. int chs, unsigned char *map,
  645. int ca)
  646. {
  647. int ordered_ca = get_channel_allocation_order(ca);
  648. int alsa_pos, hdmi_slot;
  649. int assignments[8] = {[0 ... 7] = 0xf};
  650. for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
  651. hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
  652. if (hdmi_slot < 0)
  653. continue; /* unassigned channel */
  654. assignments[hdmi_slot] = alsa_pos;
  655. }
  656. for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
  657. int val, err;
  658. val = (assignments[hdmi_slot] << 4) | hdmi_slot;
  659. err = snd_hda_codec_write(codec, pin_nid, 0,
  660. AC_VERB_SET_HDMI_CHAN_SLOT, val);
  661. if (err)
  662. return -EINVAL;
  663. }
  664. return 0;
  665. }
  666. /* store ALSA API channel map from the current default map */
  667. static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
  668. {
  669. int i;
  670. int ordered_ca = get_channel_allocation_order(ca);
  671. for (i = 0; i < 8; i++) {
  672. if (i < channel_allocations[ordered_ca].channels)
  673. map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
  674. else
  675. map[i] = 0;
  676. }
  677. }
  678. static void hdmi_setup_channel_mapping(struct hda_codec *codec,
  679. hda_nid_t pin_nid, bool non_pcm, int ca,
  680. int channels, unsigned char *map,
  681. bool chmap_set)
  682. {
  683. if (!non_pcm && chmap_set) {
  684. hdmi_manual_setup_channel_mapping(codec, pin_nid,
  685. channels, map, ca);
  686. } else {
  687. hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
  688. hdmi_setup_fake_chmap(map, ca);
  689. }
  690. hdmi_debug_channel_mapping(codec, pin_nid);
  691. }
  692. /*
  693. * Audio InfoFrame routines
  694. */
  695. /*
  696. * Enable Audio InfoFrame Transmission
  697. */
  698. static void hdmi_start_infoframe_trans(struct hda_codec *codec,
  699. hda_nid_t pin_nid)
  700. {
  701. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  702. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
  703. AC_DIPXMIT_BEST);
  704. }
  705. /*
  706. * Disable Audio InfoFrame Transmission
  707. */
  708. static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
  709. hda_nid_t pin_nid)
  710. {
  711. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  712. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
  713. AC_DIPXMIT_DISABLE);
  714. }
  715. static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
  716. {
  717. #ifdef CONFIG_SND_DEBUG_VERBOSE
  718. int i;
  719. int size;
  720. size = snd_hdmi_get_eld_size(codec, pin_nid);
  721. printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
  722. for (i = 0; i < 8; i++) {
  723. size = snd_hda_codec_read(codec, pin_nid, 0,
  724. AC_VERB_GET_HDMI_DIP_SIZE, i);
  725. printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
  726. }
  727. #endif
  728. }
  729. static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
  730. {
  731. #ifdef BE_PARANOID
  732. int i, j;
  733. int size;
  734. int pi, bi;
  735. for (i = 0; i < 8; i++) {
  736. size = snd_hda_codec_read(codec, pin_nid, 0,
  737. AC_VERB_GET_HDMI_DIP_SIZE, i);
  738. if (size == 0)
  739. continue;
  740. hdmi_set_dip_index(codec, pin_nid, i, 0x0);
  741. for (j = 1; j < 1000; j++) {
  742. hdmi_write_dip_byte(codec, pin_nid, 0x0);
  743. hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
  744. if (pi != i)
  745. snd_printd(KERN_INFO "dip index %d: %d != %d\n",
  746. bi, pi, i);
  747. if (bi == 0) /* byte index wrapped around */
  748. break;
  749. }
  750. snd_printd(KERN_INFO
  751. "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
  752. i, size, j);
  753. }
  754. #endif
  755. }
  756. static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
  757. {
  758. u8 *bytes = (u8 *)hdmi_ai;
  759. u8 sum = 0;
  760. int i;
  761. hdmi_ai->checksum = 0;
  762. for (i = 0; i < sizeof(*hdmi_ai); i++)
  763. sum += bytes[i];
  764. hdmi_ai->checksum = -sum;
  765. }
  766. static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
  767. hda_nid_t pin_nid,
  768. u8 *dip, int size)
  769. {
  770. int i;
  771. hdmi_debug_dip_size(codec, pin_nid);
  772. hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
  773. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  774. for (i = 0; i < size; i++)
  775. hdmi_write_dip_byte(codec, pin_nid, dip[i]);
  776. }
  777. static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
  778. u8 *dip, int size)
  779. {
  780. u8 val;
  781. int i;
  782. if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
  783. != AC_DIPXMIT_BEST)
  784. return false;
  785. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  786. for (i = 0; i < size; i++) {
  787. val = snd_hda_codec_read(codec, pin_nid, 0,
  788. AC_VERB_GET_HDMI_DIP_DATA, 0);
  789. if (val != dip[i])
  790. return false;
  791. }
  792. return true;
  793. }
  794. static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
  795. struct hdmi_spec_per_pin *per_pin,
  796. bool non_pcm)
  797. {
  798. hda_nid_t pin_nid = per_pin->pin_nid;
  799. int channels = per_pin->channels;
  800. int active_channels;
  801. struct hdmi_eld *eld;
  802. int ca, ordered_ca;
  803. union audio_infoframe ai;
  804. if (!channels)
  805. return;
  806. if (is_haswell(codec))
  807. snd_hda_codec_write(codec, pin_nid, 0,
  808. AC_VERB_SET_AMP_GAIN_MUTE,
  809. AMP_OUT_UNMUTE);
  810. eld = &per_pin->sink_eld;
  811. if (!eld->monitor_present)
  812. return;
  813. if (!non_pcm && per_pin->chmap_set)
  814. ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
  815. else
  816. ca = hdmi_channel_allocation(eld, channels);
  817. if (ca < 0)
  818. ca = 0;
  819. ordered_ca = get_channel_allocation_order(ca);
  820. active_channels = channel_allocations[ordered_ca].channels;
  821. hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
  822. memset(&ai, 0, sizeof(ai));
  823. if (eld->info.conn_type == 0) { /* HDMI */
  824. struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
  825. hdmi_ai->type = 0x84;
  826. hdmi_ai->ver = 0x01;
  827. hdmi_ai->len = 0x0a;
  828. hdmi_ai->CC02_CT47 = active_channels - 1;
  829. hdmi_ai->CA = ca;
  830. hdmi_checksum_audio_infoframe(hdmi_ai);
  831. } else if (eld->info.conn_type == 1) { /* DisplayPort */
  832. struct dp_audio_infoframe *dp_ai = &ai.dp;
  833. dp_ai->type = 0x84;
  834. dp_ai->len = 0x1b;
  835. dp_ai->ver = 0x11 << 2;
  836. dp_ai->CC02_CT47 = active_channels - 1;
  837. dp_ai->CA = ca;
  838. } else {
  839. snd_printd("HDMI: unknown connection type at pin %d\n",
  840. pin_nid);
  841. return;
  842. }
  843. /*
  844. * always configure channel mapping, it may have been changed by the
  845. * user in the meantime
  846. */
  847. hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
  848. channels, per_pin->chmap,
  849. per_pin->chmap_set);
  850. /*
  851. * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
  852. * sizeof(*dp_ai) to avoid partial match/update problems when
  853. * the user switches between HDMI/DP monitors.
  854. */
  855. if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
  856. sizeof(ai))) {
  857. snd_printdd("hdmi_setup_audio_infoframe: "
  858. "pin=%d channels=%d ca=0x%02x\n",
  859. pin_nid,
  860. active_channels, ca);
  861. hdmi_stop_infoframe_trans(codec, pin_nid);
  862. hdmi_fill_audio_infoframe(codec, pin_nid,
  863. ai.bytes, sizeof(ai));
  864. hdmi_start_infoframe_trans(codec, pin_nid);
  865. }
  866. per_pin->non_pcm = non_pcm;
  867. }
  868. /*
  869. * Unsolicited events
  870. */
  871. static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
  872. static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
  873. {
  874. struct hdmi_spec *spec = codec->spec;
  875. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  876. int pin_nid;
  877. int pin_idx;
  878. struct hda_jack_tbl *jack;
  879. int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
  880. jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
  881. if (!jack)
  882. return;
  883. pin_nid = jack->nid;
  884. jack->jack_dirty = 1;
  885. _snd_printd(SND_PR_VERBOSE,
  886. "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
  887. codec->addr, pin_nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
  888. !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
  889. pin_idx = pin_nid_to_pin_index(spec, pin_nid);
  890. if (pin_idx < 0)
  891. return;
  892. hdmi_present_sense(get_pin(spec, pin_idx), 1);
  893. snd_hda_jack_report_sync(codec);
  894. }
  895. static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
  896. {
  897. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  898. int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
  899. int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
  900. int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
  901. printk(KERN_INFO
  902. "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
  903. codec->addr,
  904. tag,
  905. subtag,
  906. cp_state,
  907. cp_ready);
  908. /* TODO */
  909. if (cp_state)
  910. ;
  911. if (cp_ready)
  912. ;
  913. }
  914. static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
  915. {
  916. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  917. int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
  918. if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
  919. snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
  920. return;
  921. }
  922. if (subtag == 0)
  923. hdmi_intrinsic_event(codec, res);
  924. else
  925. hdmi_non_intrinsic_event(codec, res);
  926. }
  927. static void haswell_verify_D0(struct hda_codec *codec,
  928. hda_nid_t cvt_nid, hda_nid_t nid)
  929. {
  930. int pwr;
  931. /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
  932. * thus pins could only choose converter 0 for use. Make sure the
  933. * converters are in correct power state */
  934. if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
  935. snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
  936. if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
  937. snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
  938. AC_PWRST_D0);
  939. msleep(40);
  940. pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
  941. pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
  942. snd_printd("Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
  943. }
  944. }
  945. /*
  946. * Callbacks
  947. */
  948. /* HBR should be Non-PCM, 8 channels */
  949. #define is_hbr_format(format) \
  950. ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
  951. static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
  952. hda_nid_t pin_nid, u32 stream_tag, int format)
  953. {
  954. int pinctl;
  955. int new_pinctl = 0;
  956. if (is_haswell(codec))
  957. haswell_verify_D0(codec, cvt_nid, pin_nid);
  958. if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
  959. pinctl = snd_hda_codec_read(codec, pin_nid, 0,
  960. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  961. new_pinctl = pinctl & ~AC_PINCTL_EPT;
  962. if (is_hbr_format(format))
  963. new_pinctl |= AC_PINCTL_EPT_HBR;
  964. else
  965. new_pinctl |= AC_PINCTL_EPT_NATIVE;
  966. snd_printdd("hdmi_setup_stream: "
  967. "NID=0x%x, %spinctl=0x%x\n",
  968. pin_nid,
  969. pinctl == new_pinctl ? "" : "new-",
  970. new_pinctl);
  971. if (pinctl != new_pinctl)
  972. snd_hda_codec_write(codec, pin_nid, 0,
  973. AC_VERB_SET_PIN_WIDGET_CONTROL,
  974. new_pinctl);
  975. }
  976. if (is_hbr_format(format) && !new_pinctl) {
  977. snd_printdd("hdmi_setup_stream: HBR is not supported\n");
  978. return -EINVAL;
  979. }
  980. snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
  981. return 0;
  982. }
  983. static int hdmi_choose_cvt(struct hda_codec *codec,
  984. int pin_idx, int *cvt_id, int *mux_id)
  985. {
  986. struct hdmi_spec *spec = codec->spec;
  987. struct hdmi_spec_per_pin *per_pin;
  988. struct hdmi_spec_per_cvt *per_cvt = NULL;
  989. int cvt_idx, mux_idx = 0;
  990. per_pin = get_pin(spec, pin_idx);
  991. /* Dynamically assign converter to stream */
  992. for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
  993. per_cvt = get_cvt(spec, cvt_idx);
  994. /* Must not already be assigned */
  995. if (per_cvt->assigned)
  996. continue;
  997. /* Must be in pin's mux's list of converters */
  998. for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
  999. if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
  1000. break;
  1001. /* Not in mux list */
  1002. if (mux_idx == per_pin->num_mux_nids)
  1003. continue;
  1004. break;
  1005. }
  1006. /* No free converters */
  1007. if (cvt_idx == spec->num_cvts)
  1008. return -ENODEV;
  1009. if (cvt_id)
  1010. *cvt_id = cvt_idx;
  1011. if (mux_id)
  1012. *mux_id = mux_idx;
  1013. return 0;
  1014. }
  1015. static void haswell_config_cvts(struct hda_codec *codec,
  1016. hda_nid_t pin_nid, int mux_idx)
  1017. {
  1018. struct hdmi_spec *spec = codec->spec;
  1019. hda_nid_t nid, end_nid;
  1020. int cvt_idx, curr;
  1021. struct hdmi_spec_per_cvt *per_cvt;
  1022. /* configure all pins, including "no physical connection" ones */
  1023. end_nid = codec->start_nid + codec->num_nodes;
  1024. for (nid = codec->start_nid; nid < end_nid; nid++) {
  1025. unsigned int wid_caps = get_wcaps(codec, nid);
  1026. unsigned int wid_type = get_wcaps_type(wid_caps);
  1027. if (wid_type != AC_WID_PIN)
  1028. continue;
  1029. if (nid == pin_nid)
  1030. continue;
  1031. curr = snd_hda_codec_read(codec, nid, 0,
  1032. AC_VERB_GET_CONNECT_SEL, 0);
  1033. if (curr != mux_idx)
  1034. continue;
  1035. /* choose an unassigned converter. The conveters in the
  1036. * connection list are in the same order as in the codec.
  1037. */
  1038. for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
  1039. per_cvt = get_cvt(spec, cvt_idx);
  1040. if (!per_cvt->assigned) {
  1041. snd_printdd("choose cvt %d for pin nid %d\n",
  1042. cvt_idx, nid);
  1043. snd_hda_codec_write_cache(codec, nid, 0,
  1044. AC_VERB_SET_CONNECT_SEL,
  1045. cvt_idx);
  1046. break;
  1047. }
  1048. }
  1049. }
  1050. }
  1051. /*
  1052. * HDA PCM callbacks
  1053. */
  1054. static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
  1055. struct hda_codec *codec,
  1056. struct snd_pcm_substream *substream)
  1057. {
  1058. struct hdmi_spec *spec = codec->spec;
  1059. struct snd_pcm_runtime *runtime = substream->runtime;
  1060. int pin_idx, cvt_idx, mux_idx = 0;
  1061. struct hdmi_spec_per_pin *per_pin;
  1062. struct hdmi_eld *eld;
  1063. struct hdmi_spec_per_cvt *per_cvt = NULL;
  1064. int err;
  1065. /* Validate hinfo */
  1066. pin_idx = hinfo_to_pin_index(spec, hinfo);
  1067. if (snd_BUG_ON(pin_idx < 0))
  1068. return -EINVAL;
  1069. per_pin = get_pin(spec, pin_idx);
  1070. eld = &per_pin->sink_eld;
  1071. err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
  1072. if (err < 0)
  1073. return err;
  1074. per_cvt = get_cvt(spec, cvt_idx);
  1075. /* Claim converter */
  1076. per_cvt->assigned = 1;
  1077. per_pin->cvt_nid = per_cvt->cvt_nid;
  1078. hinfo->nid = per_cvt->cvt_nid;
  1079. snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
  1080. AC_VERB_SET_CONNECT_SEL,
  1081. mux_idx);
  1082. /* configure unused pins to choose other converters */
  1083. if (is_haswell(codec))
  1084. haswell_config_cvts(codec, per_pin->pin_nid, mux_idx);
  1085. snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
  1086. /* Initially set the converter's capabilities */
  1087. hinfo->channels_min = per_cvt->channels_min;
  1088. hinfo->channels_max = per_cvt->channels_max;
  1089. hinfo->rates = per_cvt->rates;
  1090. hinfo->formats = per_cvt->formats;
  1091. hinfo->maxbps = per_cvt->maxbps;
  1092. /* Restrict capabilities by ELD if this isn't disabled */
  1093. if (!static_hdmi_pcm && eld->eld_valid) {
  1094. snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
  1095. if (hinfo->channels_min > hinfo->channels_max ||
  1096. !hinfo->rates || !hinfo->formats) {
  1097. per_cvt->assigned = 0;
  1098. hinfo->nid = 0;
  1099. snd_hda_spdif_ctls_unassign(codec, pin_idx);
  1100. return -ENODEV;
  1101. }
  1102. }
  1103. /* Store the updated parameters */
  1104. runtime->hw.channels_min = hinfo->channels_min;
  1105. runtime->hw.channels_max = hinfo->channels_max;
  1106. runtime->hw.formats = hinfo->formats;
  1107. runtime->hw.rates = hinfo->rates;
  1108. snd_pcm_hw_constraint_step(substream->runtime, 0,
  1109. SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  1110. return 0;
  1111. }
  1112. /*
  1113. * HDA/HDMI auto parsing
  1114. */
  1115. static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
  1116. {
  1117. struct hdmi_spec *spec = codec->spec;
  1118. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1119. hda_nid_t pin_nid = per_pin->pin_nid;
  1120. if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
  1121. snd_printk(KERN_WARNING
  1122. "HDMI: pin %d wcaps %#x "
  1123. "does not support connection list\n",
  1124. pin_nid, get_wcaps(codec, pin_nid));
  1125. return -EINVAL;
  1126. }
  1127. per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
  1128. per_pin->mux_nids,
  1129. HDA_MAX_CONNECTIONS);
  1130. return 0;
  1131. }
  1132. static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
  1133. {
  1134. struct hda_codec *codec = per_pin->codec;
  1135. struct hdmi_spec *spec = codec->spec;
  1136. struct hdmi_eld *eld = &spec->temp_eld;
  1137. struct hdmi_eld *pin_eld = &per_pin->sink_eld;
  1138. hda_nid_t pin_nid = per_pin->pin_nid;
  1139. /*
  1140. * Always execute a GetPinSense verb here, even when called from
  1141. * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
  1142. * response's PD bit is not the real PD value, but indicates that
  1143. * the real PD value changed. An older version of the HD-audio
  1144. * specification worked this way. Hence, we just ignore the data in
  1145. * the unsolicited response to avoid custom WARs.
  1146. */
  1147. int present = snd_hda_pin_sense(codec, pin_nid);
  1148. bool update_eld = false;
  1149. bool eld_changed = false;
  1150. mutex_lock(&pin_eld->lock);
  1151. pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
  1152. if (pin_eld->monitor_present)
  1153. eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
  1154. else
  1155. eld->eld_valid = false;
  1156. _snd_printd(SND_PR_VERBOSE,
  1157. "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
  1158. codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
  1159. if (eld->eld_valid) {
  1160. if (snd_hdmi_get_eld(codec, pin_nid, eld->eld_buffer,
  1161. &eld->eld_size) < 0)
  1162. eld->eld_valid = false;
  1163. else {
  1164. memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
  1165. if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer,
  1166. eld->eld_size) < 0)
  1167. eld->eld_valid = false;
  1168. }
  1169. if (eld->eld_valid) {
  1170. snd_hdmi_show_eld(&eld->info);
  1171. update_eld = true;
  1172. }
  1173. else if (repoll) {
  1174. queue_delayed_work(codec->bus->workq,
  1175. &per_pin->work,
  1176. msecs_to_jiffies(300));
  1177. goto unlock;
  1178. }
  1179. }
  1180. if (pin_eld->eld_valid && !eld->eld_valid) {
  1181. update_eld = true;
  1182. eld_changed = true;
  1183. }
  1184. if (update_eld) {
  1185. bool old_eld_valid = pin_eld->eld_valid;
  1186. pin_eld->eld_valid = eld->eld_valid;
  1187. eld_changed = pin_eld->eld_size != eld->eld_size ||
  1188. memcmp(pin_eld->eld_buffer, eld->eld_buffer,
  1189. eld->eld_size) != 0;
  1190. if (eld_changed)
  1191. memcpy(pin_eld->eld_buffer, eld->eld_buffer,
  1192. eld->eld_size);
  1193. pin_eld->eld_size = eld->eld_size;
  1194. pin_eld->info = eld->info;
  1195. /* Haswell-specific workaround: re-setup when the transcoder is
  1196. * changed during the stream playback
  1197. */
  1198. if (is_haswell(codec) &&
  1199. eld->eld_valid && !old_eld_valid && per_pin->setup)
  1200. hdmi_setup_audio_infoframe(codec, per_pin,
  1201. per_pin->non_pcm);
  1202. }
  1203. if (eld_changed)
  1204. snd_ctl_notify(codec->bus->card,
  1205. SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
  1206. &per_pin->eld_ctl->id);
  1207. unlock:
  1208. mutex_unlock(&pin_eld->lock);
  1209. }
  1210. static void hdmi_repoll_eld(struct work_struct *work)
  1211. {
  1212. struct hdmi_spec_per_pin *per_pin =
  1213. container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
  1214. if (per_pin->repoll_count++ > 6)
  1215. per_pin->repoll_count = 0;
  1216. hdmi_present_sense(per_pin, per_pin->repoll_count);
  1217. }
  1218. static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
  1219. hda_nid_t nid);
  1220. static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
  1221. {
  1222. struct hdmi_spec *spec = codec->spec;
  1223. unsigned int caps, config;
  1224. int pin_idx;
  1225. struct hdmi_spec_per_pin *per_pin;
  1226. int err;
  1227. caps = snd_hda_query_pin_caps(codec, pin_nid);
  1228. if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
  1229. return 0;
  1230. config = snd_hda_codec_get_pincfg(codec, pin_nid);
  1231. if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
  1232. return 0;
  1233. if (is_haswell(codec))
  1234. intel_haswell_fixup_connect_list(codec, pin_nid);
  1235. pin_idx = spec->num_pins;
  1236. per_pin = snd_array_new(&spec->pins);
  1237. if (!per_pin)
  1238. return -ENOMEM;
  1239. per_pin->pin_nid = pin_nid;
  1240. per_pin->non_pcm = false;
  1241. err = hdmi_read_pin_conn(codec, pin_idx);
  1242. if (err < 0)
  1243. return err;
  1244. spec->num_pins++;
  1245. return 0;
  1246. }
  1247. static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
  1248. {
  1249. struct hdmi_spec *spec = codec->spec;
  1250. struct hdmi_spec_per_cvt *per_cvt;
  1251. unsigned int chans;
  1252. int err;
  1253. chans = get_wcaps(codec, cvt_nid);
  1254. chans = get_wcaps_channels(chans);
  1255. per_cvt = snd_array_new(&spec->cvts);
  1256. if (!per_cvt)
  1257. return -ENOMEM;
  1258. per_cvt->cvt_nid = cvt_nid;
  1259. per_cvt->channels_min = 2;
  1260. if (chans <= 16) {
  1261. per_cvt->channels_max = chans;
  1262. if (chans > spec->channels_max)
  1263. spec->channels_max = chans;
  1264. }
  1265. err = snd_hda_query_supported_pcm(codec, cvt_nid,
  1266. &per_cvt->rates,
  1267. &per_cvt->formats,
  1268. &per_cvt->maxbps);
  1269. if (err < 0)
  1270. return err;
  1271. if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
  1272. spec->cvt_nids[spec->num_cvts] = cvt_nid;
  1273. spec->num_cvts++;
  1274. return 0;
  1275. }
  1276. static int hdmi_parse_codec(struct hda_codec *codec)
  1277. {
  1278. hda_nid_t nid;
  1279. int i, nodes;
  1280. nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
  1281. if (!nid || nodes < 0) {
  1282. snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
  1283. return -EINVAL;
  1284. }
  1285. for (i = 0; i < nodes; i++, nid++) {
  1286. unsigned int caps;
  1287. unsigned int type;
  1288. caps = get_wcaps(codec, nid);
  1289. type = get_wcaps_type(caps);
  1290. if (!(caps & AC_WCAP_DIGITAL))
  1291. continue;
  1292. switch (type) {
  1293. case AC_WID_AUD_OUT:
  1294. hdmi_add_cvt(codec, nid);
  1295. break;
  1296. case AC_WID_PIN:
  1297. hdmi_add_pin(codec, nid);
  1298. break;
  1299. }
  1300. }
  1301. #ifdef CONFIG_PM
  1302. /* We're seeing some problems with unsolicited hot plug events on
  1303. * PantherPoint after S3, if this is not enabled */
  1304. if (codec->vendor_id == 0x80862806)
  1305. codec->bus->power_keep_link_on = 1;
  1306. /*
  1307. * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
  1308. * can be lost and presence sense verb will become inaccurate if the
  1309. * HDA link is powered off at hot plug or hw initialization time.
  1310. */
  1311. else if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
  1312. AC_PWRST_EPSS))
  1313. codec->bus->power_keep_link_on = 1;
  1314. #endif
  1315. return 0;
  1316. }
  1317. /*
  1318. */
  1319. static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
  1320. {
  1321. struct hda_spdif_out *spdif;
  1322. bool non_pcm;
  1323. mutex_lock(&codec->spdif_mutex);
  1324. spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
  1325. non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
  1326. mutex_unlock(&codec->spdif_mutex);
  1327. return non_pcm;
  1328. }
  1329. /*
  1330. * HDMI callbacks
  1331. */
  1332. static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  1333. struct hda_codec *codec,
  1334. unsigned int stream_tag,
  1335. unsigned int format,
  1336. struct snd_pcm_substream *substream)
  1337. {
  1338. hda_nid_t cvt_nid = hinfo->nid;
  1339. struct hdmi_spec *spec = codec->spec;
  1340. int pin_idx = hinfo_to_pin_index(spec, hinfo);
  1341. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1342. hda_nid_t pin_nid = per_pin->pin_nid;
  1343. bool non_pcm;
  1344. non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
  1345. mutex_lock(&per_pin->sink_eld.lock);
  1346. per_pin->channels = substream->runtime->channels;
  1347. per_pin->setup = true;
  1348. hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
  1349. mutex_unlock(&per_pin->sink_eld.lock);
  1350. return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
  1351. }
  1352. static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
  1353. struct hda_codec *codec,
  1354. struct snd_pcm_substream *substream)
  1355. {
  1356. snd_hda_codec_cleanup_stream(codec, hinfo->nid);
  1357. return 0;
  1358. }
  1359. static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
  1360. struct hda_codec *codec,
  1361. struct snd_pcm_substream *substream)
  1362. {
  1363. struct hdmi_spec *spec = codec->spec;
  1364. int cvt_idx, pin_idx;
  1365. struct hdmi_spec_per_cvt *per_cvt;
  1366. struct hdmi_spec_per_pin *per_pin;
  1367. if (hinfo->nid) {
  1368. cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
  1369. if (snd_BUG_ON(cvt_idx < 0))
  1370. return -EINVAL;
  1371. per_cvt = get_cvt(spec, cvt_idx);
  1372. snd_BUG_ON(!per_cvt->assigned);
  1373. per_cvt->assigned = 0;
  1374. hinfo->nid = 0;
  1375. pin_idx = hinfo_to_pin_index(spec, hinfo);
  1376. if (snd_BUG_ON(pin_idx < 0))
  1377. return -EINVAL;
  1378. per_pin = get_pin(spec, pin_idx);
  1379. snd_hda_spdif_ctls_unassign(codec, pin_idx);
  1380. mutex_lock(&per_pin->sink_eld.lock);
  1381. per_pin->chmap_set = false;
  1382. memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
  1383. per_pin->setup = false;
  1384. per_pin->channels = 0;
  1385. mutex_unlock(&per_pin->sink_eld.lock);
  1386. }
  1387. return 0;
  1388. }
  1389. static const struct hda_pcm_ops generic_ops = {
  1390. .open = hdmi_pcm_open,
  1391. .close = hdmi_pcm_close,
  1392. .prepare = generic_hdmi_playback_pcm_prepare,
  1393. .cleanup = generic_hdmi_playback_pcm_cleanup,
  1394. };
  1395. /*
  1396. * ALSA API channel-map control callbacks
  1397. */
  1398. static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
  1399. struct snd_ctl_elem_info *uinfo)
  1400. {
  1401. struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
  1402. struct hda_codec *codec = info->private_data;
  1403. struct hdmi_spec *spec = codec->spec;
  1404. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1405. uinfo->count = spec->channels_max;
  1406. uinfo->value.integer.min = 0;
  1407. uinfo->value.integer.max = SNDRV_CHMAP_LAST;
  1408. return 0;
  1409. }
  1410. static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
  1411. unsigned int size, unsigned int __user *tlv)
  1412. {
  1413. struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
  1414. struct hda_codec *codec = info->private_data;
  1415. struct hdmi_spec *spec = codec->spec;
  1416. unsigned int __user *dst;
  1417. int chs, count = 0;
  1418. if (size < 8)
  1419. return -ENOMEM;
  1420. if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
  1421. return -EFAULT;
  1422. size -= 8;
  1423. dst = tlv + 2;
  1424. for (chs = 2; chs <= spec->channels_max; chs++) {
  1425. int i, c;
  1426. struct cea_channel_speaker_allocation *cap;
  1427. cap = channel_allocations;
  1428. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
  1429. int chs_bytes = chs * 4;
  1430. if (cap->channels != chs)
  1431. continue;
  1432. if (size < 8)
  1433. return -ENOMEM;
  1434. if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) ||
  1435. put_user(chs_bytes, dst + 1))
  1436. return -EFAULT;
  1437. dst += 2;
  1438. size -= 8;
  1439. count += 8;
  1440. if (size < chs_bytes)
  1441. return -ENOMEM;
  1442. size -= chs_bytes;
  1443. count += chs_bytes;
  1444. for (c = 7; c >= 0; c--) {
  1445. int spk = cap->speakers[c];
  1446. if (!spk)
  1447. continue;
  1448. if (put_user(spk_to_chmap(spk), dst))
  1449. return -EFAULT;
  1450. dst++;
  1451. }
  1452. }
  1453. }
  1454. if (put_user(count, tlv + 1))
  1455. return -EFAULT;
  1456. return 0;
  1457. }
  1458. static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
  1459. struct snd_ctl_elem_value *ucontrol)
  1460. {
  1461. struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
  1462. struct hda_codec *codec = info->private_data;
  1463. struct hdmi_spec *spec = codec->spec;
  1464. int pin_idx = kcontrol->private_value;
  1465. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1466. int i;
  1467. for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
  1468. ucontrol->value.integer.value[i] = per_pin->chmap[i];
  1469. return 0;
  1470. }
  1471. static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
  1472. struct snd_ctl_elem_value *ucontrol)
  1473. {
  1474. struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
  1475. struct hda_codec *codec = info->private_data;
  1476. struct hdmi_spec *spec = codec->spec;
  1477. int pin_idx = kcontrol->private_value;
  1478. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1479. unsigned int ctl_idx;
  1480. struct snd_pcm_substream *substream;
  1481. unsigned char chmap[8];
  1482. int i, ca, prepared = 0;
  1483. ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1484. substream = snd_pcm_chmap_substream(info, ctl_idx);
  1485. if (!substream || !substream->runtime)
  1486. return 0; /* just for avoiding error from alsactl restore */
  1487. switch (substream->runtime->status->state) {
  1488. case SNDRV_PCM_STATE_OPEN:
  1489. case SNDRV_PCM_STATE_SETUP:
  1490. break;
  1491. case SNDRV_PCM_STATE_PREPARED:
  1492. prepared = 1;
  1493. break;
  1494. default:
  1495. return -EBUSY;
  1496. }
  1497. memset(chmap, 0, sizeof(chmap));
  1498. for (i = 0; i < ARRAY_SIZE(chmap); i++)
  1499. chmap[i] = ucontrol->value.integer.value[i];
  1500. if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
  1501. return 0;
  1502. ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
  1503. if (ca < 0)
  1504. return -EINVAL;
  1505. mutex_lock(&per_pin->sink_eld.lock);
  1506. per_pin->chmap_set = true;
  1507. memcpy(per_pin->chmap, chmap, sizeof(chmap));
  1508. if (prepared)
  1509. hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
  1510. mutex_unlock(&per_pin->sink_eld.lock);
  1511. return 0;
  1512. }
  1513. static int generic_hdmi_build_pcms(struct hda_codec *codec)
  1514. {
  1515. struct hdmi_spec *spec = codec->spec;
  1516. int pin_idx;
  1517. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1518. struct hda_pcm *info;
  1519. struct hda_pcm_stream *pstr;
  1520. struct hdmi_spec_per_pin *per_pin;
  1521. per_pin = get_pin(spec, pin_idx);
  1522. sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
  1523. info = snd_array_new(&spec->pcm_rec);
  1524. if (!info)
  1525. return -ENOMEM;
  1526. info->name = per_pin->pcm_name;
  1527. info->pcm_type = HDA_PCM_TYPE_HDMI;
  1528. info->own_chmap = true;
  1529. pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
  1530. pstr->substreams = 1;
  1531. pstr->ops = generic_ops;
  1532. /* other pstr fields are set in open */
  1533. }
  1534. codec->num_pcms = spec->num_pins;
  1535. codec->pcm_info = spec->pcm_rec.list;
  1536. return 0;
  1537. }
  1538. static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
  1539. {
  1540. char hdmi_str[32] = "HDMI/DP";
  1541. struct hdmi_spec *spec = codec->spec;
  1542. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1543. int pcmdev = get_pcm_rec(spec, pin_idx)->device;
  1544. if (pcmdev > 0)
  1545. sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
  1546. if (!is_jack_detectable(codec, per_pin->pin_nid))
  1547. strncat(hdmi_str, " Phantom",
  1548. sizeof(hdmi_str) - strlen(hdmi_str) - 1);
  1549. return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
  1550. }
  1551. static int generic_hdmi_build_controls(struct hda_codec *codec)
  1552. {
  1553. struct hdmi_spec *spec = codec->spec;
  1554. int err;
  1555. int pin_idx;
  1556. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1557. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1558. err = generic_hdmi_build_jack(codec, pin_idx);
  1559. if (err < 0)
  1560. return err;
  1561. err = snd_hda_create_dig_out_ctls(codec,
  1562. per_pin->pin_nid,
  1563. per_pin->mux_nids[0],
  1564. HDA_PCM_TYPE_HDMI);
  1565. if (err < 0)
  1566. return err;
  1567. snd_hda_spdif_ctls_unassign(codec, pin_idx);
  1568. /* add control for ELD Bytes */
  1569. err = hdmi_create_eld_ctl(codec, pin_idx,
  1570. get_pcm_rec(spec, pin_idx)->device);
  1571. if (err < 0)
  1572. return err;
  1573. hdmi_present_sense(per_pin, 0);
  1574. }
  1575. /* add channel maps */
  1576. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1577. struct snd_pcm_chmap *chmap;
  1578. struct snd_kcontrol *kctl;
  1579. int i;
  1580. if (!codec->pcm_info[pin_idx].pcm)
  1581. break;
  1582. err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
  1583. SNDRV_PCM_STREAM_PLAYBACK,
  1584. NULL, 0, pin_idx, &chmap);
  1585. if (err < 0)
  1586. return err;
  1587. /* override handlers */
  1588. chmap->private_data = codec;
  1589. kctl = chmap->kctl;
  1590. for (i = 0; i < kctl->count; i++)
  1591. kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
  1592. kctl->info = hdmi_chmap_ctl_info;
  1593. kctl->get = hdmi_chmap_ctl_get;
  1594. kctl->put = hdmi_chmap_ctl_put;
  1595. kctl->tlv.c = hdmi_chmap_ctl_tlv;
  1596. }
  1597. return 0;
  1598. }
  1599. static int generic_hdmi_init_per_pins(struct hda_codec *codec)
  1600. {
  1601. struct hdmi_spec *spec = codec->spec;
  1602. int pin_idx;
  1603. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1604. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1605. struct hdmi_eld *eld = &per_pin->sink_eld;
  1606. per_pin->codec = codec;
  1607. mutex_init(&eld->lock);
  1608. INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
  1609. snd_hda_eld_proc_new(codec, eld, pin_idx);
  1610. }
  1611. return 0;
  1612. }
  1613. static int generic_hdmi_init(struct hda_codec *codec)
  1614. {
  1615. struct hdmi_spec *spec = codec->spec;
  1616. int pin_idx;
  1617. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1618. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1619. hda_nid_t pin_nid = per_pin->pin_nid;
  1620. hdmi_init_pin(codec, pin_nid);
  1621. snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
  1622. }
  1623. return 0;
  1624. }
  1625. static void hdmi_array_init(struct hdmi_spec *spec, int nums)
  1626. {
  1627. snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
  1628. snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
  1629. snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
  1630. }
  1631. static void hdmi_array_free(struct hdmi_spec *spec)
  1632. {
  1633. snd_array_free(&spec->pins);
  1634. snd_array_free(&spec->cvts);
  1635. snd_array_free(&spec->pcm_rec);
  1636. }
  1637. static void generic_hdmi_free(struct hda_codec *codec)
  1638. {
  1639. struct hdmi_spec *spec = codec->spec;
  1640. int pin_idx;
  1641. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1642. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1643. struct hdmi_eld *eld = &per_pin->sink_eld;
  1644. cancel_delayed_work(&per_pin->work);
  1645. snd_hda_eld_proc_free(codec, eld);
  1646. }
  1647. flush_workqueue(codec->bus->workq);
  1648. hdmi_array_free(spec);
  1649. kfree(spec);
  1650. }
  1651. #ifdef CONFIG_PM
  1652. static int generic_hdmi_resume(struct hda_codec *codec)
  1653. {
  1654. struct hdmi_spec *spec = codec->spec;
  1655. int pin_idx;
  1656. generic_hdmi_init(codec);
  1657. snd_hda_codec_resume_amp(codec);
  1658. snd_hda_codec_resume_cache(codec);
  1659. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1660. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1661. hdmi_present_sense(per_pin, 1);
  1662. }
  1663. return 0;
  1664. }
  1665. #endif
  1666. static const struct hda_codec_ops generic_hdmi_patch_ops = {
  1667. .init = generic_hdmi_init,
  1668. .free = generic_hdmi_free,
  1669. .build_pcms = generic_hdmi_build_pcms,
  1670. .build_controls = generic_hdmi_build_controls,
  1671. .unsol_event = hdmi_unsol_event,
  1672. #ifdef CONFIG_PM
  1673. .resume = generic_hdmi_resume,
  1674. #endif
  1675. };
  1676. static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
  1677. hda_nid_t nid)
  1678. {
  1679. struct hdmi_spec *spec = codec->spec;
  1680. hda_nid_t conns[4];
  1681. int nconns;
  1682. nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
  1683. if (nconns == spec->num_cvts &&
  1684. !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
  1685. return;
  1686. /* override pins connection list */
  1687. snd_printdd("hdmi: haswell: override pin connection 0x%x\n", nid);
  1688. snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
  1689. }
  1690. #define INTEL_VENDOR_NID 0x08
  1691. #define INTEL_GET_VENDOR_VERB 0xf81
  1692. #define INTEL_SET_VENDOR_VERB 0x781
  1693. #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
  1694. #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
  1695. static void intel_haswell_enable_all_pins(struct hda_codec *codec,
  1696. bool update_tree)
  1697. {
  1698. unsigned int vendor_param;
  1699. vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
  1700. INTEL_GET_VENDOR_VERB, 0);
  1701. if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
  1702. return;
  1703. vendor_param |= INTEL_EN_ALL_PIN_CVTS;
  1704. vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
  1705. INTEL_SET_VENDOR_VERB, vendor_param);
  1706. if (vendor_param == -1)
  1707. return;
  1708. if (update_tree)
  1709. snd_hda_codec_update_widgets(codec);
  1710. }
  1711. static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
  1712. {
  1713. unsigned int vendor_param;
  1714. vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
  1715. INTEL_GET_VENDOR_VERB, 0);
  1716. if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
  1717. return;
  1718. /* enable DP1.2 mode */
  1719. vendor_param |= INTEL_EN_DP12;
  1720. snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
  1721. INTEL_SET_VENDOR_VERB, vendor_param);
  1722. }
  1723. /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
  1724. * Otherwise you may get severe h/w communication errors.
  1725. */
  1726. static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
  1727. unsigned int power_state)
  1728. {
  1729. if (power_state == AC_PWRST_D0) {
  1730. intel_haswell_enable_all_pins(codec, false);
  1731. intel_haswell_fixup_enable_dp12(codec);
  1732. }
  1733. snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
  1734. snd_hda_codec_set_power_to_all(codec, fg, power_state);
  1735. }
  1736. static int patch_generic_hdmi(struct hda_codec *codec)
  1737. {
  1738. struct hdmi_spec *spec;
  1739. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  1740. if (spec == NULL)
  1741. return -ENOMEM;
  1742. codec->spec = spec;
  1743. hdmi_array_init(spec, 4);
  1744. if (is_haswell(codec)) {
  1745. intel_haswell_enable_all_pins(codec, true);
  1746. intel_haswell_fixup_enable_dp12(codec);
  1747. }
  1748. if (hdmi_parse_codec(codec) < 0) {
  1749. codec->spec = NULL;
  1750. kfree(spec);
  1751. return -EINVAL;
  1752. }
  1753. codec->patch_ops = generic_hdmi_patch_ops;
  1754. if (is_haswell(codec)) {
  1755. codec->patch_ops.set_power_state = haswell_set_power_state;
  1756. codec->dp_mst = true;
  1757. }
  1758. generic_hdmi_init_per_pins(codec);
  1759. init_channel_allocations();
  1760. return 0;
  1761. }
  1762. /*
  1763. * Shared non-generic implementations
  1764. */
  1765. static int simple_playback_build_pcms(struct hda_codec *codec)
  1766. {
  1767. struct hdmi_spec *spec = codec->spec;
  1768. struct hda_pcm *info;
  1769. unsigned int chans;
  1770. struct hda_pcm_stream *pstr;
  1771. struct hdmi_spec_per_cvt *per_cvt;
  1772. per_cvt = get_cvt(spec, 0);
  1773. chans = get_wcaps(codec, per_cvt->cvt_nid);
  1774. chans = get_wcaps_channels(chans);
  1775. info = snd_array_new(&spec->pcm_rec);
  1776. if (!info)
  1777. return -ENOMEM;
  1778. info->name = get_pin(spec, 0)->pcm_name;
  1779. sprintf(info->name, "HDMI 0");
  1780. info->pcm_type = HDA_PCM_TYPE_HDMI;
  1781. pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
  1782. *pstr = spec->pcm_playback;
  1783. pstr->nid = per_cvt->cvt_nid;
  1784. if (pstr->channels_max <= 2 && chans && chans <= 16)
  1785. pstr->channels_max = chans;
  1786. codec->num_pcms = 1;
  1787. codec->pcm_info = info;
  1788. return 0;
  1789. }
  1790. /* unsolicited event for jack sensing */
  1791. static void simple_hdmi_unsol_event(struct hda_codec *codec,
  1792. unsigned int res)
  1793. {
  1794. snd_hda_jack_set_dirty_all(codec);
  1795. snd_hda_jack_report_sync(codec);
  1796. }
  1797. /* generic_hdmi_build_jack can be used for simple_hdmi, too,
  1798. * as long as spec->pins[] is set correctly
  1799. */
  1800. #define simple_hdmi_build_jack generic_hdmi_build_jack
  1801. static int simple_playback_build_controls(struct hda_codec *codec)
  1802. {
  1803. struct hdmi_spec *spec = codec->spec;
  1804. struct hdmi_spec_per_cvt *per_cvt;
  1805. int err;
  1806. per_cvt = get_cvt(spec, 0);
  1807. err = snd_hda_create_spdif_out_ctls(codec, per_cvt->cvt_nid,
  1808. per_cvt->cvt_nid);
  1809. if (err < 0)
  1810. return err;
  1811. return simple_hdmi_build_jack(codec, 0);
  1812. }
  1813. static int simple_playback_init(struct hda_codec *codec)
  1814. {
  1815. struct hdmi_spec *spec = codec->spec;
  1816. struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
  1817. hda_nid_t pin = per_pin->pin_nid;
  1818. snd_hda_codec_write(codec, pin, 0,
  1819. AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
  1820. /* some codecs require to unmute the pin */
  1821. if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
  1822. snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
  1823. AMP_OUT_UNMUTE);
  1824. snd_hda_jack_detect_enable(codec, pin, pin);
  1825. return 0;
  1826. }
  1827. static void simple_playback_free(struct hda_codec *codec)
  1828. {
  1829. struct hdmi_spec *spec = codec->spec;
  1830. hdmi_array_free(spec);
  1831. kfree(spec);
  1832. }
  1833. /*
  1834. * Nvidia specific implementations
  1835. */
  1836. #define Nv_VERB_SET_Channel_Allocation 0xF79
  1837. #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
  1838. #define Nv_VERB_SET_Audio_Protection_On 0xF98
  1839. #define Nv_VERB_SET_Audio_Protection_Off 0xF99
  1840. #define nvhdmi_master_con_nid_7x 0x04
  1841. #define nvhdmi_master_pin_nid_7x 0x05
  1842. static const hda_nid_t nvhdmi_con_nids_7x[4] = {
  1843. /*front, rear, clfe, rear_surr */
  1844. 0x6, 0x8, 0xa, 0xc,
  1845. };
  1846. static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
  1847. /* set audio protect on */
  1848. { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
  1849. /* enable digital output on pin widget */
  1850. { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1851. {} /* terminator */
  1852. };
  1853. static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
  1854. /* set audio protect on */
  1855. { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
  1856. /* enable digital output on pin widget */
  1857. { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1858. { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1859. { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1860. { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1861. { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1862. {} /* terminator */
  1863. };
  1864. #ifdef LIMITED_RATE_FMT_SUPPORT
  1865. /* support only the safe format and rate */
  1866. #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
  1867. #define SUPPORTED_MAXBPS 16
  1868. #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
  1869. #else
  1870. /* support all rates and formats */
  1871. #define SUPPORTED_RATES \
  1872. (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
  1873. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
  1874. SNDRV_PCM_RATE_192000)
  1875. #define SUPPORTED_MAXBPS 24
  1876. #define SUPPORTED_FORMATS \
  1877. (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
  1878. #endif
  1879. static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
  1880. {
  1881. snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
  1882. return 0;
  1883. }
  1884. static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
  1885. {
  1886. snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
  1887. return 0;
  1888. }
  1889. static unsigned int channels_2_6_8[] = {
  1890. 2, 6, 8
  1891. };
  1892. static unsigned int channels_2_8[] = {
  1893. 2, 8
  1894. };
  1895. static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
  1896. .count = ARRAY_SIZE(channels_2_6_8),
  1897. .list = channels_2_6_8,
  1898. .mask = 0,
  1899. };
  1900. static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
  1901. .count = ARRAY_SIZE(channels_2_8),
  1902. .list = channels_2_8,
  1903. .mask = 0,
  1904. };
  1905. static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
  1906. struct hda_codec *codec,
  1907. struct snd_pcm_substream *substream)
  1908. {
  1909. struct hdmi_spec *spec = codec->spec;
  1910. struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
  1911. switch (codec->preset->id) {
  1912. case 0x10de0002:
  1913. case 0x10de0003:
  1914. case 0x10de0005:
  1915. case 0x10de0006:
  1916. hw_constraints_channels = &hw_constraints_2_8_channels;
  1917. break;
  1918. case 0x10de0007:
  1919. hw_constraints_channels = &hw_constraints_2_6_8_channels;
  1920. break;
  1921. default:
  1922. break;
  1923. }
  1924. if (hw_constraints_channels != NULL) {
  1925. snd_pcm_hw_constraint_list(substream->runtime, 0,
  1926. SNDRV_PCM_HW_PARAM_CHANNELS,
  1927. hw_constraints_channels);
  1928. } else {
  1929. snd_pcm_hw_constraint_step(substream->runtime, 0,
  1930. SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  1931. }
  1932. return snd_hda_multi_out_dig_open(codec, &spec->multiout);
  1933. }
  1934. static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
  1935. struct hda_codec *codec,
  1936. struct snd_pcm_substream *substream)
  1937. {
  1938. struct hdmi_spec *spec = codec->spec;
  1939. return snd_hda_multi_out_dig_close(codec, &spec->multiout);
  1940. }
  1941. static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  1942. struct hda_codec *codec,
  1943. unsigned int stream_tag,
  1944. unsigned int format,
  1945. struct snd_pcm_substream *substream)
  1946. {
  1947. struct hdmi_spec *spec = codec->spec;
  1948. return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
  1949. stream_tag, format, substream);
  1950. }
  1951. static const struct hda_pcm_stream simple_pcm_playback = {
  1952. .substreams = 1,
  1953. .channels_min = 2,
  1954. .channels_max = 2,
  1955. .ops = {
  1956. .open = simple_playback_pcm_open,
  1957. .close = simple_playback_pcm_close,
  1958. .prepare = simple_playback_pcm_prepare
  1959. },
  1960. };
  1961. static const struct hda_codec_ops simple_hdmi_patch_ops = {
  1962. .build_controls = simple_playback_build_controls,
  1963. .build_pcms = simple_playback_build_pcms,
  1964. .init = simple_playback_init,
  1965. .free = simple_playback_free,
  1966. .unsol_event = simple_hdmi_unsol_event,
  1967. };
  1968. static int patch_simple_hdmi(struct hda_codec *codec,
  1969. hda_nid_t cvt_nid, hda_nid_t pin_nid)
  1970. {
  1971. struct hdmi_spec *spec;
  1972. struct hdmi_spec_per_cvt *per_cvt;
  1973. struct hdmi_spec_per_pin *per_pin;
  1974. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  1975. if (!spec)
  1976. return -ENOMEM;
  1977. codec->spec = spec;
  1978. hdmi_array_init(spec, 1);
  1979. spec->multiout.num_dacs = 0; /* no analog */
  1980. spec->multiout.max_channels = 2;
  1981. spec->multiout.dig_out_nid = cvt_nid;
  1982. spec->num_cvts = 1;
  1983. spec->num_pins = 1;
  1984. per_pin = snd_array_new(&spec->pins);
  1985. per_cvt = snd_array_new(&spec->cvts);
  1986. if (!per_pin || !per_cvt) {
  1987. simple_playback_free(codec);
  1988. return -ENOMEM;
  1989. }
  1990. per_cvt->cvt_nid = cvt_nid;
  1991. per_pin->pin_nid = pin_nid;
  1992. spec->pcm_playback = simple_pcm_playback;
  1993. codec->patch_ops = simple_hdmi_patch_ops;
  1994. return 0;
  1995. }
  1996. static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
  1997. int channels)
  1998. {
  1999. unsigned int chanmask;
  2000. int chan = channels ? (channels - 1) : 1;
  2001. switch (channels) {
  2002. default:
  2003. case 0:
  2004. case 2:
  2005. chanmask = 0x00;
  2006. break;
  2007. case 4:
  2008. chanmask = 0x08;
  2009. break;
  2010. case 6:
  2011. chanmask = 0x0b;
  2012. break;
  2013. case 8:
  2014. chanmask = 0x13;
  2015. break;
  2016. }
  2017. /* Set the audio infoframe channel allocation and checksum fields. The
  2018. * channel count is computed implicitly by the hardware. */
  2019. snd_hda_codec_write(codec, 0x1, 0,
  2020. Nv_VERB_SET_Channel_Allocation, chanmask);
  2021. snd_hda_codec_write(codec, 0x1, 0,
  2022. Nv_VERB_SET_Info_Frame_Checksum,
  2023. (0x71 - chan - chanmask));
  2024. }
  2025. static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
  2026. struct hda_codec *codec,
  2027. struct snd_pcm_substream *substream)
  2028. {
  2029. struct hdmi_spec *spec = codec->spec;
  2030. int i;
  2031. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
  2032. 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
  2033. for (i = 0; i < 4; i++) {
  2034. /* set the stream id */
  2035. snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
  2036. AC_VERB_SET_CHANNEL_STREAMID, 0);
  2037. /* set the stream format */
  2038. snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
  2039. AC_VERB_SET_STREAM_FORMAT, 0);
  2040. }
  2041. /* The audio hardware sends a channel count of 0x7 (8ch) when all the
  2042. * streams are disabled. */
  2043. nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
  2044. return snd_hda_multi_out_dig_close(codec, &spec->multiout);
  2045. }
  2046. static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
  2047. struct hda_codec *codec,
  2048. unsigned int stream_tag,
  2049. unsigned int format,
  2050. struct snd_pcm_substream *substream)
  2051. {
  2052. int chs;
  2053. unsigned int dataDCC2, channel_id;
  2054. int i;
  2055. struct hdmi_spec *spec = codec->spec;
  2056. struct hda_spdif_out *spdif;
  2057. struct hdmi_spec_per_cvt *per_cvt;
  2058. mutex_lock(&codec->spdif_mutex);
  2059. per_cvt = get_cvt(spec, 0);
  2060. spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
  2061. chs = substream->runtime->channels;
  2062. dataDCC2 = 0x2;
  2063. /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
  2064. if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
  2065. snd_hda_codec_write(codec,
  2066. nvhdmi_master_con_nid_7x,
  2067. 0,
  2068. AC_VERB_SET_DIGI_CONVERT_1,
  2069. spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
  2070. /* set the stream id */
  2071. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
  2072. AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
  2073. /* set the stream format */
  2074. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
  2075. AC_VERB_SET_STREAM_FORMAT, format);
  2076. /* turn on again (if needed) */
  2077. /* enable and set the channel status audio/data flag */
  2078. if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
  2079. snd_hda_codec_write(codec,
  2080. nvhdmi_master_con_nid_7x,
  2081. 0,
  2082. AC_VERB_SET_DIGI_CONVERT_1,
  2083. spdif->ctls & 0xff);
  2084. snd_hda_codec_write(codec,
  2085. nvhdmi_master_con_nid_7x,
  2086. 0,
  2087. AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
  2088. }
  2089. for (i = 0; i < 4; i++) {
  2090. if (chs == 2)
  2091. channel_id = 0;
  2092. else
  2093. channel_id = i * 2;
  2094. /* turn off SPDIF once;
  2095. *otherwise the IEC958 bits won't be updated
  2096. */
  2097. if (codec->spdif_status_reset &&
  2098. (spdif->ctls & AC_DIG1_ENABLE))
  2099. snd_hda_codec_write(codec,
  2100. nvhdmi_con_nids_7x[i],
  2101. 0,
  2102. AC_VERB_SET_DIGI_CONVERT_1,
  2103. spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
  2104. /* set the stream id */
  2105. snd_hda_codec_write(codec,
  2106. nvhdmi_con_nids_7x[i],
  2107. 0,
  2108. AC_VERB_SET_CHANNEL_STREAMID,
  2109. (stream_tag << 4) | channel_id);
  2110. /* set the stream format */
  2111. snd_hda_codec_write(codec,
  2112. nvhdmi_con_nids_7x[i],
  2113. 0,
  2114. AC_VERB_SET_STREAM_FORMAT,
  2115. format);
  2116. /* turn on again (if needed) */
  2117. /* enable and set the channel status audio/data flag */
  2118. if (codec->spdif_status_reset &&
  2119. (spdif->ctls & AC_DIG1_ENABLE)) {
  2120. snd_hda_codec_write(codec,
  2121. nvhdmi_con_nids_7x[i],
  2122. 0,
  2123. AC_VERB_SET_DIGI_CONVERT_1,
  2124. spdif->ctls & 0xff);
  2125. snd_hda_codec_write(codec,
  2126. nvhdmi_con_nids_7x[i],
  2127. 0,
  2128. AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
  2129. }
  2130. }
  2131. nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
  2132. mutex_unlock(&codec->spdif_mutex);
  2133. return 0;
  2134. }
  2135. static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
  2136. .substreams = 1,
  2137. .channels_min = 2,
  2138. .channels_max = 8,
  2139. .nid = nvhdmi_master_con_nid_7x,
  2140. .rates = SUPPORTED_RATES,
  2141. .maxbps = SUPPORTED_MAXBPS,
  2142. .formats = SUPPORTED_FORMATS,
  2143. .ops = {
  2144. .open = simple_playback_pcm_open,
  2145. .close = nvhdmi_8ch_7x_pcm_close,
  2146. .prepare = nvhdmi_8ch_7x_pcm_prepare
  2147. },
  2148. };
  2149. static int patch_nvhdmi_2ch(struct hda_codec *codec)
  2150. {
  2151. struct hdmi_spec *spec;
  2152. int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
  2153. nvhdmi_master_pin_nid_7x);
  2154. if (err < 0)
  2155. return err;
  2156. codec->patch_ops.init = nvhdmi_7x_init_2ch;
  2157. /* override the PCM rates, etc, as the codec doesn't give full list */
  2158. spec = codec->spec;
  2159. spec->pcm_playback.rates = SUPPORTED_RATES;
  2160. spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
  2161. spec->pcm_playback.formats = SUPPORTED_FORMATS;
  2162. return 0;
  2163. }
  2164. static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
  2165. {
  2166. struct hdmi_spec *spec = codec->spec;
  2167. int err = simple_playback_build_pcms(codec);
  2168. if (!err) {
  2169. struct hda_pcm *info = get_pcm_rec(spec, 0);
  2170. info->own_chmap = true;
  2171. }
  2172. return err;
  2173. }
  2174. static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
  2175. {
  2176. struct hdmi_spec *spec = codec->spec;
  2177. struct hda_pcm *info;
  2178. struct snd_pcm_chmap *chmap;
  2179. int err;
  2180. err = simple_playback_build_controls(codec);
  2181. if (err < 0)
  2182. return err;
  2183. /* add channel maps */
  2184. info = get_pcm_rec(spec, 0);
  2185. err = snd_pcm_add_chmap_ctls(info->pcm,
  2186. SNDRV_PCM_STREAM_PLAYBACK,
  2187. snd_pcm_alt_chmaps, 8, 0, &chmap);
  2188. if (err < 0)
  2189. return err;
  2190. switch (codec->preset->id) {
  2191. case 0x10de0002:
  2192. case 0x10de0003:
  2193. case 0x10de0005:
  2194. case 0x10de0006:
  2195. chmap->channel_mask = (1U << 2) | (1U << 8);
  2196. break;
  2197. case 0x10de0007:
  2198. chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
  2199. }
  2200. return 0;
  2201. }
  2202. static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
  2203. {
  2204. struct hdmi_spec *spec;
  2205. int err = patch_nvhdmi_2ch(codec);
  2206. if (err < 0)
  2207. return err;
  2208. spec = codec->spec;
  2209. spec->multiout.max_channels = 8;
  2210. spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
  2211. codec->patch_ops.init = nvhdmi_7x_init_8ch;
  2212. codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
  2213. codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
  2214. /* Initialize the audio infoframe channel mask and checksum to something
  2215. * valid */
  2216. nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
  2217. return 0;
  2218. }
  2219. /*
  2220. * ATI-specific implementations
  2221. *
  2222. * FIXME: we may omit the whole this and use the generic code once after
  2223. * it's confirmed to work.
  2224. */
  2225. #define ATIHDMI_CVT_NID 0x02 /* audio converter */
  2226. #define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
  2227. static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  2228. struct hda_codec *codec,
  2229. unsigned int stream_tag,
  2230. unsigned int format,
  2231. struct snd_pcm_substream *substream)
  2232. {
  2233. struct hdmi_spec *spec = codec->spec;
  2234. struct hdmi_spec_per_cvt *per_cvt = get_cvt(spec, 0);
  2235. int chans = substream->runtime->channels;
  2236. int i, err;
  2237. err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
  2238. substream);
  2239. if (err < 0)
  2240. return err;
  2241. snd_hda_codec_write(codec, per_cvt->cvt_nid, 0,
  2242. AC_VERB_SET_CVT_CHAN_COUNT, chans - 1);
  2243. /* FIXME: XXX */
  2244. for (i = 0; i < chans; i++) {
  2245. snd_hda_codec_write(codec, per_cvt->cvt_nid, 0,
  2246. AC_VERB_SET_HDMI_CHAN_SLOT,
  2247. (i << 4) | i);
  2248. }
  2249. return 0;
  2250. }
  2251. static int patch_atihdmi(struct hda_codec *codec)
  2252. {
  2253. struct hdmi_spec *spec;
  2254. int err = patch_simple_hdmi(codec, ATIHDMI_CVT_NID, ATIHDMI_PIN_NID);
  2255. if (err < 0)
  2256. return err;
  2257. spec = codec->spec;
  2258. spec->pcm_playback.ops.prepare = atihdmi_playback_pcm_prepare;
  2259. return 0;
  2260. }
  2261. /* VIA HDMI Implementation */
  2262. #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
  2263. #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
  2264. static int patch_via_hdmi(struct hda_codec *codec)
  2265. {
  2266. return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
  2267. }
  2268. /*
  2269. * patch entries
  2270. */
  2271. static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
  2272. { .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
  2273. { .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
  2274. { .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
  2275. { .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
  2276. { .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
  2277. { .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
  2278. { .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
  2279. { .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  2280. { .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  2281. { .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  2282. { .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  2283. { .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
  2284. { .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
  2285. { .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
  2286. { .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
  2287. { .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
  2288. { .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
  2289. { .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
  2290. { .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
  2291. { .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
  2292. { .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
  2293. { .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
  2294. { .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
  2295. /* 17 is known to be absent */
  2296. { .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
  2297. { .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
  2298. { .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
  2299. { .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
  2300. { .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
  2301. { .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
  2302. { .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
  2303. { .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
  2304. { .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
  2305. { .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
  2306. { .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_generic_hdmi },
  2307. { .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_generic_hdmi },
  2308. { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
  2309. { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
  2310. { .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
  2311. { .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
  2312. { .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
  2313. { .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
  2314. { .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
  2315. { .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
  2316. { .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
  2317. { .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
  2318. { .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
  2319. { .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
  2320. { .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
  2321. { .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
  2322. { .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
  2323. { .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
  2324. {} /* terminator */
  2325. };
  2326. MODULE_ALIAS("snd-hda-codec-id:1002793c");
  2327. MODULE_ALIAS("snd-hda-codec-id:10027919");
  2328. MODULE_ALIAS("snd-hda-codec-id:1002791a");
  2329. MODULE_ALIAS("snd-hda-codec-id:1002aa01");
  2330. MODULE_ALIAS("snd-hda-codec-id:10951390");
  2331. MODULE_ALIAS("snd-hda-codec-id:10951392");
  2332. MODULE_ALIAS("snd-hda-codec-id:10de0002");
  2333. MODULE_ALIAS("snd-hda-codec-id:10de0003");
  2334. MODULE_ALIAS("snd-hda-codec-id:10de0005");
  2335. MODULE_ALIAS("snd-hda-codec-id:10de0006");
  2336. MODULE_ALIAS("snd-hda-codec-id:10de0007");
  2337. MODULE_ALIAS("snd-hda-codec-id:10de000a");
  2338. MODULE_ALIAS("snd-hda-codec-id:10de000b");
  2339. MODULE_ALIAS("snd-hda-codec-id:10de000c");
  2340. MODULE_ALIAS("snd-hda-codec-id:10de000d");
  2341. MODULE_ALIAS("snd-hda-codec-id:10de0010");
  2342. MODULE_ALIAS("snd-hda-codec-id:10de0011");
  2343. MODULE_ALIAS("snd-hda-codec-id:10de0012");
  2344. MODULE_ALIAS("snd-hda-codec-id:10de0013");
  2345. MODULE_ALIAS("snd-hda-codec-id:10de0014");
  2346. MODULE_ALIAS("snd-hda-codec-id:10de0015");
  2347. MODULE_ALIAS("snd-hda-codec-id:10de0016");
  2348. MODULE_ALIAS("snd-hda-codec-id:10de0018");
  2349. MODULE_ALIAS("snd-hda-codec-id:10de0019");
  2350. MODULE_ALIAS("snd-hda-codec-id:10de001a");
  2351. MODULE_ALIAS("snd-hda-codec-id:10de001b");
  2352. MODULE_ALIAS("snd-hda-codec-id:10de001c");
  2353. MODULE_ALIAS("snd-hda-codec-id:10de0040");
  2354. MODULE_ALIAS("snd-hda-codec-id:10de0041");
  2355. MODULE_ALIAS("snd-hda-codec-id:10de0042");
  2356. MODULE_ALIAS("snd-hda-codec-id:10de0043");
  2357. MODULE_ALIAS("snd-hda-codec-id:10de0044");
  2358. MODULE_ALIAS("snd-hda-codec-id:10de0051");
  2359. MODULE_ALIAS("snd-hda-codec-id:10de0060");
  2360. MODULE_ALIAS("snd-hda-codec-id:10de0067");
  2361. MODULE_ALIAS("snd-hda-codec-id:10de8001");
  2362. MODULE_ALIAS("snd-hda-codec-id:11069f80");
  2363. MODULE_ALIAS("snd-hda-codec-id:11069f81");
  2364. MODULE_ALIAS("snd-hda-codec-id:11069f84");
  2365. MODULE_ALIAS("snd-hda-codec-id:11069f85");
  2366. MODULE_ALIAS("snd-hda-codec-id:17e80047");
  2367. MODULE_ALIAS("snd-hda-codec-id:80860054");
  2368. MODULE_ALIAS("snd-hda-codec-id:80862801");
  2369. MODULE_ALIAS("snd-hda-codec-id:80862802");
  2370. MODULE_ALIAS("snd-hda-codec-id:80862803");
  2371. MODULE_ALIAS("snd-hda-codec-id:80862804");
  2372. MODULE_ALIAS("snd-hda-codec-id:80862805");
  2373. MODULE_ALIAS("snd-hda-codec-id:80862806");
  2374. MODULE_ALIAS("snd-hda-codec-id:80862807");
  2375. MODULE_ALIAS("snd-hda-codec-id:80862880");
  2376. MODULE_ALIAS("snd-hda-codec-id:808629fb");
  2377. MODULE_LICENSE("GPL");
  2378. MODULE_DESCRIPTION("HDMI HD-audio codec");
  2379. MODULE_ALIAS("snd-hda-codec-intelhdmi");
  2380. MODULE_ALIAS("snd-hda-codec-nvhdmi");
  2381. MODULE_ALIAS("snd-hda-codec-atihdmi");
  2382. static struct hda_codec_preset_list intel_list = {
  2383. .preset = snd_hda_preset_hdmi,
  2384. .owner = THIS_MODULE,
  2385. };
  2386. static int __init patch_hdmi_init(void)
  2387. {
  2388. return snd_hda_add_codec_preset(&intel_list);
  2389. }
  2390. static void __exit patch_hdmi_exit(void)
  2391. {
  2392. snd_hda_delete_codec_preset(&intel_list);
  2393. }
  2394. module_init(patch_hdmi_init)
  2395. module_exit(patch_hdmi_exit)