iwl3945-base.c 221 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/ieee80211_radiotap.h>
  42. #include <net/lib80211.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #define DRV_NAME "iwl3945"
  46. #include "iwl-commands.h"
  47. #include "iwl-3945.h"
  48. #include "iwl-3945-fh.h"
  49. #include "iwl-helpers.h"
  50. #include "iwl-core.h"
  51. #include "iwl-dev.h"
  52. static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
  53. struct iwl3945_tx_queue *txq);
  54. /*
  55. * module name, copyright, version, etc.
  56. */
  57. #define DRV_DESCRIPTION \
  58. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  59. #ifdef CONFIG_IWL3945_DEBUG
  60. #define VD "d"
  61. #else
  62. #define VD
  63. #endif
  64. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  65. #define VS "s"
  66. #else
  67. #define VS
  68. #endif
  69. #define IWL39_VERSION "1.2.26k" VD VS
  70. #define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
  71. #define DRV_AUTHOR "<ilw@linux.intel.com>"
  72. #define DRV_VERSION IWL39_VERSION
  73. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  74. MODULE_VERSION(DRV_VERSION);
  75. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  76. MODULE_LICENSE("GPL");
  77. /* module parameters */
  78. struct iwl_mod_params iwl3945_mod_params = {
  79. .num_of_queues = IWL39_MAX_NUM_QUEUES,
  80. /* the rest are 0 by default */
  81. };
  82. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  83. * DMA services
  84. *
  85. * Theory of operation
  86. *
  87. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  88. * of buffer descriptors, each of which points to one or more data buffers for
  89. * the device to read from or fill. Driver and device exchange status of each
  90. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  91. * entries in each circular buffer, to protect against confusing empty and full
  92. * queue states.
  93. *
  94. * The device reads or writes the data in the queues via the device's several
  95. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  96. *
  97. * For Tx queue, there are low mark and high mark limits. If, after queuing
  98. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  99. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  100. * Tx queue resumed.
  101. *
  102. * The 3945 operates with six queues: One receive queue, one transmit queue
  103. * (#4) for sending commands to the device firmware, and four transmit queues
  104. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  105. ***************************************************/
  106. int iwl3945_x2_queue_used(const struct iwl_queue *q, int i)
  107. {
  108. return q->write_ptr > q->read_ptr ?
  109. (i >= q->read_ptr && i < q->write_ptr) :
  110. !(i < q->read_ptr && i >= q->write_ptr);
  111. }
  112. /**
  113. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  114. */
  115. static int iwl3945_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
  116. int count, int slots_num, u32 id)
  117. {
  118. q->n_bd = count;
  119. q->n_window = slots_num;
  120. q->id = id;
  121. /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
  122. * and iwl_queue_dec_wrap are broken. */
  123. BUG_ON(!is_power_of_2(count));
  124. /* slots_num must be power-of-two size, otherwise
  125. * get_cmd_index is broken. */
  126. BUG_ON(!is_power_of_2(slots_num));
  127. q->low_mark = q->n_window / 4;
  128. if (q->low_mark < 4)
  129. q->low_mark = 4;
  130. q->high_mark = q->n_window / 8;
  131. if (q->high_mark < 2)
  132. q->high_mark = 2;
  133. q->write_ptr = q->read_ptr = 0;
  134. return 0;
  135. }
  136. /**
  137. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  138. */
  139. static int iwl3945_tx_queue_alloc(struct iwl_priv *priv,
  140. struct iwl3945_tx_queue *txq, u32 id)
  141. {
  142. struct pci_dev *dev = priv->pci_dev;
  143. /* Driver private data, only for Tx (not command) queues,
  144. * not shared with device. */
  145. if (id != IWL_CMD_QUEUE_NUM) {
  146. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  147. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  148. if (!txq->txb) {
  149. IWL_ERR(priv, "kmalloc for auxiliary BD "
  150. "structures failed\n");
  151. goto error;
  152. }
  153. } else
  154. txq->txb = NULL;
  155. /* Circular buffer of transmit frame descriptors (TFDs),
  156. * shared with device */
  157. txq->bd = pci_alloc_consistent(dev,
  158. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  159. &txq->q.dma_addr);
  160. if (!txq->bd) {
  161. IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n",
  162. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  163. goto error;
  164. }
  165. txq->q.id = id;
  166. return 0;
  167. error:
  168. kfree(txq->txb);
  169. txq->txb = NULL;
  170. return -ENOMEM;
  171. }
  172. /**
  173. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  174. */
  175. int iwl3945_tx_queue_init(struct iwl_priv *priv,
  176. struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
  177. {
  178. struct pci_dev *dev = priv->pci_dev;
  179. int len;
  180. int rc = 0;
  181. /*
  182. * Alloc buffer array for commands (Tx or other types of commands).
  183. * For the command queue (#4), allocate command space + one big
  184. * command for scan, since scan command is very huge; the system will
  185. * not have two scans at the same time, so only one is needed.
  186. * For data Tx queues (all other queues), no super-size command
  187. * space is needed.
  188. */
  189. len = sizeof(struct iwl_cmd) * slots_num;
  190. if (txq_id == IWL_CMD_QUEUE_NUM)
  191. len += IWL_MAX_SCAN_SIZE;
  192. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  193. if (!txq->cmd)
  194. return -ENOMEM;
  195. /* Alloc driver data array and TFD circular buffer */
  196. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  197. if (rc) {
  198. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  199. return -ENOMEM;
  200. }
  201. txq->need_update = 0;
  202. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  203. * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
  204. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  205. /* Initialize queue high/low-water, head/tail indexes */
  206. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  207. /* Tell device where to find queue, enable DMA channel. */
  208. iwl3945_hw_tx_queue_init(priv, txq);
  209. return 0;
  210. }
  211. /**
  212. * iwl3945_tx_queue_free - Deallocate DMA queue.
  213. * @txq: Transmit queue to deallocate.
  214. *
  215. * Empty queue by removing and destroying all BD's.
  216. * Free all buffers.
  217. * 0-fill, but do not free "txq" descriptor structure.
  218. */
  219. void iwl3945_tx_queue_free(struct iwl_priv *priv, struct iwl3945_tx_queue *txq)
  220. {
  221. struct iwl_queue *q = &txq->q;
  222. struct pci_dev *dev = priv->pci_dev;
  223. int len;
  224. if (q->n_bd == 0)
  225. return;
  226. /* first, empty all BD's */
  227. for (; q->write_ptr != q->read_ptr;
  228. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
  229. iwl3945_hw_txq_free_tfd(priv, txq);
  230. len = sizeof(struct iwl_cmd) * q->n_window;
  231. if (q->id == IWL_CMD_QUEUE_NUM)
  232. len += IWL_MAX_SCAN_SIZE;
  233. /* De-alloc array of command/tx buffers */
  234. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  235. /* De-alloc circular buffer of TFDs */
  236. if (txq->q.n_bd)
  237. pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
  238. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  239. /* De-alloc array of per-TFD driver data */
  240. kfree(txq->txb);
  241. txq->txb = NULL;
  242. /* 0-fill queue descriptor structure */
  243. memset(txq, 0, sizeof(*txq));
  244. }
  245. /*************** STATION TABLE MANAGEMENT ****
  246. * mac80211 should be examined to determine if sta_info is duplicating
  247. * the functionality provided here
  248. */
  249. /**************************************************************/
  250. #if 0 /* temporary disable till we add real remove station */
  251. /**
  252. * iwl3945_remove_station - Remove driver's knowledge of station.
  253. *
  254. * NOTE: This does not remove station from device's station table.
  255. */
  256. static u8 iwl3945_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
  257. {
  258. int index = IWL_INVALID_STATION;
  259. int i;
  260. unsigned long flags;
  261. spin_lock_irqsave(&priv->sta_lock, flags);
  262. if (is_ap)
  263. index = IWL_AP_ID;
  264. else if (is_broadcast_ether_addr(addr))
  265. index = priv->hw_params.bcast_sta_id;
  266. else
  267. for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++)
  268. if (priv->stations_39[i].used &&
  269. !compare_ether_addr(priv->stations_39[i].sta.sta.addr,
  270. addr)) {
  271. index = i;
  272. break;
  273. }
  274. if (unlikely(index == IWL_INVALID_STATION))
  275. goto out;
  276. if (priv->stations_39[index].used) {
  277. priv->stations_39[index].used = 0;
  278. priv->num_stations--;
  279. }
  280. BUG_ON(priv->num_stations < 0);
  281. out:
  282. spin_unlock_irqrestore(&priv->sta_lock, flags);
  283. return 0;
  284. }
  285. #endif
  286. /**
  287. * iwl3945_clear_stations_table - Clear the driver's station table
  288. *
  289. * NOTE: This does not clear or otherwise alter the device's station table.
  290. */
  291. static void iwl3945_clear_stations_table(struct iwl_priv *priv)
  292. {
  293. unsigned long flags;
  294. spin_lock_irqsave(&priv->sta_lock, flags);
  295. priv->num_stations = 0;
  296. memset(priv->stations_39, 0, sizeof(priv->stations_39));
  297. spin_unlock_irqrestore(&priv->sta_lock, flags);
  298. }
  299. /**
  300. * iwl3945_add_station - Add station to station tables in driver and device
  301. */
  302. u8 iwl3945_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap, u8 flags)
  303. {
  304. int i;
  305. int index = IWL_INVALID_STATION;
  306. struct iwl3945_station_entry *station;
  307. unsigned long flags_spin;
  308. u8 rate;
  309. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  310. if (is_ap)
  311. index = IWL_AP_ID;
  312. else if (is_broadcast_ether_addr(addr))
  313. index = priv->hw_params.bcast_sta_id;
  314. else
  315. for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++) {
  316. if (!compare_ether_addr(priv->stations_39[i].sta.sta.addr,
  317. addr)) {
  318. index = i;
  319. break;
  320. }
  321. if (!priv->stations_39[i].used &&
  322. index == IWL_INVALID_STATION)
  323. index = i;
  324. }
  325. /* These two conditions has the same outcome but keep them separate
  326. since they have different meaning */
  327. if (unlikely(index == IWL_INVALID_STATION)) {
  328. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  329. return index;
  330. }
  331. if (priv->stations_39[index].used &&
  332. !compare_ether_addr(priv->stations_39[index].sta.sta.addr, addr)) {
  333. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  334. return index;
  335. }
  336. IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
  337. station = &priv->stations_39[index];
  338. station->used = 1;
  339. priv->num_stations++;
  340. /* Set up the REPLY_ADD_STA command to send to device */
  341. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  342. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  343. station->sta.mode = 0;
  344. station->sta.sta.sta_id = index;
  345. station->sta.station_flags = 0;
  346. if (priv->band == IEEE80211_BAND_5GHZ)
  347. rate = IWL_RATE_6M_PLCP;
  348. else
  349. rate = IWL_RATE_1M_PLCP;
  350. /* Turn on both antennas for the station... */
  351. station->sta.rate_n_flags =
  352. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  353. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  354. /* Add station to device's station table */
  355. iwl3945_send_add_station(priv, &station->sta, flags);
  356. return index;
  357. }
  358. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  359. #define IWL_CMD(x) case x: return #x
  360. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  361. /**
  362. * iwl3945_enqueue_hcmd - enqueue a uCode command
  363. * @priv: device private data point
  364. * @cmd: a point to the ucode command structure
  365. *
  366. * The function returns < 0 values to indicate the operation is
  367. * failed. On success, it turns the index (> 0) of command in the
  368. * command queue.
  369. */
  370. static int iwl3945_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
  371. {
  372. struct iwl3945_tx_queue *txq = &priv->txq39[IWL_CMD_QUEUE_NUM];
  373. struct iwl_queue *q = &txq->q;
  374. struct iwl3945_tfd_frame *tfd;
  375. u32 *control_flags;
  376. struct iwl_cmd *out_cmd;
  377. u32 idx;
  378. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  379. dma_addr_t phys_addr;
  380. int pad;
  381. u16 count;
  382. int ret;
  383. unsigned long flags;
  384. /* If any of the command structures end up being larger than
  385. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  386. * we will need to increase the size of the TFD entries */
  387. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  388. !(cmd->meta.flags & CMD_SIZE_HUGE));
  389. if (iwl_is_rfkill(priv)) {
  390. IWL_DEBUG_INFO("Not sending command - RF KILL");
  391. return -EIO;
  392. }
  393. if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  394. IWL_ERR(priv, "No space for Tx\n");
  395. return -ENOSPC;
  396. }
  397. spin_lock_irqsave(&priv->hcmd_lock, flags);
  398. tfd = &txq->bd[q->write_ptr];
  399. memset(tfd, 0, sizeof(*tfd));
  400. control_flags = (u32 *) tfd;
  401. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  402. out_cmd = &txq->cmd[idx];
  403. out_cmd->hdr.cmd = cmd->id;
  404. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  405. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  406. /* At this point, the out_cmd now has all of the incoming cmd
  407. * information */
  408. out_cmd->hdr.flags = 0;
  409. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  410. INDEX_TO_SEQ(q->write_ptr));
  411. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  412. out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
  413. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  414. offsetof(struct iwl_cmd, hdr);
  415. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  416. pad = U32_PAD(cmd->len);
  417. count = TFD_CTL_COUNT_GET(*control_flags);
  418. *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
  419. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  420. "%d bytes at %d[%d]:%d\n",
  421. get_cmd_string(out_cmd->hdr.cmd),
  422. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  423. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  424. txq->need_update = 1;
  425. /* Increment and update queue's write index */
  426. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  427. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  428. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  429. return ret ? ret : idx;
  430. }
  431. static int iwl3945_send_cmd_async(struct iwl_priv *priv,
  432. struct iwl_host_cmd *cmd)
  433. {
  434. int ret;
  435. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  436. /* An asynchronous command can not expect an SKB to be set. */
  437. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  438. /* An asynchronous command MUST have a callback. */
  439. BUG_ON(!cmd->meta.u.callback);
  440. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  441. return -EBUSY;
  442. ret = iwl3945_enqueue_hcmd(priv, cmd);
  443. if (ret < 0) {
  444. IWL_ERR(priv,
  445. "Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  446. get_cmd_string(cmd->id), ret);
  447. return ret;
  448. }
  449. return 0;
  450. }
  451. static int iwl3945_send_cmd_sync(struct iwl_priv *priv,
  452. struct iwl_host_cmd *cmd)
  453. {
  454. int cmd_idx;
  455. int ret;
  456. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  457. /* A synchronous command can not have a callback set. */
  458. BUG_ON(cmd->meta.u.callback != NULL);
  459. if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
  460. IWL_ERR(priv,
  461. "Error sending %s: Already sending a host command\n",
  462. get_cmd_string(cmd->id));
  463. ret = -EBUSY;
  464. goto out;
  465. }
  466. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  467. if (cmd->meta.flags & CMD_WANT_SKB)
  468. cmd->meta.source = &cmd->meta;
  469. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  470. if (cmd_idx < 0) {
  471. ret = cmd_idx;
  472. IWL_ERR(priv,
  473. "Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  474. get_cmd_string(cmd->id), ret);
  475. goto out;
  476. }
  477. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  478. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  479. HOST_COMPLETE_TIMEOUT);
  480. if (!ret) {
  481. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  482. IWL_ERR(priv, "Error sending %s: time out after %dms\n",
  483. get_cmd_string(cmd->id),
  484. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  485. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  486. ret = -ETIMEDOUT;
  487. goto cancel;
  488. }
  489. }
  490. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  491. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  492. get_cmd_string(cmd->id));
  493. ret = -ECANCELED;
  494. goto fail;
  495. }
  496. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  497. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  498. get_cmd_string(cmd->id));
  499. ret = -EIO;
  500. goto fail;
  501. }
  502. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  503. IWL_ERR(priv, "Error: Response NULL in '%s'\n",
  504. get_cmd_string(cmd->id));
  505. ret = -EIO;
  506. goto cancel;
  507. }
  508. ret = 0;
  509. goto out;
  510. cancel:
  511. if (cmd->meta.flags & CMD_WANT_SKB) {
  512. struct iwl_cmd *qcmd;
  513. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  514. * TX cmd queue. Otherwise in case the cmd comes
  515. * in later, it will possibly set an invalid
  516. * address (cmd->meta.source). */
  517. qcmd = &priv->txq39[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  518. qcmd->meta.flags &= ~CMD_WANT_SKB;
  519. }
  520. fail:
  521. if (cmd->meta.u.skb) {
  522. dev_kfree_skb_any(cmd->meta.u.skb);
  523. cmd->meta.u.skb = NULL;
  524. }
  525. out:
  526. clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
  527. return ret;
  528. }
  529. int iwl3945_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
  530. {
  531. if (cmd->meta.flags & CMD_ASYNC)
  532. return iwl3945_send_cmd_async(priv, cmd);
  533. return iwl3945_send_cmd_sync(priv, cmd);
  534. }
  535. int iwl3945_send_cmd_pdu(struct iwl_priv *priv, u8 id, u16 len, const void *data)
  536. {
  537. struct iwl_host_cmd cmd = {
  538. .id = id,
  539. .len = len,
  540. .data = data,
  541. };
  542. return iwl3945_send_cmd_sync(priv, &cmd);
  543. }
  544. static int __must_check iwl3945_send_cmd_u32(struct iwl_priv *priv, u8 id, u32 val)
  545. {
  546. struct iwl_host_cmd cmd = {
  547. .id = id,
  548. .len = sizeof(val),
  549. .data = &val,
  550. };
  551. return iwl3945_send_cmd_sync(priv, &cmd);
  552. }
  553. int iwl3945_send_statistics_request(struct iwl_priv *priv)
  554. {
  555. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  556. }
  557. /**
  558. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  559. * @band: 2.4 or 5 GHz band
  560. * @channel: Any channel valid for the requested band
  561. * In addition to setting the staging RXON, priv->band is also set.
  562. *
  563. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  564. * in the staging RXON flag structure based on the band
  565. */
  566. static int iwl3945_set_rxon_channel(struct iwl_priv *priv,
  567. enum ieee80211_band band,
  568. u16 channel)
  569. {
  570. if (!iwl3945_get_channel_info(priv, band, channel)) {
  571. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  572. channel, band);
  573. return -EINVAL;
  574. }
  575. if ((le16_to_cpu(priv->staging39_rxon.channel) == channel) &&
  576. (priv->band == band))
  577. return 0;
  578. priv->staging39_rxon.channel = cpu_to_le16(channel);
  579. if (band == IEEE80211_BAND_5GHZ)
  580. priv->staging39_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  581. else
  582. priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  583. priv->band = band;
  584. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  585. return 0;
  586. }
  587. /**
  588. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  589. *
  590. * NOTE: This is really only useful during development and can eventually
  591. * be #ifdef'd out once the driver is stable and folks aren't actively
  592. * making changes
  593. */
  594. static int iwl3945_check_rxon_cmd(struct iwl_priv *priv)
  595. {
  596. int error = 0;
  597. int counter = 1;
  598. struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
  599. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  600. error |= le32_to_cpu(rxon->flags &
  601. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  602. RXON_FLG_RADAR_DETECT_MSK));
  603. if (error)
  604. IWL_WARN(priv, "check 24G fields %d | %d\n",
  605. counter++, error);
  606. } else {
  607. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  608. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  609. if (error)
  610. IWL_WARN(priv, "check 52 fields %d | %d\n",
  611. counter++, error);
  612. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  613. if (error)
  614. IWL_WARN(priv, "check 52 CCK %d | %d\n",
  615. counter++, error);
  616. }
  617. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  618. if (error)
  619. IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
  620. /* make sure basic rates 6Mbps and 1Mbps are supported */
  621. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  622. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  623. if (error)
  624. IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
  625. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  626. if (error)
  627. IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
  628. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  629. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  630. if (error)
  631. IWL_WARN(priv, "check CCK and short slot %d | %d\n",
  632. counter++, error);
  633. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  634. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  635. if (error)
  636. IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
  637. counter++, error);
  638. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  639. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  640. if (error)
  641. IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
  642. counter++, error);
  643. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  644. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  645. RXON_FLG_ANT_A_MSK)) == 0);
  646. if (error)
  647. IWL_WARN(priv, "check antenna %d %d\n", counter++, error);
  648. if (error)
  649. IWL_WARN(priv, "Tuning to channel %d\n",
  650. le16_to_cpu(rxon->channel));
  651. if (error) {
  652. IWL_ERR(priv, "Not a valid rxon_assoc_cmd field values\n");
  653. return -1;
  654. }
  655. return 0;
  656. }
  657. /**
  658. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  659. * @priv: staging_rxon is compared to active_rxon
  660. *
  661. * If the RXON structure is changing enough to require a new tune,
  662. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  663. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  664. */
  665. static int iwl3945_full_rxon_required(struct iwl_priv *priv)
  666. {
  667. /* These items are only settable from the full RXON command */
  668. if (!(iwl3945_is_associated(priv)) ||
  669. compare_ether_addr(priv->staging39_rxon.bssid_addr,
  670. priv->active39_rxon.bssid_addr) ||
  671. compare_ether_addr(priv->staging39_rxon.node_addr,
  672. priv->active39_rxon.node_addr) ||
  673. compare_ether_addr(priv->staging39_rxon.wlap_bssid_addr,
  674. priv->active39_rxon.wlap_bssid_addr) ||
  675. (priv->staging39_rxon.dev_type != priv->active39_rxon.dev_type) ||
  676. (priv->staging39_rxon.channel != priv->active39_rxon.channel) ||
  677. (priv->staging39_rxon.air_propagation !=
  678. priv->active39_rxon.air_propagation) ||
  679. (priv->staging39_rxon.assoc_id != priv->active39_rxon.assoc_id))
  680. return 1;
  681. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  682. * be updated with the RXON_ASSOC command -- however only some
  683. * flag transitions are allowed using RXON_ASSOC */
  684. /* Check if we are not switching bands */
  685. if ((priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  686. (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK))
  687. return 1;
  688. /* Check if we are switching association toggle */
  689. if ((priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  690. (priv->active39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  691. return 1;
  692. return 0;
  693. }
  694. static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
  695. {
  696. int rc = 0;
  697. struct iwl_rx_packet *res = NULL;
  698. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  699. struct iwl_host_cmd cmd = {
  700. .id = REPLY_RXON_ASSOC,
  701. .len = sizeof(rxon_assoc),
  702. .meta.flags = CMD_WANT_SKB,
  703. .data = &rxon_assoc,
  704. };
  705. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging39_rxon;
  706. const struct iwl3945_rxon_cmd *rxon2 = &priv->active39_rxon;
  707. if ((rxon1->flags == rxon2->flags) &&
  708. (rxon1->filter_flags == rxon2->filter_flags) &&
  709. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  710. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  711. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  712. return 0;
  713. }
  714. rxon_assoc.flags = priv->staging39_rxon.flags;
  715. rxon_assoc.filter_flags = priv->staging39_rxon.filter_flags;
  716. rxon_assoc.ofdm_basic_rates = priv->staging39_rxon.ofdm_basic_rates;
  717. rxon_assoc.cck_basic_rates = priv->staging39_rxon.cck_basic_rates;
  718. rxon_assoc.reserved = 0;
  719. rc = iwl3945_send_cmd_sync(priv, &cmd);
  720. if (rc)
  721. return rc;
  722. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  723. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  724. IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
  725. rc = -EIO;
  726. }
  727. priv->alloc_rxb_skb--;
  728. dev_kfree_skb_any(cmd.meta.u.skb);
  729. return rc;
  730. }
  731. /**
  732. * iwl3945_commit_rxon - commit staging_rxon to hardware
  733. *
  734. * The RXON command in staging_rxon is committed to the hardware and
  735. * the active_rxon structure is updated with the new data. This
  736. * function correctly transitions out of the RXON_ASSOC_MSK state if
  737. * a HW tune is required based on the RXON structure changes.
  738. */
  739. static int iwl3945_commit_rxon(struct iwl_priv *priv)
  740. {
  741. /* cast away the const for active_rxon in this function */
  742. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active39_rxon;
  743. int rc = 0;
  744. if (!iwl_is_alive(priv))
  745. return -1;
  746. /* always get timestamp with Rx frame */
  747. priv->staging39_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  748. /* select antenna */
  749. priv->staging39_rxon.flags &=
  750. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  751. priv->staging39_rxon.flags |= iwl3945_get_antenna_flags(priv);
  752. rc = iwl3945_check_rxon_cmd(priv);
  753. if (rc) {
  754. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  755. return -EINVAL;
  756. }
  757. /* If we don't need to send a full RXON, we can use
  758. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  759. * and other flags for the current radio configuration. */
  760. if (!iwl3945_full_rxon_required(priv)) {
  761. rc = iwl3945_send_rxon_assoc(priv);
  762. if (rc) {
  763. IWL_ERR(priv, "Error setting RXON_ASSOC "
  764. "configuration (%d).\n", rc);
  765. return rc;
  766. }
  767. memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
  768. return 0;
  769. }
  770. /* If we are currently associated and the new config requires
  771. * an RXON_ASSOC and the new config wants the associated mask enabled,
  772. * we must clear the associated from the active configuration
  773. * before we apply the new config */
  774. if (iwl3945_is_associated(priv) &&
  775. (priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  776. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  777. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  778. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  779. sizeof(struct iwl3945_rxon_cmd),
  780. &priv->active39_rxon);
  781. /* If the mask clearing failed then we set
  782. * active_rxon back to what it was previously */
  783. if (rc) {
  784. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  785. IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
  786. "configuration (%d).\n", rc);
  787. return rc;
  788. }
  789. }
  790. IWL_DEBUG_INFO("Sending RXON\n"
  791. "* with%s RXON_FILTER_ASSOC_MSK\n"
  792. "* channel = %d\n"
  793. "* bssid = %pM\n",
  794. ((priv->staging39_rxon.filter_flags &
  795. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  796. le16_to_cpu(priv->staging39_rxon.channel),
  797. priv->staging_rxon.bssid_addr);
  798. /* Apply the new configuration */
  799. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  800. sizeof(struct iwl3945_rxon_cmd), &priv->staging39_rxon);
  801. if (rc) {
  802. IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
  803. return rc;
  804. }
  805. memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
  806. iwl3945_clear_stations_table(priv);
  807. /* If we issue a new RXON command which required a tune then we must
  808. * send a new TXPOWER command or we won't be able to Tx any frames */
  809. rc = iwl3945_hw_reg_send_txpower(priv);
  810. if (rc) {
  811. IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
  812. return rc;
  813. }
  814. /* Add the broadcast address so we can send broadcast frames */
  815. if (iwl3945_add_station(priv, iwl_bcast_addr, 0, 0) ==
  816. IWL_INVALID_STATION) {
  817. IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
  818. return -EIO;
  819. }
  820. /* If we have set the ASSOC_MSK and we are in BSS mode then
  821. * add the IWL_AP_ID to the station rate table */
  822. if (iwl3945_is_associated(priv) &&
  823. (priv->iw_mode == NL80211_IFTYPE_STATION))
  824. if (iwl3945_add_station(priv, priv->active39_rxon.bssid_addr, 1, 0)
  825. == IWL_INVALID_STATION) {
  826. IWL_ERR(priv, "Error adding AP address for transmit\n");
  827. return -EIO;
  828. }
  829. /* Init the hardware's rate fallback order based on the band */
  830. rc = iwl3945_init_hw_rate_table(priv);
  831. if (rc) {
  832. IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
  833. return -EIO;
  834. }
  835. return 0;
  836. }
  837. static int iwl3945_send_bt_config(struct iwl_priv *priv)
  838. {
  839. struct iwl_bt_cmd bt_cmd = {
  840. .flags = 3,
  841. .lead_time = 0xAA,
  842. .max_kill = 1,
  843. .kill_ack_mask = 0,
  844. .kill_cts_mask = 0,
  845. };
  846. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  847. sizeof(bt_cmd), &bt_cmd);
  848. }
  849. static int iwl3945_send_scan_abort(struct iwl_priv *priv)
  850. {
  851. int rc = 0;
  852. struct iwl_rx_packet *res;
  853. struct iwl_host_cmd cmd = {
  854. .id = REPLY_SCAN_ABORT_CMD,
  855. .meta.flags = CMD_WANT_SKB,
  856. };
  857. /* If there isn't a scan actively going on in the hardware
  858. * then we are in between scan bands and not actually
  859. * actively scanning, so don't send the abort command */
  860. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  861. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  862. return 0;
  863. }
  864. rc = iwl3945_send_cmd_sync(priv, &cmd);
  865. if (rc) {
  866. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  867. return rc;
  868. }
  869. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  870. if (res->u.status != CAN_ABORT_STATUS) {
  871. /* The scan abort will return 1 for success or
  872. * 2 for "failure". A failure condition can be
  873. * due to simply not being in an active scan which
  874. * can occur if we send the scan abort before we
  875. * the microcode has notified us that a scan is
  876. * completed. */
  877. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  878. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  879. clear_bit(STATUS_SCAN_HW, &priv->status);
  880. }
  881. dev_kfree_skb_any(cmd.meta.u.skb);
  882. return rc;
  883. }
  884. static int iwl3945_card_state_sync_callback(struct iwl_priv *priv,
  885. struct iwl_cmd *cmd,
  886. struct sk_buff *skb)
  887. {
  888. return 1;
  889. }
  890. /*
  891. * CARD_STATE_CMD
  892. *
  893. * Use: Sets the device's internal card state to enable, disable, or halt
  894. *
  895. * When in the 'enable' state the card operates as normal.
  896. * When in the 'disable' state, the card enters into a low power mode.
  897. * When in the 'halt' state, the card is shut down and must be fully
  898. * restarted to come back on.
  899. */
  900. static int iwl3945_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
  901. {
  902. struct iwl_host_cmd cmd = {
  903. .id = REPLY_CARD_STATE_CMD,
  904. .len = sizeof(u32),
  905. .data = &flags,
  906. .meta.flags = meta_flag,
  907. };
  908. if (meta_flag & CMD_ASYNC)
  909. cmd.meta.u.callback = iwl3945_card_state_sync_callback;
  910. return iwl3945_send_cmd(priv, &cmd);
  911. }
  912. static int iwl3945_add_sta_sync_callback(struct iwl_priv *priv,
  913. struct iwl_cmd *cmd, struct sk_buff *skb)
  914. {
  915. struct iwl_rx_packet *res = NULL;
  916. if (!skb) {
  917. IWL_ERR(priv, "Error: Response NULL in REPLY_ADD_STA.\n");
  918. return 1;
  919. }
  920. res = (struct iwl_rx_packet *)skb->data;
  921. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  922. IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n",
  923. res->hdr.flags);
  924. return 1;
  925. }
  926. switch (res->u.add_sta.status) {
  927. case ADD_STA_SUCCESS_MSK:
  928. break;
  929. default:
  930. break;
  931. }
  932. /* We didn't cache the SKB; let the caller free it */
  933. return 1;
  934. }
  935. int iwl3945_send_add_station(struct iwl_priv *priv,
  936. struct iwl3945_addsta_cmd *sta, u8 flags)
  937. {
  938. struct iwl_rx_packet *res = NULL;
  939. int rc = 0;
  940. struct iwl_host_cmd cmd = {
  941. .id = REPLY_ADD_STA,
  942. .len = sizeof(struct iwl3945_addsta_cmd),
  943. .meta.flags = flags,
  944. .data = sta,
  945. };
  946. if (flags & CMD_ASYNC)
  947. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  948. else
  949. cmd.meta.flags |= CMD_WANT_SKB;
  950. rc = iwl3945_send_cmd(priv, &cmd);
  951. if (rc || (flags & CMD_ASYNC))
  952. return rc;
  953. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  954. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  955. IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n",
  956. res->hdr.flags);
  957. rc = -EIO;
  958. }
  959. if (rc == 0) {
  960. switch (res->u.add_sta.status) {
  961. case ADD_STA_SUCCESS_MSK:
  962. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  963. break;
  964. default:
  965. rc = -EIO;
  966. IWL_WARN(priv, "REPLY_ADD_STA failed\n");
  967. break;
  968. }
  969. }
  970. priv->alloc_rxb_skb--;
  971. dev_kfree_skb_any(cmd.meta.u.skb);
  972. return rc;
  973. }
  974. static int iwl3945_update_sta_key_info(struct iwl_priv *priv,
  975. struct ieee80211_key_conf *keyconf,
  976. u8 sta_id)
  977. {
  978. unsigned long flags;
  979. __le16 key_flags = 0;
  980. switch (keyconf->alg) {
  981. case ALG_CCMP:
  982. key_flags |= STA_KEY_FLG_CCMP;
  983. key_flags |= cpu_to_le16(
  984. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  985. key_flags &= ~STA_KEY_FLG_INVALID;
  986. break;
  987. case ALG_TKIP:
  988. case ALG_WEP:
  989. default:
  990. return -EINVAL;
  991. }
  992. spin_lock_irqsave(&priv->sta_lock, flags);
  993. priv->stations_39[sta_id].keyinfo.alg = keyconf->alg;
  994. priv->stations_39[sta_id].keyinfo.keylen = keyconf->keylen;
  995. memcpy(priv->stations_39[sta_id].keyinfo.key, keyconf->key,
  996. keyconf->keylen);
  997. memcpy(priv->stations_39[sta_id].sta.key.key, keyconf->key,
  998. keyconf->keylen);
  999. priv->stations_39[sta_id].sta.key.key_flags = key_flags;
  1000. priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1001. priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1002. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1003. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1004. iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
  1005. return 0;
  1006. }
  1007. static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
  1008. {
  1009. unsigned long flags;
  1010. spin_lock_irqsave(&priv->sta_lock, flags);
  1011. memset(&priv->stations_39[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1012. memset(&priv->stations_39[sta_id].sta.key, 0,
  1013. sizeof(struct iwl4965_keyinfo));
  1014. priv->stations_39[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1015. priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1016. priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1017. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1018. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1019. iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
  1020. return 0;
  1021. }
  1022. static void iwl3945_clear_free_frames(struct iwl_priv *priv)
  1023. {
  1024. struct list_head *element;
  1025. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1026. priv->frames_count);
  1027. while (!list_empty(&priv->free_frames)) {
  1028. element = priv->free_frames.next;
  1029. list_del(element);
  1030. kfree(list_entry(element, struct iwl3945_frame, list));
  1031. priv->frames_count--;
  1032. }
  1033. if (priv->frames_count) {
  1034. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  1035. priv->frames_count);
  1036. priv->frames_count = 0;
  1037. }
  1038. }
  1039. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
  1040. {
  1041. struct iwl3945_frame *frame;
  1042. struct list_head *element;
  1043. if (list_empty(&priv->free_frames)) {
  1044. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1045. if (!frame) {
  1046. IWL_ERR(priv, "Could not allocate frame!\n");
  1047. return NULL;
  1048. }
  1049. priv->frames_count++;
  1050. return frame;
  1051. }
  1052. element = priv->free_frames.next;
  1053. list_del(element);
  1054. return list_entry(element, struct iwl3945_frame, list);
  1055. }
  1056. static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
  1057. {
  1058. memset(frame, 0, sizeof(*frame));
  1059. list_add(&frame->list, &priv->free_frames);
  1060. }
  1061. unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
  1062. struct ieee80211_hdr *hdr,
  1063. int left)
  1064. {
  1065. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1066. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  1067. (priv->iw_mode != NL80211_IFTYPE_AP)))
  1068. return 0;
  1069. if (priv->ibss_beacon->len > left)
  1070. return 0;
  1071. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1072. return priv->ibss_beacon->len;
  1073. }
  1074. static u8 iwl3945_rate_get_lowest_plcp(struct iwl_priv *priv)
  1075. {
  1076. u8 i;
  1077. int rate_mask;
  1078. /* Set rate mask*/
  1079. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1080. rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
  1081. else
  1082. rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
  1083. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1084. i = iwl3945_rates[i].next_ieee) {
  1085. if (rate_mask & (1 << i))
  1086. return iwl3945_rates[i].plcp;
  1087. }
  1088. /* No valid rate was found. Assign the lowest one */
  1089. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1090. return IWL_RATE_1M_PLCP;
  1091. else
  1092. return IWL_RATE_6M_PLCP;
  1093. }
  1094. static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
  1095. {
  1096. struct iwl3945_frame *frame;
  1097. unsigned int frame_size;
  1098. int rc;
  1099. u8 rate;
  1100. frame = iwl3945_get_free_frame(priv);
  1101. if (!frame) {
  1102. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  1103. "command.\n");
  1104. return -ENOMEM;
  1105. }
  1106. rate = iwl3945_rate_get_lowest_plcp(priv);
  1107. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1108. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1109. &frame->u.cmd[0]);
  1110. iwl3945_free_frame(priv, frame);
  1111. return rc;
  1112. }
  1113. /******************************************************************************
  1114. *
  1115. * EEPROM related functions
  1116. *
  1117. ******************************************************************************/
  1118. static void get_eeprom_mac(struct iwl_priv *priv, u8 *mac)
  1119. {
  1120. memcpy(mac, priv->eeprom39.mac_address, 6);
  1121. }
  1122. /*
  1123. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1124. * embedded controller) as EEPROM reader; each read is a series of pulses
  1125. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1126. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1127. * simply claims ownership, which should be safe when this function is called
  1128. * (i.e. before loading uCode!).
  1129. */
  1130. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
  1131. {
  1132. _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1133. return 0;
  1134. }
  1135. /**
  1136. * iwl3945_eeprom_init - read EEPROM contents
  1137. *
  1138. * Load the EEPROM contents from adapter into priv->eeprom39
  1139. *
  1140. * NOTE: This routine uses the non-debug IO access functions.
  1141. */
  1142. int iwl3945_eeprom_init(struct iwl_priv *priv)
  1143. {
  1144. u16 *e = (u16 *)&priv->eeprom39;
  1145. u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
  1146. int sz = sizeof(priv->eeprom39);
  1147. int ret;
  1148. u16 addr;
  1149. /* The EEPROM structure has several padding buffers within it
  1150. * and when adding new EEPROM maps is subject to programmer errors
  1151. * which may be very difficult to identify without explicitly
  1152. * checking the resulting size of the eeprom map. */
  1153. BUILD_BUG_ON(sizeof(priv->eeprom39) != IWL_EEPROM_IMAGE_SIZE);
  1154. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1155. IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
  1156. return -ENOENT;
  1157. }
  1158. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1159. ret = iwl3945_eeprom_acquire_semaphore(priv);
  1160. if (ret < 0) {
  1161. IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n");
  1162. return -ENOENT;
  1163. }
  1164. /* eeprom is an array of 16bit values */
  1165. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1166. u32 r;
  1167. _iwl_write32(priv, CSR_EEPROM_REG,
  1168. CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
  1169. _iwl_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1170. ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG,
  1171. CSR_EEPROM_REG_READ_VALID_MSK,
  1172. IWL_EEPROM_ACCESS_TIMEOUT);
  1173. if (ret < 0) {
  1174. IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
  1175. return ret;
  1176. }
  1177. r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
  1178. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1179. }
  1180. return 0;
  1181. }
  1182. static void iwl3945_unset_hw_params(struct iwl_priv *priv)
  1183. {
  1184. if (priv->shared_virt)
  1185. pci_free_consistent(priv->pci_dev,
  1186. sizeof(struct iwl3945_shared),
  1187. priv->shared_virt,
  1188. priv->shared_phys);
  1189. }
  1190. /**
  1191. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1192. *
  1193. * return : set the bit for each supported rate insert in ie
  1194. */
  1195. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1196. u16 basic_rate, int *left)
  1197. {
  1198. u16 ret_rates = 0, bit;
  1199. int i;
  1200. u8 *cnt = ie;
  1201. u8 *rates = ie + 1;
  1202. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1203. if (bit & supported_rate) {
  1204. ret_rates |= bit;
  1205. rates[*cnt] = iwl3945_rates[i].ieee |
  1206. ((bit & basic_rate) ? 0x80 : 0x00);
  1207. (*cnt)++;
  1208. (*left)--;
  1209. if ((*left <= 0) ||
  1210. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1211. break;
  1212. }
  1213. }
  1214. return ret_rates;
  1215. }
  1216. /**
  1217. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1218. */
  1219. static u16 iwl3945_fill_probe_req(struct iwl_priv *priv,
  1220. struct ieee80211_mgmt *frame,
  1221. int left)
  1222. {
  1223. int len = 0;
  1224. u8 *pos = NULL;
  1225. u16 active_rates, ret_rates, cck_rates;
  1226. /* Make sure there is enough space for the probe request,
  1227. * two mandatory IEs and the data */
  1228. left -= 24;
  1229. if (left < 0)
  1230. return 0;
  1231. len += 24;
  1232. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1233. memcpy(frame->da, iwl_bcast_addr, ETH_ALEN);
  1234. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1235. memcpy(frame->bssid, iwl_bcast_addr, ETH_ALEN);
  1236. frame->seq_ctrl = 0;
  1237. /* fill in our indirect SSID IE */
  1238. /* ...next IE... */
  1239. left -= 2;
  1240. if (left < 0)
  1241. return 0;
  1242. len += 2;
  1243. pos = &(frame->u.probe_req.variable[0]);
  1244. *pos++ = WLAN_EID_SSID;
  1245. *pos++ = 0;
  1246. /* fill in supported rate */
  1247. /* ...next IE... */
  1248. left -= 2;
  1249. if (left < 0)
  1250. return 0;
  1251. /* ... fill it in... */
  1252. *pos++ = WLAN_EID_SUPP_RATES;
  1253. *pos = 0;
  1254. priv->active_rate = priv->rates_mask;
  1255. active_rates = priv->active_rate;
  1256. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1257. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1258. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1259. priv->active_rate_basic, &left);
  1260. active_rates &= ~ret_rates;
  1261. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1262. priv->active_rate_basic, &left);
  1263. active_rates &= ~ret_rates;
  1264. len += 2 + *pos;
  1265. pos += (*pos) + 1;
  1266. if (active_rates == 0)
  1267. goto fill_end;
  1268. /* fill in supported extended rate */
  1269. /* ...next IE... */
  1270. left -= 2;
  1271. if (left < 0)
  1272. return 0;
  1273. /* ... fill it in... */
  1274. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1275. *pos = 0;
  1276. iwl3945_supported_rate_to_ie(pos, active_rates,
  1277. priv->active_rate_basic, &left);
  1278. if (*pos > 0)
  1279. len += 2 + *pos;
  1280. fill_end:
  1281. return (u16)len;
  1282. }
  1283. /*
  1284. * QoS support
  1285. */
  1286. static int iwl3945_send_qos_params_command(struct iwl_priv *priv,
  1287. struct iwl_qosparam_cmd *qos)
  1288. {
  1289. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1290. sizeof(struct iwl_qosparam_cmd), qos);
  1291. }
  1292. static void iwl3945_activate_qos(struct iwl_priv *priv, u8 force)
  1293. {
  1294. unsigned long flags;
  1295. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1296. return;
  1297. spin_lock_irqsave(&priv->lock, flags);
  1298. priv->qos_data.def_qos_parm.qos_flags = 0;
  1299. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1300. !priv->qos_data.qos_cap.q_AP.txop_request)
  1301. priv->qos_data.def_qos_parm.qos_flags |=
  1302. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1303. if (priv->qos_data.qos_active)
  1304. priv->qos_data.def_qos_parm.qos_flags |=
  1305. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1306. spin_unlock_irqrestore(&priv->lock, flags);
  1307. if (force || iwl3945_is_associated(priv)) {
  1308. IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n",
  1309. priv->qos_data.qos_active);
  1310. iwl3945_send_qos_params_command(priv,
  1311. &(priv->qos_data.def_qos_parm));
  1312. }
  1313. }
  1314. /*
  1315. * Power management (not Tx power!) functions
  1316. */
  1317. #define MSEC_TO_USEC 1024
  1318. #define NOSLP __constant_cpu_to_le16(0), 0, 0
  1319. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
  1320. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1321. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1322. __constant_cpu_to_le32(X1), \
  1323. __constant_cpu_to_le32(X2), \
  1324. __constant_cpu_to_le32(X3), \
  1325. __constant_cpu_to_le32(X4)}
  1326. /* default power management (not Tx power) table values */
  1327. /* for TIM 0-10 */
  1328. static struct iwl_power_vec_entry range_0[IWL39_POWER_AC] = {
  1329. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1330. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1331. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1332. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1333. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1334. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1335. };
  1336. /* for TIM > 10 */
  1337. static struct iwl_power_vec_entry range_1[IWL39_POWER_AC] = {
  1338. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1339. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1340. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1341. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1342. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1343. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1344. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1345. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1346. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1347. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1348. };
  1349. int iwl3945_power_init_handle(struct iwl_priv *priv)
  1350. {
  1351. int rc = 0, i;
  1352. struct iwl3945_power_mgr *pow_data;
  1353. int size = sizeof(struct iwl_power_vec_entry) * IWL39_POWER_AC;
  1354. u16 pci_pm;
  1355. IWL_DEBUG_POWER("Initialize power \n");
  1356. pow_data = &(priv->power_data_39);
  1357. memset(pow_data, 0, sizeof(*pow_data));
  1358. pow_data->active_index = IWL_POWER_RANGE_0;
  1359. pow_data->dtim_val = 0xffff;
  1360. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1361. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1362. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1363. if (rc != 0)
  1364. return 0;
  1365. else {
  1366. struct iwl_powertable_cmd *cmd;
  1367. IWL_DEBUG_POWER("adjust power command flags\n");
  1368. for (i = 0; i < IWL39_POWER_AC; i++) {
  1369. cmd = &pow_data->pwr_range_0[i].cmd;
  1370. if (pci_pm & 0x1)
  1371. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1372. else
  1373. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1374. }
  1375. }
  1376. return rc;
  1377. }
  1378. static int iwl3945_update_power_cmd(struct iwl_priv *priv,
  1379. struct iwl_powertable_cmd *cmd, u32 mode)
  1380. {
  1381. int rc = 0, i;
  1382. u8 skip;
  1383. u32 max_sleep = 0;
  1384. struct iwl_power_vec_entry *range;
  1385. u8 period = 0;
  1386. struct iwl3945_power_mgr *pow_data;
  1387. if (mode > IWL_POWER_INDEX_5) {
  1388. IWL_DEBUG_POWER("Error invalid power mode \n");
  1389. return -1;
  1390. }
  1391. pow_data = &(priv->power_data_39);
  1392. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1393. range = &pow_data->pwr_range_0[0];
  1394. else
  1395. range = &pow_data->pwr_range_1[1];
  1396. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1397. #ifdef IWL_MAC80211_DISABLE
  1398. if (priv->assoc_network != NULL) {
  1399. unsigned long flags;
  1400. period = priv->assoc_network->tim.tim_period;
  1401. }
  1402. #endif /*IWL_MAC80211_DISABLE */
  1403. skip = range[mode].no_dtim;
  1404. if (period == 0) {
  1405. period = 1;
  1406. skip = 0;
  1407. }
  1408. if (skip == 0) {
  1409. max_sleep = period;
  1410. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1411. } else {
  1412. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1413. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1414. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1415. }
  1416. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1417. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1418. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1419. }
  1420. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1421. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1422. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1423. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1424. le32_to_cpu(cmd->sleep_interval[0]),
  1425. le32_to_cpu(cmd->sleep_interval[1]),
  1426. le32_to_cpu(cmd->sleep_interval[2]),
  1427. le32_to_cpu(cmd->sleep_interval[3]),
  1428. le32_to_cpu(cmd->sleep_interval[4]));
  1429. return rc;
  1430. }
  1431. static int iwl3945_send_power_mode(struct iwl_priv *priv, u32 mode)
  1432. {
  1433. u32 uninitialized_var(final_mode);
  1434. int rc;
  1435. struct iwl_powertable_cmd cmd;
  1436. /* If on battery, set to 3,
  1437. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1438. * else user level */
  1439. switch (mode) {
  1440. case IWL39_POWER_BATTERY:
  1441. final_mode = IWL_POWER_INDEX_3;
  1442. break;
  1443. case IWL39_POWER_AC:
  1444. final_mode = IWL_POWER_MODE_CAM;
  1445. break;
  1446. default:
  1447. final_mode = mode;
  1448. break;
  1449. }
  1450. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1451. /* FIXME use get_hcmd_size 3945 command is 4 bytes shorter */
  1452. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD,
  1453. sizeof(struct iwl3945_powertable_cmd), &cmd);
  1454. if (final_mode == IWL_POWER_MODE_CAM)
  1455. clear_bit(STATUS_POWER_PMI, &priv->status);
  1456. else
  1457. set_bit(STATUS_POWER_PMI, &priv->status);
  1458. return rc;
  1459. }
  1460. /**
  1461. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1462. *
  1463. * NOTE: priv->mutex is not required before calling this function
  1464. */
  1465. static int iwl3945_scan_cancel(struct iwl_priv *priv)
  1466. {
  1467. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1468. clear_bit(STATUS_SCANNING, &priv->status);
  1469. return 0;
  1470. }
  1471. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1472. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1473. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1474. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1475. queue_work(priv->workqueue, &priv->abort_scan);
  1476. } else
  1477. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1478. return test_bit(STATUS_SCANNING, &priv->status);
  1479. }
  1480. return 0;
  1481. }
  1482. /**
  1483. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1484. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1485. *
  1486. * NOTE: priv->mutex must be held before calling this function
  1487. */
  1488. static int iwl3945_scan_cancel_timeout(struct iwl_priv *priv, unsigned long ms)
  1489. {
  1490. unsigned long now = jiffies;
  1491. int ret;
  1492. ret = iwl3945_scan_cancel(priv);
  1493. if (ret && ms) {
  1494. mutex_unlock(&priv->mutex);
  1495. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1496. test_bit(STATUS_SCANNING, &priv->status))
  1497. msleep(1);
  1498. mutex_lock(&priv->mutex);
  1499. return test_bit(STATUS_SCANNING, &priv->status);
  1500. }
  1501. return ret;
  1502. }
  1503. #define MAX_UCODE_BEACON_INTERVAL 1024
  1504. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1505. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1506. {
  1507. u16 new_val = 0;
  1508. u16 beacon_factor = 0;
  1509. beacon_factor =
  1510. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1511. / MAX_UCODE_BEACON_INTERVAL;
  1512. new_val = beacon_val / beacon_factor;
  1513. return cpu_to_le16(new_val);
  1514. }
  1515. static void iwl3945_setup_rxon_timing(struct iwl_priv *priv)
  1516. {
  1517. u64 interval_tm_unit;
  1518. u64 tsf, result;
  1519. unsigned long flags;
  1520. struct ieee80211_conf *conf = NULL;
  1521. u16 beacon_int = 0;
  1522. conf = ieee80211_get_hw_conf(priv->hw);
  1523. spin_lock_irqsave(&priv->lock, flags);
  1524. priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
  1525. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1526. tsf = priv->timestamp;
  1527. beacon_int = priv->beacon_int;
  1528. spin_unlock_irqrestore(&priv->lock, flags);
  1529. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  1530. if (beacon_int == 0) {
  1531. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1532. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1533. } else {
  1534. priv->rxon_timing.beacon_interval =
  1535. cpu_to_le16(beacon_int);
  1536. priv->rxon_timing.beacon_interval =
  1537. iwl3945_adjust_beacon_interval(
  1538. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1539. }
  1540. priv->rxon_timing.atim_window = 0;
  1541. } else {
  1542. priv->rxon_timing.beacon_interval =
  1543. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1544. /* TODO: we need to get atim_window from upper stack
  1545. * for now we set to 0 */
  1546. priv->rxon_timing.atim_window = 0;
  1547. }
  1548. interval_tm_unit =
  1549. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1550. result = do_div(tsf, interval_tm_unit);
  1551. priv->rxon_timing.beacon_init_val =
  1552. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1553. IWL_DEBUG_ASSOC
  1554. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1555. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1556. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1557. le16_to_cpu(priv->rxon_timing.atim_window));
  1558. }
  1559. static int iwl3945_scan_initiate(struct iwl_priv *priv)
  1560. {
  1561. if (!iwl_is_ready_rf(priv)) {
  1562. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1563. return -EIO;
  1564. }
  1565. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1566. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1567. return -EAGAIN;
  1568. }
  1569. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1570. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1571. "Queuing.\n");
  1572. return -EAGAIN;
  1573. }
  1574. IWL_DEBUG_INFO("Starting scan...\n");
  1575. if (priv->cfg->sku & IWL_SKU_G)
  1576. priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
  1577. if (priv->cfg->sku & IWL_SKU_A)
  1578. priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
  1579. set_bit(STATUS_SCANNING, &priv->status);
  1580. priv->scan_start = jiffies;
  1581. priv->scan_pass_start = priv->scan_start;
  1582. queue_work(priv->workqueue, &priv->request_scan);
  1583. return 0;
  1584. }
  1585. static int iwl3945_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
  1586. {
  1587. struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
  1588. if (hw_decrypt)
  1589. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  1590. else
  1591. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  1592. return 0;
  1593. }
  1594. static void iwl3945_set_flags_for_phymode(struct iwl_priv *priv,
  1595. enum ieee80211_band band)
  1596. {
  1597. if (band == IEEE80211_BAND_5GHZ) {
  1598. priv->staging39_rxon.flags &=
  1599. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1600. | RXON_FLG_CCK_MSK);
  1601. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1602. } else {
  1603. /* Copied from iwl3945_bg_post_associate() */
  1604. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1605. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1606. else
  1607. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1608. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1609. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1610. priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1611. priv->staging39_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1612. priv->staging39_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1613. }
  1614. }
  1615. /*
  1616. * initialize rxon structure with default values from eeprom
  1617. */
  1618. static void iwl3945_connection_init_rx_config(struct iwl_priv *priv,
  1619. int mode)
  1620. {
  1621. const struct iwl_channel_info *ch_info;
  1622. memset(&priv->staging39_rxon, 0, sizeof(priv->staging39_rxon));
  1623. switch (mode) {
  1624. case NL80211_IFTYPE_AP:
  1625. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_AP;
  1626. break;
  1627. case NL80211_IFTYPE_STATION:
  1628. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1629. priv->staging39_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1630. break;
  1631. case NL80211_IFTYPE_ADHOC:
  1632. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1633. priv->staging39_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1634. priv->staging39_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1635. RXON_FILTER_ACCEPT_GRP_MSK;
  1636. break;
  1637. case NL80211_IFTYPE_MONITOR:
  1638. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  1639. priv->staging39_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  1640. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  1641. break;
  1642. default:
  1643. IWL_ERR(priv, "Unsupported interface type %d\n", mode);
  1644. break;
  1645. }
  1646. #if 0
  1647. /* TODO: Figure out when short_preamble would be set and cache from
  1648. * that */
  1649. if (!hw_to_local(priv->hw)->short_preamble)
  1650. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1651. else
  1652. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1653. #endif
  1654. ch_info = iwl3945_get_channel_info(priv, priv->band,
  1655. le16_to_cpu(priv->active39_rxon.channel));
  1656. if (!ch_info)
  1657. ch_info = &priv->channel_info[0];
  1658. /*
  1659. * in some case A channels are all non IBSS
  1660. * in this case force B/G channel
  1661. */
  1662. if ((mode == NL80211_IFTYPE_ADHOC) && !(is_channel_ibss(ch_info)))
  1663. ch_info = &priv->channel_info[0];
  1664. priv->staging39_rxon.channel = cpu_to_le16(ch_info->channel);
  1665. if (is_channel_a_band(ch_info))
  1666. priv->band = IEEE80211_BAND_5GHZ;
  1667. else
  1668. priv->band = IEEE80211_BAND_2GHZ;
  1669. iwl3945_set_flags_for_phymode(priv, priv->band);
  1670. priv->staging39_rxon.ofdm_basic_rates =
  1671. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1672. priv->staging39_rxon.cck_basic_rates =
  1673. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1674. }
  1675. static int iwl3945_set_mode(struct iwl_priv *priv, int mode)
  1676. {
  1677. if (mode == NL80211_IFTYPE_ADHOC) {
  1678. const struct iwl_channel_info *ch_info;
  1679. ch_info = iwl3945_get_channel_info(priv,
  1680. priv->band,
  1681. le16_to_cpu(priv->staging39_rxon.channel));
  1682. if (!ch_info || !is_channel_ibss(ch_info)) {
  1683. IWL_ERR(priv, "channel %d not IBSS channel\n",
  1684. le16_to_cpu(priv->staging39_rxon.channel));
  1685. return -EINVAL;
  1686. }
  1687. }
  1688. iwl3945_connection_init_rx_config(priv, mode);
  1689. memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1690. iwl3945_clear_stations_table(priv);
  1691. /* don't commit rxon if rf-kill is on*/
  1692. if (!iwl_is_ready_rf(priv))
  1693. return -EAGAIN;
  1694. cancel_delayed_work(&priv->scan_check);
  1695. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  1696. IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
  1697. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  1698. return -EAGAIN;
  1699. }
  1700. iwl3945_commit_rxon(priv);
  1701. return 0;
  1702. }
  1703. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
  1704. struct ieee80211_tx_info *info,
  1705. struct iwl_cmd *cmd,
  1706. struct sk_buff *skb_frag,
  1707. int last_frag)
  1708. {
  1709. struct iwl3945_hw_key *keyinfo =
  1710. &priv->stations_39[info->control.hw_key->hw_key_idx].keyinfo;
  1711. switch (keyinfo->alg) {
  1712. case ALG_CCMP:
  1713. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  1714. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  1715. IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
  1716. break;
  1717. case ALG_TKIP:
  1718. #if 0
  1719. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  1720. if (last_frag)
  1721. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  1722. 8);
  1723. else
  1724. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  1725. #endif
  1726. break;
  1727. case ALG_WEP:
  1728. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  1729. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  1730. if (keyinfo->keylen == 13)
  1731. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  1732. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  1733. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  1734. "with key %d\n", info->control.hw_key->hw_key_idx);
  1735. break;
  1736. default:
  1737. IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
  1738. break;
  1739. }
  1740. }
  1741. /*
  1742. * handle build REPLY_TX command notification.
  1743. */
  1744. static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
  1745. struct iwl_cmd *cmd,
  1746. struct ieee80211_tx_info *info,
  1747. struct ieee80211_hdr *hdr,
  1748. int is_unicast, u8 std_id)
  1749. {
  1750. __le16 fc = hdr->frame_control;
  1751. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  1752. u8 rc_flags = info->control.rates[0].flags;
  1753. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  1754. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  1755. tx_flags |= TX_CMD_FLG_ACK_MSK;
  1756. if (ieee80211_is_mgmt(fc))
  1757. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1758. if (ieee80211_is_probe_resp(fc) &&
  1759. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  1760. tx_flags |= TX_CMD_FLG_TSF_MSK;
  1761. } else {
  1762. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  1763. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1764. }
  1765. cmd->cmd.tx.sta_id = std_id;
  1766. if (ieee80211_has_morefrags(fc))
  1767. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  1768. if (ieee80211_is_data_qos(fc)) {
  1769. u8 *qc = ieee80211_get_qos_ctl(hdr);
  1770. cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
  1771. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  1772. } else {
  1773. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1774. }
  1775. if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  1776. tx_flags |= TX_CMD_FLG_RTS_MSK;
  1777. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  1778. } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  1779. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  1780. tx_flags |= TX_CMD_FLG_CTS_MSK;
  1781. }
  1782. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  1783. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  1784. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  1785. if (ieee80211_is_mgmt(fc)) {
  1786. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  1787. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  1788. else
  1789. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  1790. } else {
  1791. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  1792. #ifdef CONFIG_IWL3945_LEDS
  1793. priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
  1794. #endif
  1795. }
  1796. cmd->cmd.tx.driver_txop = 0;
  1797. cmd->cmd.tx.tx_flags = tx_flags;
  1798. cmd->cmd.tx.next_frame_len = 0;
  1799. }
  1800. /**
  1801. * iwl3945_get_sta_id - Find station's index within station table
  1802. */
  1803. static int iwl3945_get_sta_id(struct iwl_priv *priv, struct ieee80211_hdr *hdr)
  1804. {
  1805. int sta_id;
  1806. u16 fc = le16_to_cpu(hdr->frame_control);
  1807. /* If this frame is broadcast or management, use broadcast station id */
  1808. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  1809. is_multicast_ether_addr(hdr->addr1))
  1810. return priv->hw_params.bcast_sta_id;
  1811. switch (priv->iw_mode) {
  1812. /* If we are a client station in a BSS network, use the special
  1813. * AP station entry (that's the only station we communicate with) */
  1814. case NL80211_IFTYPE_STATION:
  1815. return IWL_AP_ID;
  1816. /* If we are an AP, then find the station, or use BCAST */
  1817. case NL80211_IFTYPE_AP:
  1818. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  1819. if (sta_id != IWL_INVALID_STATION)
  1820. return sta_id;
  1821. return priv->hw_params.bcast_sta_id;
  1822. /* If this frame is going out to an IBSS network, find the station,
  1823. * or create a new station table entry */
  1824. case NL80211_IFTYPE_ADHOC: {
  1825. /* Create new station table entry */
  1826. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  1827. if (sta_id != IWL_INVALID_STATION)
  1828. return sta_id;
  1829. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  1830. if (sta_id != IWL_INVALID_STATION)
  1831. return sta_id;
  1832. IWL_DEBUG_DROP("Station %pM not in station map. "
  1833. "Defaulting to broadcast...\n",
  1834. hdr->addr1);
  1835. iwl_print_hex_dump(priv, IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  1836. return priv->hw_params.bcast_sta_id;
  1837. }
  1838. /* If we are in monitor mode, use BCAST. This is required for
  1839. * packet injection. */
  1840. case NL80211_IFTYPE_MONITOR:
  1841. return priv->hw_params.bcast_sta_id;
  1842. default:
  1843. IWL_WARN(priv, "Unknown mode of operation: %d\n",
  1844. priv->iw_mode);
  1845. return priv->hw_params.bcast_sta_id;
  1846. }
  1847. }
  1848. /*
  1849. * start REPLY_TX command process
  1850. */
  1851. static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
  1852. {
  1853. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1854. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1855. struct iwl3945_tfd_frame *tfd;
  1856. u32 *control_flags;
  1857. int txq_id = skb_get_queue_mapping(skb);
  1858. struct iwl3945_tx_queue *txq = NULL;
  1859. struct iwl_queue *q = NULL;
  1860. dma_addr_t phys_addr;
  1861. dma_addr_t txcmd_phys;
  1862. struct iwl_cmd *out_cmd = NULL;
  1863. u16 len, idx, len_org, hdr_len;
  1864. u8 id;
  1865. u8 unicast;
  1866. u8 sta_id;
  1867. u8 tid = 0;
  1868. u16 seq_number = 0;
  1869. __le16 fc;
  1870. u8 wait_write_ptr = 0;
  1871. u8 *qc = NULL;
  1872. unsigned long flags;
  1873. int rc;
  1874. spin_lock_irqsave(&priv->lock, flags);
  1875. if (iwl_is_rfkill(priv)) {
  1876. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  1877. goto drop_unlock;
  1878. }
  1879. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  1880. IWL_ERR(priv, "ERROR: No TX rate available.\n");
  1881. goto drop_unlock;
  1882. }
  1883. unicast = !is_multicast_ether_addr(hdr->addr1);
  1884. id = 0;
  1885. fc = hdr->frame_control;
  1886. #ifdef CONFIG_IWL3945_DEBUG
  1887. if (ieee80211_is_auth(fc))
  1888. IWL_DEBUG_TX("Sending AUTH frame\n");
  1889. else if (ieee80211_is_assoc_req(fc))
  1890. IWL_DEBUG_TX("Sending ASSOC frame\n");
  1891. else if (ieee80211_is_reassoc_req(fc))
  1892. IWL_DEBUG_TX("Sending REASSOC frame\n");
  1893. #endif
  1894. /* drop all data frame if we are not associated */
  1895. if (ieee80211_is_data(fc) &&
  1896. (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
  1897. (!iwl3945_is_associated(priv) ||
  1898. ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
  1899. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  1900. goto drop_unlock;
  1901. }
  1902. spin_unlock_irqrestore(&priv->lock, flags);
  1903. hdr_len = ieee80211_hdrlen(fc);
  1904. /* Find (or create) index into station table for destination station */
  1905. sta_id = iwl3945_get_sta_id(priv, hdr);
  1906. if (sta_id == IWL_INVALID_STATION) {
  1907. IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
  1908. hdr->addr1);
  1909. goto drop;
  1910. }
  1911. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  1912. if (ieee80211_is_data_qos(fc)) {
  1913. qc = ieee80211_get_qos_ctl(hdr);
  1914. tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
  1915. seq_number = priv->stations_39[sta_id].tid[tid].seq_number &
  1916. IEEE80211_SCTL_SEQ;
  1917. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  1918. (hdr->seq_ctrl &
  1919. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  1920. seq_number += 0x10;
  1921. }
  1922. /* Descriptor for chosen Tx queue */
  1923. txq = &priv->txq39[txq_id];
  1924. q = &txq->q;
  1925. spin_lock_irqsave(&priv->lock, flags);
  1926. /* Set up first empty TFD within this queue's circular TFD buffer */
  1927. tfd = &txq->bd[q->write_ptr];
  1928. memset(tfd, 0, sizeof(*tfd));
  1929. control_flags = (u32 *) tfd;
  1930. idx = get_cmd_index(q, q->write_ptr, 0);
  1931. /* Set up driver data for this TFD */
  1932. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
  1933. txq->txb[q->write_ptr].skb[0] = skb;
  1934. /* Init first empty entry in queue's array of Tx/cmd buffers */
  1935. out_cmd = &txq->cmd[idx];
  1936. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  1937. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  1938. /*
  1939. * Set up the Tx-command (not MAC!) header.
  1940. * Store the chosen Tx queue and TFD index within the sequence field;
  1941. * after Tx, uCode's Tx response will return this value so driver can
  1942. * locate the frame within the tx queue and do post-tx processing.
  1943. */
  1944. out_cmd->hdr.cmd = REPLY_TX;
  1945. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  1946. INDEX_TO_SEQ(q->write_ptr)));
  1947. /* Copy MAC header from skb into command buffer */
  1948. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  1949. /*
  1950. * Use the first empty entry in this queue's command buffer array
  1951. * to contain the Tx command and MAC header concatenated together
  1952. * (payload data will be in another buffer).
  1953. * Size of this varies, due to varying MAC header length.
  1954. * If end is not dword aligned, we'll have 2 extra bytes at the end
  1955. * of the MAC header (device reads on dword boundaries).
  1956. * We'll tell device about this padding later.
  1957. */
  1958. len = sizeof(struct iwl3945_tx_cmd) +
  1959. sizeof(struct iwl_cmd_header) + hdr_len;
  1960. len_org = len;
  1961. len = (len + 3) & ~3;
  1962. if (len_org != len)
  1963. len_org = 1;
  1964. else
  1965. len_org = 0;
  1966. /* Physical address of this Tx command's header (not MAC header!),
  1967. * within command buffer array. */
  1968. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl_cmd) * idx +
  1969. offsetof(struct iwl_cmd, hdr);
  1970. /* Add buffer containing Tx command and MAC(!) header to TFD's
  1971. * first entry */
  1972. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  1973. if (info->control.hw_key)
  1974. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
  1975. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  1976. * if any (802.11 null frames have no payload). */
  1977. len = skb->len - hdr_len;
  1978. if (len) {
  1979. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  1980. len, PCI_DMA_TODEVICE);
  1981. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  1982. }
  1983. if (!len)
  1984. /* If there is no payload, then we use only one Tx buffer */
  1985. *control_flags = TFD_CTL_COUNT_SET(1);
  1986. else
  1987. /* Else use 2 buffers.
  1988. * Tell 3945 about any padding after MAC header */
  1989. *control_flags = TFD_CTL_COUNT_SET(2) |
  1990. TFD_CTL_PAD_SET(U32_PAD(len));
  1991. /* Total # bytes to be transmitted */
  1992. len = (u16)skb->len;
  1993. out_cmd->cmd.tx.len = cpu_to_le16(len);
  1994. /* TODO need this for burst mode later on */
  1995. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
  1996. /* set is_hcca to 0; it probably will never be implemented */
  1997. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  1998. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  1999. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  2000. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  2001. txq->need_update = 1;
  2002. if (qc)
  2003. priv->stations_39[sta_id].tid[tid].seq_number = seq_number;
  2004. } else {
  2005. wait_write_ptr = 1;
  2006. txq->need_update = 0;
  2007. }
  2008. iwl_print_hex_dump(priv, IWL_DL_TX, out_cmd->cmd.payload,
  2009. sizeof(out_cmd->cmd.tx));
  2010. iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2011. ieee80211_hdrlen(fc));
  2012. /* Tell device the write index *just past* this latest filled TFD */
  2013. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  2014. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2015. spin_unlock_irqrestore(&priv->lock, flags);
  2016. if (rc)
  2017. return rc;
  2018. if ((iwl_queue_space(q) < q->high_mark)
  2019. && priv->mac80211_registered) {
  2020. if (wait_write_ptr) {
  2021. spin_lock_irqsave(&priv->lock, flags);
  2022. txq->need_update = 1;
  2023. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2024. spin_unlock_irqrestore(&priv->lock, flags);
  2025. }
  2026. ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
  2027. }
  2028. return 0;
  2029. drop_unlock:
  2030. spin_unlock_irqrestore(&priv->lock, flags);
  2031. drop:
  2032. return -1;
  2033. }
  2034. static void iwl3945_set_rate(struct iwl_priv *priv)
  2035. {
  2036. const struct ieee80211_supported_band *sband = NULL;
  2037. struct ieee80211_rate *rate;
  2038. int i;
  2039. sband = iwl_get_hw_mode(priv, priv->band);
  2040. if (!sband) {
  2041. IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
  2042. return;
  2043. }
  2044. priv->active_rate = 0;
  2045. priv->active_rate_basic = 0;
  2046. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2047. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2048. for (i = 0; i < sband->n_bitrates; i++) {
  2049. rate = &sband->bitrates[i];
  2050. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2051. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2052. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2053. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2054. priv->active_rate |= (1 << rate->hw_value);
  2055. }
  2056. }
  2057. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2058. priv->active_rate, priv->active_rate_basic);
  2059. /*
  2060. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2061. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2062. * OFDM
  2063. */
  2064. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2065. priv->staging39_rxon.cck_basic_rates =
  2066. ((priv->active_rate_basic &
  2067. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2068. else
  2069. priv->staging39_rxon.cck_basic_rates =
  2070. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2071. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2072. priv->staging39_rxon.ofdm_basic_rates =
  2073. ((priv->active_rate_basic &
  2074. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2075. IWL_FIRST_OFDM_RATE) & 0xFF;
  2076. else
  2077. priv->staging39_rxon.ofdm_basic_rates =
  2078. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2079. }
  2080. static void iwl3945_radio_kill_sw(struct iwl_priv *priv, int disable_radio)
  2081. {
  2082. unsigned long flags;
  2083. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2084. return;
  2085. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2086. disable_radio ? "OFF" : "ON");
  2087. if (disable_radio) {
  2088. iwl3945_scan_cancel(priv);
  2089. /* FIXME: This is a workaround for AP */
  2090. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  2091. spin_lock_irqsave(&priv->lock, flags);
  2092. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2093. CSR_UCODE_SW_BIT_RFKILL);
  2094. spin_unlock_irqrestore(&priv->lock, flags);
  2095. iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2096. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2097. }
  2098. return;
  2099. }
  2100. spin_lock_irqsave(&priv->lock, flags);
  2101. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2102. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2103. spin_unlock_irqrestore(&priv->lock, flags);
  2104. /* wake up ucode */
  2105. msleep(10);
  2106. spin_lock_irqsave(&priv->lock, flags);
  2107. iwl_read32(priv, CSR_UCODE_DRV_GP1);
  2108. if (!iwl_grab_nic_access(priv))
  2109. iwl_release_nic_access(priv);
  2110. spin_unlock_irqrestore(&priv->lock, flags);
  2111. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2112. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2113. "disabled by HW switch\n");
  2114. return;
  2115. }
  2116. if (priv->is_open)
  2117. queue_work(priv->workqueue, &priv->restart);
  2118. return;
  2119. }
  2120. void iwl3945_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb,
  2121. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2122. {
  2123. u16 fc =
  2124. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2125. if (priv->active39_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2126. return;
  2127. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2128. return;
  2129. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2130. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2131. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2132. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2133. RX_RES_STATUS_BAD_ICV_MIC)
  2134. stats->flag |= RX_FLAG_MMIC_ERROR;
  2135. case RX_RES_STATUS_SEC_TYPE_WEP:
  2136. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2137. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2138. RX_RES_STATUS_DECRYPT_OK) {
  2139. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2140. stats->flag |= RX_FLAG_DECRYPTED;
  2141. }
  2142. break;
  2143. default:
  2144. break;
  2145. }
  2146. }
  2147. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2148. #include "iwl-spectrum.h"
  2149. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2150. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2151. #define TIME_UNIT 1024
  2152. /*
  2153. * extended beacon time format
  2154. * time in usec will be changed into a 32-bit value in 8:24 format
  2155. * the high 1 byte is the beacon counts
  2156. * the lower 3 bytes is the time in usec within one beacon interval
  2157. */
  2158. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2159. {
  2160. u32 quot;
  2161. u32 rem;
  2162. u32 interval = beacon_interval * 1024;
  2163. if (!interval || !usec)
  2164. return 0;
  2165. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2166. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2167. return (quot << 24) + rem;
  2168. }
  2169. /* base is usually what we get from ucode with each received frame,
  2170. * the same as HW timer counter counting down
  2171. */
  2172. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2173. {
  2174. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2175. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2176. u32 interval = beacon_interval * TIME_UNIT;
  2177. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2178. (addon & BEACON_TIME_MASK_HIGH);
  2179. if (base_low > addon_low)
  2180. res += base_low - addon_low;
  2181. else if (base_low < addon_low) {
  2182. res += interval + base_low - addon_low;
  2183. res += (1 << 24);
  2184. } else
  2185. res += (1 << 24);
  2186. return cpu_to_le32(res);
  2187. }
  2188. static int iwl3945_get_measurement(struct iwl_priv *priv,
  2189. struct ieee80211_measurement_params *params,
  2190. u8 type)
  2191. {
  2192. struct iwl_spectrum_cmd spectrum;
  2193. struct iwl_rx_packet *res;
  2194. struct iwl_host_cmd cmd = {
  2195. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2196. .data = (void *)&spectrum,
  2197. .meta.flags = CMD_WANT_SKB,
  2198. };
  2199. u32 add_time = le64_to_cpu(params->start_time);
  2200. int rc;
  2201. int spectrum_resp_status;
  2202. int duration = le16_to_cpu(params->duration);
  2203. if (iwl3945_is_associated(priv))
  2204. add_time =
  2205. iwl3945_usecs_to_beacons(
  2206. le64_to_cpu(params->start_time) - priv->last_tsf,
  2207. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2208. memset(&spectrum, 0, sizeof(spectrum));
  2209. spectrum.channel_count = cpu_to_le16(1);
  2210. spectrum.flags =
  2211. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2212. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2213. cmd.len = sizeof(spectrum);
  2214. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2215. if (iwl3945_is_associated(priv))
  2216. spectrum.start_time =
  2217. iwl3945_add_beacon_time(priv->last_beacon_time,
  2218. add_time,
  2219. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2220. else
  2221. spectrum.start_time = 0;
  2222. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2223. spectrum.channels[0].channel = params->channel;
  2224. spectrum.channels[0].type = type;
  2225. if (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2226. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2227. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2228. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2229. if (rc)
  2230. return rc;
  2231. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  2232. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2233. IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
  2234. rc = -EIO;
  2235. }
  2236. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2237. switch (spectrum_resp_status) {
  2238. case 0: /* Command will be handled */
  2239. if (res->u.spectrum.id != 0xff) {
  2240. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2241. res->u.spectrum.id);
  2242. priv->measurement_status &= ~MEASUREMENT_READY;
  2243. }
  2244. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2245. rc = 0;
  2246. break;
  2247. case 1: /* Command will not be handled */
  2248. rc = -EAGAIN;
  2249. break;
  2250. }
  2251. dev_kfree_skb_any(cmd.meta.u.skb);
  2252. return rc;
  2253. }
  2254. #endif
  2255. static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
  2256. struct iwl_rx_mem_buffer *rxb)
  2257. {
  2258. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2259. struct iwl_alive_resp *palive;
  2260. struct delayed_work *pwork;
  2261. palive = &pkt->u.alive_frame;
  2262. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2263. "0x%01X 0x%01X\n",
  2264. palive->is_valid, palive->ver_type,
  2265. palive->ver_subtype);
  2266. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2267. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2268. memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
  2269. sizeof(struct iwl_alive_resp));
  2270. pwork = &priv->init_alive_start;
  2271. } else {
  2272. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2273. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2274. sizeof(struct iwl_alive_resp));
  2275. pwork = &priv->alive_start;
  2276. iwl3945_disable_events(priv);
  2277. }
  2278. /* We delay the ALIVE response by 5ms to
  2279. * give the HW RF Kill time to activate... */
  2280. if (palive->is_valid == UCODE_VALID_OK)
  2281. queue_delayed_work(priv->workqueue, pwork,
  2282. msecs_to_jiffies(5));
  2283. else
  2284. IWL_WARN(priv, "uCode did not respond OK.\n");
  2285. }
  2286. static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
  2287. struct iwl_rx_mem_buffer *rxb)
  2288. {
  2289. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2290. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2291. return;
  2292. }
  2293. static void iwl3945_rx_reply_error(struct iwl_priv *priv,
  2294. struct iwl_rx_mem_buffer *rxb)
  2295. {
  2296. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2297. IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
  2298. "seq 0x%04X ser 0x%08X\n",
  2299. le32_to_cpu(pkt->u.err_resp.error_type),
  2300. get_cmd_string(pkt->u.err_resp.cmd_id),
  2301. pkt->u.err_resp.cmd_id,
  2302. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2303. le32_to_cpu(pkt->u.err_resp.error_info));
  2304. }
  2305. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2306. static void iwl3945_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  2307. {
  2308. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2309. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active39_rxon;
  2310. struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
  2311. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2312. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2313. rxon->channel = csa->channel;
  2314. priv->staging39_rxon.channel = csa->channel;
  2315. }
  2316. static void iwl3945_rx_spectrum_measure_notif(struct iwl_priv *priv,
  2317. struct iwl_rx_mem_buffer *rxb)
  2318. {
  2319. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2320. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2321. struct iwl_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2322. if (!report->state) {
  2323. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2324. "Spectrum Measure Notification: Start\n");
  2325. return;
  2326. }
  2327. memcpy(&priv->measure_report, report, sizeof(*report));
  2328. priv->measurement_status |= MEASUREMENT_READY;
  2329. #endif
  2330. }
  2331. static void iwl3945_rx_pm_sleep_notif(struct iwl_priv *priv,
  2332. struct iwl_rx_mem_buffer *rxb)
  2333. {
  2334. #ifdef CONFIG_IWL3945_DEBUG
  2335. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2336. struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2337. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2338. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2339. #endif
  2340. }
  2341. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
  2342. struct iwl_rx_mem_buffer *rxb)
  2343. {
  2344. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2345. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2346. "notification for %s:\n",
  2347. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2348. iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw,
  2349. le32_to_cpu(pkt->len));
  2350. }
  2351. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2352. {
  2353. struct iwl_priv *priv =
  2354. container_of(work, struct iwl_priv, beacon_update);
  2355. struct sk_buff *beacon;
  2356. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2357. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  2358. if (!beacon) {
  2359. IWL_ERR(priv, "update beacon failed\n");
  2360. return;
  2361. }
  2362. mutex_lock(&priv->mutex);
  2363. /* new beacon skb is allocated every time; dispose previous.*/
  2364. if (priv->ibss_beacon)
  2365. dev_kfree_skb(priv->ibss_beacon);
  2366. priv->ibss_beacon = beacon;
  2367. mutex_unlock(&priv->mutex);
  2368. iwl3945_send_beacon_cmd(priv);
  2369. }
  2370. static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
  2371. struct iwl_rx_mem_buffer *rxb)
  2372. {
  2373. #ifdef CONFIG_IWL3945_DEBUG
  2374. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2375. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2376. u8 rate = beacon->beacon_notify_hdr.rate;
  2377. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  2378. "tsf %d %d rate %d\n",
  2379. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  2380. beacon->beacon_notify_hdr.failure_frame,
  2381. le32_to_cpu(beacon->ibss_mgr_status),
  2382. le32_to_cpu(beacon->high_tsf),
  2383. le32_to_cpu(beacon->low_tsf), rate);
  2384. #endif
  2385. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  2386. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  2387. queue_work(priv->workqueue, &priv->beacon_update);
  2388. }
  2389. /* Service response to REPLY_SCAN_CMD (0x80) */
  2390. static void iwl3945_rx_reply_scan(struct iwl_priv *priv,
  2391. struct iwl_rx_mem_buffer *rxb)
  2392. {
  2393. #ifdef CONFIG_IWL3945_DEBUG
  2394. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2395. struct iwl_scanreq_notification *notif =
  2396. (struct iwl_scanreq_notification *)pkt->u.raw;
  2397. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  2398. #endif
  2399. }
  2400. /* Service SCAN_START_NOTIFICATION (0x82) */
  2401. static void iwl3945_rx_scan_start_notif(struct iwl_priv *priv,
  2402. struct iwl_rx_mem_buffer *rxb)
  2403. {
  2404. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2405. struct iwl_scanstart_notification *notif =
  2406. (struct iwl_scanstart_notification *)pkt->u.raw;
  2407. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  2408. IWL_DEBUG_SCAN("Scan start: "
  2409. "%d [802.11%s] "
  2410. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  2411. notif->channel,
  2412. notif->band ? "bg" : "a",
  2413. notif->tsf_high,
  2414. notif->tsf_low, notif->status, notif->beacon_timer);
  2415. }
  2416. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  2417. static void iwl3945_rx_scan_results_notif(struct iwl_priv *priv,
  2418. struct iwl_rx_mem_buffer *rxb)
  2419. {
  2420. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2421. struct iwl_scanresults_notification *notif =
  2422. (struct iwl_scanresults_notification *)pkt->u.raw;
  2423. IWL_DEBUG_SCAN("Scan ch.res: "
  2424. "%d [802.11%s] "
  2425. "(TSF: 0x%08X:%08X) - %d "
  2426. "elapsed=%lu usec (%dms since last)\n",
  2427. notif->channel,
  2428. notif->band ? "bg" : "a",
  2429. le32_to_cpu(notif->tsf_high),
  2430. le32_to_cpu(notif->tsf_low),
  2431. le32_to_cpu(notif->statistics[0]),
  2432. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  2433. jiffies_to_msecs(elapsed_jiffies
  2434. (priv->last_scan_jiffies, jiffies)));
  2435. priv->last_scan_jiffies = jiffies;
  2436. priv->next_scan_jiffies = 0;
  2437. }
  2438. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  2439. static void iwl3945_rx_scan_complete_notif(struct iwl_priv *priv,
  2440. struct iwl_rx_mem_buffer *rxb)
  2441. {
  2442. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2443. struct iwl_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  2444. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  2445. scan_notif->scanned_channels,
  2446. scan_notif->tsf_low,
  2447. scan_notif->tsf_high, scan_notif->status);
  2448. /* The HW is no longer scanning */
  2449. clear_bit(STATUS_SCAN_HW, &priv->status);
  2450. /* The scan completion notification came in, so kill that timer... */
  2451. cancel_delayed_work(&priv->scan_check);
  2452. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  2453. (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
  2454. "2.4" : "5.2",
  2455. jiffies_to_msecs(elapsed_jiffies
  2456. (priv->scan_pass_start, jiffies)));
  2457. /* Remove this scanned band from the list of pending
  2458. * bands to scan, band G precedes A in order of scanning
  2459. * as seen in iwl3945_bg_request_scan */
  2460. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
  2461. priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
  2462. else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
  2463. priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
  2464. /* If a request to abort was given, or the scan did not succeed
  2465. * then we reset the scan state machine and terminate,
  2466. * re-queuing another scan if one has been requested */
  2467. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2468. IWL_DEBUG_INFO("Aborted scan completed.\n");
  2469. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  2470. } else {
  2471. /* If there are more bands on this scan pass reschedule */
  2472. if (priv->scan_bands > 0)
  2473. goto reschedule;
  2474. }
  2475. priv->last_scan_jiffies = jiffies;
  2476. priv->next_scan_jiffies = 0;
  2477. IWL_DEBUG_INFO("Setting scan to off\n");
  2478. clear_bit(STATUS_SCANNING, &priv->status);
  2479. IWL_DEBUG_INFO("Scan took %dms\n",
  2480. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  2481. queue_work(priv->workqueue, &priv->scan_completed);
  2482. return;
  2483. reschedule:
  2484. priv->scan_pass_start = jiffies;
  2485. queue_work(priv->workqueue, &priv->request_scan);
  2486. }
  2487. /* Handle notification from uCode that card's power state is changing
  2488. * due to software, hardware, or critical temperature RFKILL */
  2489. static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
  2490. struct iwl_rx_mem_buffer *rxb)
  2491. {
  2492. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2493. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  2494. unsigned long status = priv->status;
  2495. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  2496. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  2497. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  2498. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2499. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2500. if (flags & HW_CARD_DISABLED)
  2501. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2502. else
  2503. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2504. if (flags & SW_CARD_DISABLED)
  2505. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2506. else
  2507. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2508. iwl3945_scan_cancel(priv);
  2509. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  2510. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  2511. (test_bit(STATUS_RF_KILL_SW, &status) !=
  2512. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  2513. queue_work(priv->workqueue, &priv->rf_kill);
  2514. else
  2515. wake_up_interruptible(&priv->wait_command_queue);
  2516. }
  2517. /**
  2518. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  2519. *
  2520. * Setup the RX handlers for each of the reply types sent from the uCode
  2521. * to the host.
  2522. *
  2523. * This function chains into the hardware specific files for them to setup
  2524. * any hardware specific handlers as well.
  2525. */
  2526. static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
  2527. {
  2528. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  2529. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  2530. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  2531. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  2532. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  2533. iwl3945_rx_spectrum_measure_notif;
  2534. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  2535. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  2536. iwl3945_rx_pm_debug_statistics_notif;
  2537. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  2538. /*
  2539. * The same handler is used for both the REPLY to a discrete
  2540. * statistics request from the host as well as for the periodic
  2541. * statistics notifications (after received beacons) from the uCode.
  2542. */
  2543. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  2544. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  2545. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  2546. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  2547. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  2548. iwl3945_rx_scan_results_notif;
  2549. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  2550. iwl3945_rx_scan_complete_notif;
  2551. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  2552. /* Set up hardware specific Rx handlers */
  2553. iwl3945_hw_rx_handler_setup(priv);
  2554. }
  2555. /**
  2556. * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
  2557. * When FW advances 'R' index, all entries between old and new 'R' index
  2558. * need to be reclaimed.
  2559. */
  2560. static void iwl3945_cmd_queue_reclaim(struct iwl_priv *priv,
  2561. int txq_id, int index)
  2562. {
  2563. struct iwl3945_tx_queue *txq = &priv->txq39[txq_id];
  2564. struct iwl_queue *q = &txq->q;
  2565. int nfreed = 0;
  2566. if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
  2567. IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
  2568. "is out of range [0-%d] %d %d.\n", txq_id,
  2569. index, q->n_bd, q->write_ptr, q->read_ptr);
  2570. return;
  2571. }
  2572. for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
  2573. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2574. if (nfreed > 1) {
  2575. IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", index,
  2576. q->write_ptr, q->read_ptr);
  2577. queue_work(priv->workqueue, &priv->restart);
  2578. break;
  2579. }
  2580. nfreed++;
  2581. }
  2582. }
  2583. /**
  2584. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2585. * @rxb: Rx buffer to reclaim
  2586. *
  2587. * If an Rx buffer has an async callback associated with it the callback
  2588. * will be executed. The attached skb (if present) will only be freed
  2589. * if the callback returns 1
  2590. */
  2591. static void iwl3945_tx_cmd_complete(struct iwl_priv *priv,
  2592. struct iwl_rx_mem_buffer *rxb)
  2593. {
  2594. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2595. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2596. int txq_id = SEQ_TO_QUEUE(sequence);
  2597. int index = SEQ_TO_INDEX(sequence);
  2598. int huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
  2599. int cmd_index;
  2600. struct iwl_cmd *cmd;
  2601. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  2602. cmd_index = get_cmd_index(&priv->txq39[IWL_CMD_QUEUE_NUM].q, index, huge);
  2603. cmd = &priv->txq39[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  2604. /* Input error checking is done when commands are added to queue. */
  2605. if (cmd->meta.flags & CMD_WANT_SKB) {
  2606. cmd->meta.source->u.skb = rxb->skb;
  2607. rxb->skb = NULL;
  2608. } else if (cmd->meta.u.callback &&
  2609. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  2610. rxb->skb = NULL;
  2611. iwl3945_cmd_queue_reclaim(priv, txq_id, index);
  2612. if (!(cmd->meta.flags & CMD_ASYNC)) {
  2613. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  2614. wake_up_interruptible(&priv->wait_command_queue);
  2615. }
  2616. }
  2617. /************************** RX-FUNCTIONS ****************************/
  2618. /*
  2619. * Rx theory of operation
  2620. *
  2621. * The host allocates 32 DMA target addresses and passes the host address
  2622. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  2623. * 0 to 31
  2624. *
  2625. * Rx Queue Indexes
  2626. * The host/firmware share two index registers for managing the Rx buffers.
  2627. *
  2628. * The READ index maps to the first position that the firmware may be writing
  2629. * to -- the driver can read up to (but not including) this position and get
  2630. * good data.
  2631. * The READ index is managed by the firmware once the card is enabled.
  2632. *
  2633. * The WRITE index maps to the last position the driver has read from -- the
  2634. * position preceding WRITE is the last slot the firmware can place a packet.
  2635. *
  2636. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2637. * WRITE = READ.
  2638. *
  2639. * During initialization, the host sets up the READ queue position to the first
  2640. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  2641. *
  2642. * When the firmware places a packet in a buffer, it will advance the READ index
  2643. * and fire the RX interrupt. The driver can then query the READ index and
  2644. * process as many packets as possible, moving the WRITE index forward as it
  2645. * resets the Rx queue buffers with new memory.
  2646. *
  2647. * The management in the driver is as follows:
  2648. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2649. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2650. * to replenish the iwl->rxq->rx_free.
  2651. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  2652. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  2653. * 'processed' and 'read' driver indexes as well)
  2654. * + A received packet is processed and handed to the kernel network stack,
  2655. * detached from the iwl->rxq. The driver 'processed' index is updated.
  2656. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2657. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2658. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  2659. * were enough free buffers and RX_STALLED is set it is cleared.
  2660. *
  2661. *
  2662. * Driver sequence:
  2663. *
  2664. * iwl3945_rx_queue_alloc() Allocates rx_free
  2665. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  2666. * iwl3945_rx_queue_restock
  2667. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  2668. * queue, updates firmware pointers, and updates
  2669. * the WRITE index. If insufficient rx_free buffers
  2670. * are available, schedules iwl3945_rx_replenish
  2671. *
  2672. * -- enable interrupts --
  2673. * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
  2674. * READ INDEX, detaching the SKB from the pool.
  2675. * Moves the packet buffer from queue to rx_used.
  2676. * Calls iwl3945_rx_queue_restock to refill any empty
  2677. * slots.
  2678. * ...
  2679. *
  2680. */
  2681. /**
  2682. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  2683. */
  2684. static int iwl3945_rx_queue_space(const struct iwl_rx_queue *q)
  2685. {
  2686. int s = q->read - q->write;
  2687. if (s <= 0)
  2688. s += RX_QUEUE_SIZE;
  2689. /* keep some buffer to not confuse full and empty queue */
  2690. s -= 2;
  2691. if (s < 0)
  2692. s = 0;
  2693. return s;
  2694. }
  2695. /**
  2696. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  2697. */
  2698. int iwl3945_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
  2699. {
  2700. u32 reg = 0;
  2701. int rc = 0;
  2702. unsigned long flags;
  2703. spin_lock_irqsave(&q->lock, flags);
  2704. if (q->need_update == 0)
  2705. goto exit_unlock;
  2706. /* If power-saving is in use, make sure device is awake */
  2707. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  2708. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  2709. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2710. iwl_set_bit(priv, CSR_GP_CNTRL,
  2711. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2712. goto exit_unlock;
  2713. }
  2714. rc = iwl_grab_nic_access(priv);
  2715. if (rc)
  2716. goto exit_unlock;
  2717. /* Device expects a multiple of 8 */
  2718. iwl_write_direct32(priv, FH39_RSCSR_CHNL0_WPTR,
  2719. q->write & ~0x7);
  2720. iwl_release_nic_access(priv);
  2721. /* Else device is assumed to be awake */
  2722. } else
  2723. /* Device expects a multiple of 8 */
  2724. iwl_write32(priv, FH39_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  2725. q->need_update = 0;
  2726. exit_unlock:
  2727. spin_unlock_irqrestore(&q->lock, flags);
  2728. return rc;
  2729. }
  2730. /**
  2731. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  2732. */
  2733. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
  2734. dma_addr_t dma_addr)
  2735. {
  2736. return cpu_to_le32((u32)dma_addr);
  2737. }
  2738. /**
  2739. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  2740. *
  2741. * If there are slots in the RX queue that need to be restocked,
  2742. * and we have free pre-allocated buffers, fill the ranks as much
  2743. * as we can, pulling from rx_free.
  2744. *
  2745. * This moves the 'write' index forward to catch up with 'processed', and
  2746. * also updates the memory address in the firmware to reference the new
  2747. * target buffer.
  2748. */
  2749. static int iwl3945_rx_queue_restock(struct iwl_priv *priv)
  2750. {
  2751. struct iwl_rx_queue *rxq = &priv->rxq;
  2752. struct list_head *element;
  2753. struct iwl_rx_mem_buffer *rxb;
  2754. unsigned long flags;
  2755. int write, rc;
  2756. spin_lock_irqsave(&rxq->lock, flags);
  2757. write = rxq->write & ~0x7;
  2758. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  2759. /* Get next free Rx buffer, remove from free list */
  2760. element = rxq->rx_free.next;
  2761. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  2762. list_del(element);
  2763. /* Point to Rx buffer via next RBD in circular buffer */
  2764. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr);
  2765. rxq->queue[rxq->write] = rxb;
  2766. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  2767. rxq->free_count--;
  2768. }
  2769. spin_unlock_irqrestore(&rxq->lock, flags);
  2770. /* If the pre-allocated buffer pool is dropping low, schedule to
  2771. * refill it */
  2772. if (rxq->free_count <= RX_LOW_WATERMARK)
  2773. queue_work(priv->workqueue, &priv->rx_replenish);
  2774. /* If we've added more space for the firmware to place data, tell it.
  2775. * Increment device's write pointer in multiples of 8. */
  2776. if ((write != (rxq->write & ~0x7))
  2777. || (abs(rxq->write - rxq->read) > 7)) {
  2778. spin_lock_irqsave(&rxq->lock, flags);
  2779. rxq->need_update = 1;
  2780. spin_unlock_irqrestore(&rxq->lock, flags);
  2781. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  2782. if (rc)
  2783. return rc;
  2784. }
  2785. return 0;
  2786. }
  2787. /**
  2788. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  2789. *
  2790. * When moving to rx_free an SKB is allocated for the slot.
  2791. *
  2792. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  2793. * This is called as a scheduled work item (except for during initialization)
  2794. */
  2795. static void iwl3945_rx_allocate(struct iwl_priv *priv)
  2796. {
  2797. struct iwl_rx_queue *rxq = &priv->rxq;
  2798. struct list_head *element;
  2799. struct iwl_rx_mem_buffer *rxb;
  2800. unsigned long flags;
  2801. spin_lock_irqsave(&rxq->lock, flags);
  2802. while (!list_empty(&rxq->rx_used)) {
  2803. element = rxq->rx_used.next;
  2804. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  2805. /* Alloc a new receive buffer */
  2806. rxb->skb =
  2807. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  2808. if (!rxb->skb) {
  2809. if (net_ratelimit())
  2810. IWL_CRIT(priv, ": Can not allocate SKB buffers\n");
  2811. /* We don't reschedule replenish work here -- we will
  2812. * call the restock method and if it still needs
  2813. * more buffers it will schedule replenish */
  2814. break;
  2815. }
  2816. /* If radiotap head is required, reserve some headroom here.
  2817. * The physical head count is a variable rx_stats->phy_count.
  2818. * We reserve 4 bytes here. Plus these extra bytes, the
  2819. * headroom of the physical head should be enough for the
  2820. * radiotap head that iwl3945 supported. See iwl3945_rt.
  2821. */
  2822. skb_reserve(rxb->skb, 4);
  2823. priv->alloc_rxb_skb++;
  2824. list_del(element);
  2825. /* Get physical address of RB/SKB */
  2826. rxb->real_dma_addr =
  2827. pci_map_single(priv->pci_dev, rxb->skb->data,
  2828. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  2829. list_add_tail(&rxb->list, &rxq->rx_free);
  2830. rxq->free_count++;
  2831. }
  2832. spin_unlock_irqrestore(&rxq->lock, flags);
  2833. }
  2834. /*
  2835. * this should be called while priv->lock is locked
  2836. */
  2837. static void __iwl3945_rx_replenish(void *data)
  2838. {
  2839. struct iwl_priv *priv = data;
  2840. iwl3945_rx_allocate(priv);
  2841. iwl3945_rx_queue_restock(priv);
  2842. }
  2843. void iwl3945_rx_replenish(void *data)
  2844. {
  2845. struct iwl_priv *priv = data;
  2846. unsigned long flags;
  2847. iwl3945_rx_allocate(priv);
  2848. spin_lock_irqsave(&priv->lock, flags);
  2849. iwl3945_rx_queue_restock(priv);
  2850. spin_unlock_irqrestore(&priv->lock, flags);
  2851. }
  2852. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  2853. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  2854. * This free routine walks the list of POOL entries and if SKB is set to
  2855. * non NULL it is unmapped and freed
  2856. */
  2857. static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  2858. {
  2859. int i;
  2860. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  2861. if (rxq->pool[i].skb != NULL) {
  2862. pci_unmap_single(priv->pci_dev,
  2863. rxq->pool[i].real_dma_addr,
  2864. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  2865. dev_kfree_skb(rxq->pool[i].skb);
  2866. }
  2867. }
  2868. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  2869. rxq->dma_addr);
  2870. rxq->bd = NULL;
  2871. }
  2872. int iwl3945_rx_queue_alloc(struct iwl_priv *priv)
  2873. {
  2874. struct iwl_rx_queue *rxq = &priv->rxq;
  2875. struct pci_dev *dev = priv->pci_dev;
  2876. int i;
  2877. spin_lock_init(&rxq->lock);
  2878. INIT_LIST_HEAD(&rxq->rx_free);
  2879. INIT_LIST_HEAD(&rxq->rx_used);
  2880. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  2881. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  2882. if (!rxq->bd)
  2883. return -ENOMEM;
  2884. /* Fill the rx_used queue with _all_ of the Rx buffers */
  2885. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  2886. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  2887. /* Set us so that we have processed and used all buffers, but have
  2888. * not restocked the Rx queue with fresh buffers */
  2889. rxq->read = rxq->write = 0;
  2890. rxq->free_count = 0;
  2891. rxq->need_update = 0;
  2892. return 0;
  2893. }
  2894. void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  2895. {
  2896. unsigned long flags;
  2897. int i;
  2898. spin_lock_irqsave(&rxq->lock, flags);
  2899. INIT_LIST_HEAD(&rxq->rx_free);
  2900. INIT_LIST_HEAD(&rxq->rx_used);
  2901. /* Fill the rx_used queue with _all_ of the Rx buffers */
  2902. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  2903. /* In the reset function, these buffers may have been allocated
  2904. * to an SKB, so we need to unmap and free potential storage */
  2905. if (rxq->pool[i].skb != NULL) {
  2906. pci_unmap_single(priv->pci_dev,
  2907. rxq->pool[i].real_dma_addr,
  2908. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  2909. priv->alloc_rxb_skb--;
  2910. dev_kfree_skb(rxq->pool[i].skb);
  2911. rxq->pool[i].skb = NULL;
  2912. }
  2913. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  2914. }
  2915. /* Set us so that we have processed and used all buffers, but have
  2916. * not restocked the Rx queue with fresh buffers */
  2917. rxq->read = rxq->write = 0;
  2918. rxq->free_count = 0;
  2919. spin_unlock_irqrestore(&rxq->lock, flags);
  2920. }
  2921. /* Convert linear signal-to-noise ratio into dB */
  2922. static u8 ratio2dB[100] = {
  2923. /* 0 1 2 3 4 5 6 7 8 9 */
  2924. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  2925. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  2926. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  2927. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  2928. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  2929. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  2930. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  2931. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  2932. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  2933. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  2934. };
  2935. /* Calculates a relative dB value from a ratio of linear
  2936. * (i.e. not dB) signal levels.
  2937. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  2938. int iwl3945_calc_db_from_ratio(int sig_ratio)
  2939. {
  2940. /* 1000:1 or higher just report as 60 dB */
  2941. if (sig_ratio >= 1000)
  2942. return 60;
  2943. /* 100:1 or higher, divide by 10 and use table,
  2944. * add 20 dB to make up for divide by 10 */
  2945. if (sig_ratio >= 100)
  2946. return 20 + (int)ratio2dB[sig_ratio/10];
  2947. /* We shouldn't see this */
  2948. if (sig_ratio < 1)
  2949. return 0;
  2950. /* Use table for ratios 1:1 - 99:1 */
  2951. return (int)ratio2dB[sig_ratio];
  2952. }
  2953. #define PERFECT_RSSI (-20) /* dBm */
  2954. #define WORST_RSSI (-95) /* dBm */
  2955. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  2956. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  2957. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  2958. * about formulas used below. */
  2959. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  2960. {
  2961. int sig_qual;
  2962. int degradation = PERFECT_RSSI - rssi_dbm;
  2963. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  2964. * as indicator; formula is (signal dbm - noise dbm).
  2965. * SNR at or above 40 is a great signal (100%).
  2966. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  2967. * Weakest usable signal is usually 10 - 15 dB SNR. */
  2968. if (noise_dbm) {
  2969. if (rssi_dbm - noise_dbm >= 40)
  2970. return 100;
  2971. else if (rssi_dbm < noise_dbm)
  2972. return 0;
  2973. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  2974. /* Else use just the signal level.
  2975. * This formula is a least squares fit of data points collected and
  2976. * compared with a reference system that had a percentage (%) display
  2977. * for signal quality. */
  2978. } else
  2979. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  2980. (15 * RSSI_RANGE + 62 * degradation)) /
  2981. (RSSI_RANGE * RSSI_RANGE);
  2982. if (sig_qual > 100)
  2983. sig_qual = 100;
  2984. else if (sig_qual < 1)
  2985. sig_qual = 0;
  2986. return sig_qual;
  2987. }
  2988. /**
  2989. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  2990. *
  2991. * Uses the priv->rx_handlers callback function array to invoke
  2992. * the appropriate handlers, including command responses,
  2993. * frame-received notifications, and other notifications.
  2994. */
  2995. static void iwl3945_rx_handle(struct iwl_priv *priv)
  2996. {
  2997. struct iwl_rx_mem_buffer *rxb;
  2998. struct iwl_rx_packet *pkt;
  2999. struct iwl_rx_queue *rxq = &priv->rxq;
  3000. u32 r, i;
  3001. int reclaim;
  3002. unsigned long flags;
  3003. u8 fill_rx = 0;
  3004. u32 count = 8;
  3005. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  3006. * buffer that the driver may process (last buffer filled by ucode). */
  3007. r = iwl3945_hw_get_rx_read(priv);
  3008. i = rxq->read;
  3009. if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  3010. fill_rx = 1;
  3011. /* Rx interrupt, but nothing sent from uCode */
  3012. if (i == r)
  3013. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3014. while (i != r) {
  3015. rxb = rxq->queue[i];
  3016. /* If an RXB doesn't have a Rx queue slot associated with it,
  3017. * then a bug has been introduced in the queue refilling
  3018. * routines -- catch it here */
  3019. BUG_ON(rxb == NULL);
  3020. rxq->queue[i] = NULL;
  3021. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->real_dma_addr,
  3022. IWL_RX_BUF_SIZE,
  3023. PCI_DMA_FROMDEVICE);
  3024. pkt = (struct iwl_rx_packet *)rxb->skb->data;
  3025. /* Reclaim a command buffer only if this packet is a response
  3026. * to a (driver-originated) command.
  3027. * If the packet (e.g. Rx frame) originated from uCode,
  3028. * there is no command buffer to reclaim.
  3029. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3030. * but apparently a few don't get set; catch them here. */
  3031. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3032. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3033. (pkt->hdr.cmd != REPLY_TX);
  3034. /* Based on type of command response or notification,
  3035. * handle those that need handling via function in
  3036. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3037. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3038. IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
  3039. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3040. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3041. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3042. } else {
  3043. /* No handling needed */
  3044. IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
  3045. "r %d i %d No handler needed for %s, 0x%02x\n",
  3046. r, i, get_cmd_string(pkt->hdr.cmd),
  3047. pkt->hdr.cmd);
  3048. }
  3049. if (reclaim) {
  3050. /* Invoke any callbacks, transfer the skb to caller, and
  3051. * fire off the (possibly) blocking iwl3945_send_cmd()
  3052. * as we reclaim the driver command queue */
  3053. if (rxb && rxb->skb)
  3054. iwl3945_tx_cmd_complete(priv, rxb);
  3055. else
  3056. IWL_WARN(priv, "Claim null rxb?\n");
  3057. }
  3058. /* For now we just don't re-use anything. We can tweak this
  3059. * later to try and re-use notification packets and SKBs that
  3060. * fail to Rx correctly */
  3061. if (rxb->skb != NULL) {
  3062. priv->alloc_rxb_skb--;
  3063. dev_kfree_skb_any(rxb->skb);
  3064. rxb->skb = NULL;
  3065. }
  3066. pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
  3067. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3068. spin_lock_irqsave(&rxq->lock, flags);
  3069. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3070. spin_unlock_irqrestore(&rxq->lock, flags);
  3071. i = (i + 1) & RX_QUEUE_MASK;
  3072. /* If there are a lot of unused frames,
  3073. * restock the Rx queue so ucode won't assert. */
  3074. if (fill_rx) {
  3075. count++;
  3076. if (count >= 8) {
  3077. priv->rxq.read = i;
  3078. __iwl3945_rx_replenish(priv);
  3079. count = 0;
  3080. }
  3081. }
  3082. }
  3083. /* Backtrack one entry */
  3084. priv->rxq.read = i;
  3085. iwl3945_rx_queue_restock(priv);
  3086. }
  3087. /**
  3088. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  3089. */
  3090. static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
  3091. struct iwl3945_tx_queue *txq)
  3092. {
  3093. u32 reg = 0;
  3094. int rc = 0;
  3095. int txq_id = txq->q.id;
  3096. if (txq->need_update == 0)
  3097. return rc;
  3098. /* if we're trying to save power */
  3099. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3100. /* wake up nic if it's powered down ...
  3101. * uCode will wake up, and interrupt us again, so next
  3102. * time we'll skip this part. */
  3103. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  3104. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3105. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3106. iwl_set_bit(priv, CSR_GP_CNTRL,
  3107. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3108. return rc;
  3109. }
  3110. /* restore this queue's parameters in nic hardware. */
  3111. rc = iwl_grab_nic_access(priv);
  3112. if (rc)
  3113. return rc;
  3114. iwl_write_direct32(priv, HBUS_TARG_WRPTR,
  3115. txq->q.write_ptr | (txq_id << 8));
  3116. iwl_release_nic_access(priv);
  3117. /* else not in power-save mode, uCode will never sleep when we're
  3118. * trying to tx (during RFKILL, we're not trying to tx). */
  3119. } else
  3120. iwl_write32(priv, HBUS_TARG_WRPTR,
  3121. txq->q.write_ptr | (txq_id << 8));
  3122. txq->need_update = 0;
  3123. return rc;
  3124. }
  3125. #ifdef CONFIG_IWL3945_DEBUG
  3126. static void iwl3945_print_rx_config_cmd(struct iwl_priv *priv,
  3127. struct iwl3945_rxon_cmd *rxon)
  3128. {
  3129. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3130. iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3131. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3132. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3133. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3134. le32_to_cpu(rxon->filter_flags));
  3135. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3136. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3137. rxon->ofdm_basic_rates);
  3138. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3139. IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
  3140. IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  3141. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3142. }
  3143. #endif
  3144. static void iwl3945_enable_interrupts(struct iwl_priv *priv)
  3145. {
  3146. IWL_DEBUG_ISR("Enabling interrupts\n");
  3147. set_bit(STATUS_INT_ENABLED, &priv->status);
  3148. iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3149. }
  3150. /* call this function to flush any scheduled tasklet */
  3151. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  3152. {
  3153. /* wait to make sure we flush pending tasklet*/
  3154. synchronize_irq(priv->pci_dev->irq);
  3155. tasklet_kill(&priv->irq_tasklet);
  3156. }
  3157. static inline void iwl3945_disable_interrupts(struct iwl_priv *priv)
  3158. {
  3159. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3160. /* disable interrupts from uCode/NIC to host */
  3161. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  3162. /* acknowledge/clear/reset any interrupts still pending
  3163. * from uCode or flow handler (Rx/Tx DMA) */
  3164. iwl_write32(priv, CSR_INT, 0xffffffff);
  3165. iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3166. IWL_DEBUG_ISR("Disabled interrupts\n");
  3167. }
  3168. static const char *desc_lookup(int i)
  3169. {
  3170. switch (i) {
  3171. case 1:
  3172. return "FAIL";
  3173. case 2:
  3174. return "BAD_PARAM";
  3175. case 3:
  3176. return "BAD_CHECKSUM";
  3177. case 4:
  3178. return "NMI_INTERRUPT";
  3179. case 5:
  3180. return "SYSASSERT";
  3181. case 6:
  3182. return "FATAL_ERROR";
  3183. }
  3184. return "UNKNOWN";
  3185. }
  3186. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3187. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3188. static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
  3189. {
  3190. u32 i;
  3191. u32 desc, time, count, base, data1;
  3192. u32 blink1, blink2, ilink1, ilink2;
  3193. int rc;
  3194. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3195. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3196. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  3197. return;
  3198. }
  3199. rc = iwl_grab_nic_access(priv);
  3200. if (rc) {
  3201. IWL_WARN(priv, "Can not read from adapter at this time.\n");
  3202. return;
  3203. }
  3204. count = iwl_read_targ_mem(priv, base);
  3205. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3206. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  3207. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  3208. priv->status, count);
  3209. }
  3210. IWL_ERR(priv, "Desc Time asrtPC blink2 "
  3211. "ilink1 nmiPC Line\n");
  3212. for (i = ERROR_START_OFFSET;
  3213. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3214. i += ERROR_ELEM_SIZE) {
  3215. desc = iwl_read_targ_mem(priv, base + i);
  3216. time =
  3217. iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3218. blink1 =
  3219. iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3220. blink2 =
  3221. iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3222. ilink1 =
  3223. iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3224. ilink2 =
  3225. iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3226. data1 =
  3227. iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3228. IWL_ERR(priv,
  3229. "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3230. desc_lookup(desc), desc, time, blink1, blink2,
  3231. ilink1, ilink2, data1);
  3232. }
  3233. iwl_release_nic_access(priv);
  3234. }
  3235. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3236. /**
  3237. * iwl3945_print_event_log - Dump error event log to syslog
  3238. *
  3239. * NOTE: Must be called with iwl_grab_nic_access() already obtained!
  3240. */
  3241. static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
  3242. u32 num_events, u32 mode)
  3243. {
  3244. u32 i;
  3245. u32 base; /* SRAM byte address of event log header */
  3246. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3247. u32 ptr; /* SRAM byte address of log data */
  3248. u32 ev, time, data; /* event log data */
  3249. if (num_events == 0)
  3250. return;
  3251. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3252. if (mode == 0)
  3253. event_size = 2 * sizeof(u32);
  3254. else
  3255. event_size = 3 * sizeof(u32);
  3256. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3257. /* "time" is actually "data" for mode 0 (no timestamp).
  3258. * place event id # at far right for easier visual parsing. */
  3259. for (i = 0; i < num_events; i++) {
  3260. ev = iwl_read_targ_mem(priv, ptr);
  3261. ptr += sizeof(u32);
  3262. time = iwl_read_targ_mem(priv, ptr);
  3263. ptr += sizeof(u32);
  3264. if (mode == 0) {
  3265. /* data, ev */
  3266. IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
  3267. } else {
  3268. data = iwl_read_targ_mem(priv, ptr);
  3269. ptr += sizeof(u32);
  3270. IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", time, data, ev);
  3271. }
  3272. }
  3273. }
  3274. static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
  3275. {
  3276. int rc;
  3277. u32 base; /* SRAM byte address of event log header */
  3278. u32 capacity; /* event log capacity in # entries */
  3279. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3280. u32 num_wraps; /* # times uCode wrapped to top of log */
  3281. u32 next_entry; /* index of next entry to be written by uCode */
  3282. u32 size; /* # entries that we'll print */
  3283. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3284. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3285. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  3286. return;
  3287. }
  3288. rc = iwl_grab_nic_access(priv);
  3289. if (rc) {
  3290. IWL_WARN(priv, "Can not read from adapter at this time.\n");
  3291. return;
  3292. }
  3293. /* event log header */
  3294. capacity = iwl_read_targ_mem(priv, base);
  3295. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3296. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3297. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3298. size = num_wraps ? capacity : next_entry;
  3299. /* bail out if nothing in log */
  3300. if (size == 0) {
  3301. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  3302. iwl_release_nic_access(priv);
  3303. return;
  3304. }
  3305. IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
  3306. size, num_wraps);
  3307. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3308. * i.e the next one that uCode would fill. */
  3309. if (num_wraps)
  3310. iwl3945_print_event_log(priv, next_entry,
  3311. capacity - next_entry, mode);
  3312. /* (then/else) start at top of log */
  3313. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3314. iwl_release_nic_access(priv);
  3315. }
  3316. /**
  3317. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3318. */
  3319. static void iwl3945_irq_handle_error(struct iwl_priv *priv)
  3320. {
  3321. /* Set the FW error flag -- cleared on iwl3945_down */
  3322. set_bit(STATUS_FW_ERROR, &priv->status);
  3323. /* Cancel currently queued command. */
  3324. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3325. #ifdef CONFIG_IWL3945_DEBUG
  3326. if (priv->debug_level & IWL_DL_FW_ERRORS) {
  3327. iwl3945_dump_nic_error_log(priv);
  3328. iwl3945_dump_nic_event_log(priv);
  3329. iwl3945_print_rx_config_cmd(priv, &priv->staging39_rxon);
  3330. }
  3331. #endif
  3332. wake_up_interruptible(&priv->wait_command_queue);
  3333. /* Keep the restart process from trying to send host
  3334. * commands by clearing the INIT status bit */
  3335. clear_bit(STATUS_READY, &priv->status);
  3336. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3337. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3338. "Restarting adapter due to uCode error.\n");
  3339. if (iwl3945_is_associated(priv)) {
  3340. memcpy(&priv->recovery39_rxon, &priv->active39_rxon,
  3341. sizeof(priv->recovery39_rxon));
  3342. priv->error_recovering = 1;
  3343. }
  3344. queue_work(priv->workqueue, &priv->restart);
  3345. }
  3346. }
  3347. static void iwl3945_error_recovery(struct iwl_priv *priv)
  3348. {
  3349. unsigned long flags;
  3350. memcpy(&priv->staging39_rxon, &priv->recovery39_rxon,
  3351. sizeof(priv->staging39_rxon));
  3352. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3353. iwl3945_commit_rxon(priv);
  3354. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3355. spin_lock_irqsave(&priv->lock, flags);
  3356. priv->assoc_id = le16_to_cpu(priv->staging39_rxon.assoc_id);
  3357. priv->error_recovering = 0;
  3358. spin_unlock_irqrestore(&priv->lock, flags);
  3359. }
  3360. static void iwl3945_irq_tasklet(struct iwl_priv *priv)
  3361. {
  3362. u32 inta, handled = 0;
  3363. u32 inta_fh;
  3364. unsigned long flags;
  3365. #ifdef CONFIG_IWL3945_DEBUG
  3366. u32 inta_mask;
  3367. #endif
  3368. spin_lock_irqsave(&priv->lock, flags);
  3369. /* Ack/clear/reset pending uCode interrupts.
  3370. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3371. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3372. inta = iwl_read32(priv, CSR_INT);
  3373. iwl_write32(priv, CSR_INT, inta);
  3374. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3375. * Any new interrupts that happen after this, either while we're
  3376. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3377. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  3378. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3379. #ifdef CONFIG_IWL3945_DEBUG
  3380. if (priv->debug_level & IWL_DL_ISR) {
  3381. /* just for debug */
  3382. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  3383. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3384. inta, inta_mask, inta_fh);
  3385. }
  3386. #endif
  3387. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3388. * atomic, make sure that inta covers all the interrupts that
  3389. * we've discovered, even if FH interrupt came in just after
  3390. * reading CSR_INT. */
  3391. if (inta_fh & CSR39_FH_INT_RX_MASK)
  3392. inta |= CSR_INT_BIT_FH_RX;
  3393. if (inta_fh & CSR39_FH_INT_TX_MASK)
  3394. inta |= CSR_INT_BIT_FH_TX;
  3395. /* Now service all interrupt bits discovered above. */
  3396. if (inta & CSR_INT_BIT_HW_ERR) {
  3397. IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
  3398. /* Tell the device to stop sending interrupts */
  3399. iwl3945_disable_interrupts(priv);
  3400. iwl3945_irq_handle_error(priv);
  3401. handled |= CSR_INT_BIT_HW_ERR;
  3402. spin_unlock_irqrestore(&priv->lock, flags);
  3403. return;
  3404. }
  3405. #ifdef CONFIG_IWL3945_DEBUG
  3406. if (priv->debug_level & (IWL_DL_ISR)) {
  3407. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3408. if (inta & CSR_INT_BIT_SCD)
  3409. IWL_DEBUG_ISR("Scheduler finished to transmit "
  3410. "the frame/frames.\n");
  3411. /* Alive notification via Rx interrupt will do the real work */
  3412. if (inta & CSR_INT_BIT_ALIVE)
  3413. IWL_DEBUG_ISR("Alive interrupt\n");
  3414. }
  3415. #endif
  3416. /* Safely ignore these bits for debug checks below */
  3417. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  3418. /* Error detected by uCode */
  3419. if (inta & CSR_INT_BIT_SW_ERR) {
  3420. IWL_ERR(priv, "Microcode SW error detected. "
  3421. "Restarting 0x%X.\n", inta);
  3422. iwl3945_irq_handle_error(priv);
  3423. handled |= CSR_INT_BIT_SW_ERR;
  3424. }
  3425. /* uCode wakes up after power-down sleep */
  3426. if (inta & CSR_INT_BIT_WAKEUP) {
  3427. IWL_DEBUG_ISR("Wakeup interrupt\n");
  3428. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  3429. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[0]);
  3430. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[1]);
  3431. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[2]);
  3432. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[3]);
  3433. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[4]);
  3434. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[5]);
  3435. handled |= CSR_INT_BIT_WAKEUP;
  3436. }
  3437. /* All uCode command responses, including Tx command responses,
  3438. * Rx "responses" (frame-received notification), and other
  3439. * notifications from uCode come through here*/
  3440. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  3441. iwl3945_rx_handle(priv);
  3442. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  3443. }
  3444. if (inta & CSR_INT_BIT_FH_TX) {
  3445. IWL_DEBUG_ISR("Tx interrupt\n");
  3446. iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  3447. if (!iwl_grab_nic_access(priv)) {
  3448. iwl_write_direct32(priv, FH39_TCSR_CREDIT
  3449. (FH39_SRVC_CHNL), 0x0);
  3450. iwl_release_nic_access(priv);
  3451. }
  3452. handled |= CSR_INT_BIT_FH_TX;
  3453. }
  3454. if (inta & ~handled)
  3455. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  3456. if (inta & ~CSR_INI_SET_MASK) {
  3457. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  3458. inta & ~CSR_INI_SET_MASK);
  3459. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  3460. }
  3461. /* Re-enable all interrupts */
  3462. /* only Re-enable if disabled by irq */
  3463. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3464. iwl3945_enable_interrupts(priv);
  3465. #ifdef CONFIG_IWL3945_DEBUG
  3466. if (priv->debug_level & (IWL_DL_ISR)) {
  3467. inta = iwl_read32(priv, CSR_INT);
  3468. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  3469. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  3470. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  3471. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  3472. }
  3473. #endif
  3474. spin_unlock_irqrestore(&priv->lock, flags);
  3475. }
  3476. static irqreturn_t iwl3945_isr(int irq, void *data)
  3477. {
  3478. struct iwl_priv *priv = data;
  3479. u32 inta, inta_mask;
  3480. u32 inta_fh;
  3481. if (!priv)
  3482. return IRQ_NONE;
  3483. spin_lock(&priv->lock);
  3484. /* Disable (but don't clear!) interrupts here to avoid
  3485. * back-to-back ISRs and sporadic interrupts from our NIC.
  3486. * If we have something to service, the tasklet will re-enable ints.
  3487. * If we *don't* have something, we'll re-enable before leaving here. */
  3488. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  3489. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  3490. /* Discover which interrupts are active/pending */
  3491. inta = iwl_read32(priv, CSR_INT);
  3492. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  3493. /* Ignore interrupt if there's nothing in NIC to service.
  3494. * This may be due to IRQ shared with another device,
  3495. * or due to sporadic interrupts thrown from our NIC. */
  3496. if (!inta && !inta_fh) {
  3497. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  3498. goto none;
  3499. }
  3500. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  3501. /* Hardware disappeared */
  3502. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  3503. goto unplugged;
  3504. }
  3505. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3506. inta, inta_mask, inta_fh);
  3507. inta &= ~CSR_INT_BIT_SCD;
  3508. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  3509. if (likely(inta || inta_fh))
  3510. tasklet_schedule(&priv->irq_tasklet);
  3511. unplugged:
  3512. spin_unlock(&priv->lock);
  3513. return IRQ_HANDLED;
  3514. none:
  3515. /* re-enable interrupts here since we don't have anything to service. */
  3516. /* only Re-enable if disabled by irq */
  3517. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3518. iwl3945_enable_interrupts(priv);
  3519. spin_unlock(&priv->lock);
  3520. return IRQ_NONE;
  3521. }
  3522. /************************** EEPROM BANDS ****************************
  3523. *
  3524. * The iwl3945_eeprom_band definitions below provide the mapping from the
  3525. * EEPROM contents to the specific channel number supported for each
  3526. * band.
  3527. *
  3528. * For example, iwl3945_priv->eeprom39.band_3_channels[4] from the band_3
  3529. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  3530. * The specific geography and calibration information for that channel
  3531. * is contained in the eeprom map itself.
  3532. *
  3533. * During init, we copy the eeprom information and channel map
  3534. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  3535. *
  3536. * channel_map_24/52 provides the index in the channel_info array for a
  3537. * given channel. We have to have two separate maps as there is channel
  3538. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  3539. * band_2
  3540. *
  3541. * A value of 0xff stored in the channel_map indicates that the channel
  3542. * is not supported by the hardware at all.
  3543. *
  3544. * A value of 0xfe in the channel_map indicates that the channel is not
  3545. * valid for Tx with the current hardware. This means that
  3546. * while the system can tune and receive on a given channel, it may not
  3547. * be able to associate or transmit any frames on that
  3548. * channel. There is no corresponding channel information for that
  3549. * entry.
  3550. *
  3551. *********************************************************************/
  3552. /* 2.4 GHz */
  3553. static const u8 iwl3945_eeprom_band_1[14] = {
  3554. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  3555. };
  3556. /* 5.2 GHz bands */
  3557. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  3558. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  3559. };
  3560. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  3561. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  3562. };
  3563. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  3564. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  3565. };
  3566. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  3567. 145, 149, 153, 157, 161, 165
  3568. };
  3569. static void iwl3945_init_band_reference(const struct iwl_priv *priv, int band,
  3570. int *eeprom_ch_count,
  3571. const struct iwl_eeprom_channel
  3572. **eeprom_ch_info,
  3573. const u8 **eeprom_ch_index)
  3574. {
  3575. switch (band) {
  3576. case 1: /* 2.4GHz band */
  3577. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  3578. *eeprom_ch_info = priv->eeprom39.band_1_channels;
  3579. *eeprom_ch_index = iwl3945_eeprom_band_1;
  3580. break;
  3581. case 2: /* 4.9GHz band */
  3582. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  3583. *eeprom_ch_info = priv->eeprom39.band_2_channels;
  3584. *eeprom_ch_index = iwl3945_eeprom_band_2;
  3585. break;
  3586. case 3: /* 5.2GHz band */
  3587. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  3588. *eeprom_ch_info = priv->eeprom39.band_3_channels;
  3589. *eeprom_ch_index = iwl3945_eeprom_band_3;
  3590. break;
  3591. case 4: /* 5.5GHz band */
  3592. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  3593. *eeprom_ch_info = priv->eeprom39.band_4_channels;
  3594. *eeprom_ch_index = iwl3945_eeprom_band_4;
  3595. break;
  3596. case 5: /* 5.7GHz band */
  3597. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  3598. *eeprom_ch_info = priv->eeprom39.band_5_channels;
  3599. *eeprom_ch_index = iwl3945_eeprom_band_5;
  3600. break;
  3601. default:
  3602. BUG();
  3603. return;
  3604. }
  3605. }
  3606. /**
  3607. * iwl3945_get_channel_info - Find driver's private channel info
  3608. *
  3609. * Based on band and channel number.
  3610. */
  3611. const struct iwl_channel_info *
  3612. iwl3945_get_channel_info(const struct iwl_priv *priv,
  3613. enum ieee80211_band band, u16 channel)
  3614. {
  3615. int i;
  3616. switch (band) {
  3617. case IEEE80211_BAND_5GHZ:
  3618. for (i = 14; i < priv->channel_count; i++) {
  3619. if (priv->channel_info[i].channel == channel)
  3620. return &priv->channel_info[i];
  3621. }
  3622. break;
  3623. case IEEE80211_BAND_2GHZ:
  3624. if (channel >= 1 && channel <= 14)
  3625. return &priv->channel_info[channel - 1];
  3626. break;
  3627. case IEEE80211_NUM_BANDS:
  3628. WARN_ON(1);
  3629. }
  3630. return NULL;
  3631. }
  3632. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  3633. ? # x " " : "")
  3634. /**
  3635. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  3636. */
  3637. static int iwl3945_init_channel_map(struct iwl_priv *priv)
  3638. {
  3639. int eeprom_ch_count = 0;
  3640. const u8 *eeprom_ch_index = NULL;
  3641. const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
  3642. int band, ch;
  3643. struct iwl_channel_info *ch_info;
  3644. if (priv->channel_count) {
  3645. IWL_DEBUG_INFO("Channel map already initialized.\n");
  3646. return 0;
  3647. }
  3648. if (priv->eeprom39.version < 0x2f) {
  3649. IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
  3650. priv->eeprom39.version);
  3651. return -EINVAL;
  3652. }
  3653. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  3654. priv->channel_count =
  3655. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  3656. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  3657. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  3658. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  3659. ARRAY_SIZE(iwl3945_eeprom_band_5);
  3660. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  3661. priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) *
  3662. priv->channel_count, GFP_KERNEL);
  3663. if (!priv->channel_info) {
  3664. IWL_ERR(priv, "Could not allocate channel_info\n");
  3665. priv->channel_count = 0;
  3666. return -ENOMEM;
  3667. }
  3668. ch_info = priv->channel_info;
  3669. /* Loop through the 5 EEPROM bands adding them in order to the
  3670. * channel map we maintain (that contains additional information than
  3671. * what just in the EEPROM) */
  3672. for (band = 1; band <= 5; band++) {
  3673. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  3674. &eeprom_ch_info, &eeprom_ch_index);
  3675. /* Loop through each band adding each of the channels */
  3676. for (ch = 0; ch < eeprom_ch_count; ch++) {
  3677. ch_info->channel = eeprom_ch_index[ch];
  3678. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  3679. IEEE80211_BAND_5GHZ;
  3680. /* permanently store EEPROM's channel regulatory flags
  3681. * and max power in channel info database. */
  3682. ch_info->eeprom = eeprom_ch_info[ch];
  3683. /* Copy the run-time flags so they are there even on
  3684. * invalid channels */
  3685. ch_info->flags = eeprom_ch_info[ch].flags;
  3686. if (!(is_channel_valid(ch_info))) {
  3687. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  3688. "No traffic\n",
  3689. ch_info->channel,
  3690. ch_info->flags,
  3691. is_channel_a_band(ch_info) ?
  3692. "5.2" : "2.4");
  3693. ch_info++;
  3694. continue;
  3695. }
  3696. /* Initialize regulatory-based run-time data */
  3697. ch_info->max_power_avg = ch_info->curr_txpow =
  3698. eeprom_ch_info[ch].max_power_avg;
  3699. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  3700. ch_info->min_power = 0;
  3701. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  3702. " %ddBm): Ad-Hoc %ssupported\n",
  3703. ch_info->channel,
  3704. is_channel_a_band(ch_info) ?
  3705. "5.2" : "2.4",
  3706. CHECK_AND_PRINT(VALID),
  3707. CHECK_AND_PRINT(IBSS),
  3708. CHECK_AND_PRINT(ACTIVE),
  3709. CHECK_AND_PRINT(RADAR),
  3710. CHECK_AND_PRINT(WIDE),
  3711. CHECK_AND_PRINT(DFS),
  3712. eeprom_ch_info[ch].flags,
  3713. eeprom_ch_info[ch].max_power_avg,
  3714. ((eeprom_ch_info[ch].
  3715. flags & EEPROM_CHANNEL_IBSS)
  3716. && !(eeprom_ch_info[ch].
  3717. flags & EEPROM_CHANNEL_RADAR))
  3718. ? "" : "not ");
  3719. /* Set the user_txpower_limit to the highest power
  3720. * supported by any channel */
  3721. if (eeprom_ch_info[ch].max_power_avg >
  3722. priv->user_txpower_limit)
  3723. priv->user_txpower_limit =
  3724. eeprom_ch_info[ch].max_power_avg;
  3725. ch_info++;
  3726. }
  3727. }
  3728. /* Set up txpower settings in driver for all channels */
  3729. if (iwl3945_txpower_set_from_eeprom(priv))
  3730. return -EIO;
  3731. return 0;
  3732. }
  3733. /*
  3734. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  3735. */
  3736. static void iwl3945_free_channel_map(struct iwl_priv *priv)
  3737. {
  3738. kfree(priv->channel_info);
  3739. priv->channel_count = 0;
  3740. }
  3741. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  3742. * sending probe req. This should be set long enough to hear probe responses
  3743. * from more than one AP. */
  3744. #define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
  3745. #define IWL_ACTIVE_DWELL_TIME_52 (20)
  3746. #define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
  3747. #define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
  3748. /* For faster active scanning, scan will move to the next channel if fewer than
  3749. * PLCP_QUIET_THRESH packets are heard on this channel within
  3750. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  3751. * time if it's a quiet channel (nothing responded to our probe, and there's
  3752. * no other traffic).
  3753. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  3754. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  3755. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
  3756. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  3757. * Must be set longer than active dwell time.
  3758. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  3759. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  3760. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  3761. #define IWL_PASSIVE_DWELL_BASE (100)
  3762. #define IWL_CHANNEL_TUNE_TIME 5
  3763. #define IWL_SCAN_PROBE_MASK(n) (BIT(n) | (BIT(n) - BIT(1)))
  3764. static inline u16 iwl3945_get_active_dwell_time(struct iwl_priv *priv,
  3765. enum ieee80211_band band,
  3766. u8 n_probes)
  3767. {
  3768. if (band == IEEE80211_BAND_5GHZ)
  3769. return IWL_ACTIVE_DWELL_TIME_52 +
  3770. IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
  3771. else
  3772. return IWL_ACTIVE_DWELL_TIME_24 +
  3773. IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
  3774. }
  3775. static u16 iwl3945_get_passive_dwell_time(struct iwl_priv *priv,
  3776. enum ieee80211_band band)
  3777. {
  3778. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  3779. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  3780. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  3781. if (iwl3945_is_associated(priv)) {
  3782. /* If we're associated, we clamp the maximum passive
  3783. * dwell time to be 98% of the beacon interval (minus
  3784. * 2 * channel tune time) */
  3785. passive = priv->beacon_int;
  3786. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  3787. passive = IWL_PASSIVE_DWELL_BASE;
  3788. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  3789. }
  3790. return passive;
  3791. }
  3792. static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
  3793. enum ieee80211_band band,
  3794. u8 is_active, u8 n_probes,
  3795. struct iwl3945_scan_channel *scan_ch)
  3796. {
  3797. const struct ieee80211_channel *channels = NULL;
  3798. const struct ieee80211_supported_band *sband;
  3799. const struct iwl_channel_info *ch_info;
  3800. u16 passive_dwell = 0;
  3801. u16 active_dwell = 0;
  3802. int added, i;
  3803. sband = iwl_get_hw_mode(priv, band);
  3804. if (!sband)
  3805. return 0;
  3806. channels = sband->channels;
  3807. active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
  3808. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  3809. if (passive_dwell <= active_dwell)
  3810. passive_dwell = active_dwell + 1;
  3811. for (i = 0, added = 0; i < sband->n_channels; i++) {
  3812. if (channels[i].flags & IEEE80211_CHAN_DISABLED)
  3813. continue;
  3814. scan_ch->channel = channels[i].hw_value;
  3815. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  3816. if (!is_channel_valid(ch_info)) {
  3817. IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
  3818. scan_ch->channel);
  3819. continue;
  3820. }
  3821. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  3822. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  3823. /* If passive , set up for auto-switch
  3824. * and use long active_dwell time.
  3825. */
  3826. if (!is_active || is_channel_passive(ch_info) ||
  3827. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
  3828. scan_ch->type = 0; /* passive */
  3829. if (IWL_UCODE_API(priv->ucode_ver) == 1)
  3830. scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
  3831. } else {
  3832. scan_ch->type = 1; /* active */
  3833. }
  3834. /* Set direct probe bits. These may be used both for active
  3835. * scan channels (probes gets sent right away),
  3836. * or for passive channels (probes get se sent only after
  3837. * hearing clear Rx packet).*/
  3838. if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
  3839. if (n_probes)
  3840. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  3841. } else {
  3842. /* uCode v1 does not allow setting direct probe bits on
  3843. * passive channel. */
  3844. if ((scan_ch->type & 1) && n_probes)
  3845. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  3846. }
  3847. /* Set txpower levels to defaults */
  3848. scan_ch->tpc.dsp_atten = 110;
  3849. /* scan_pwr_info->tpc.dsp_atten; */
  3850. /*scan_pwr_info->tpc.tx_gain; */
  3851. if (band == IEEE80211_BAND_5GHZ)
  3852. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  3853. else {
  3854. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  3855. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  3856. * power level:
  3857. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  3858. */
  3859. }
  3860. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  3861. scan_ch->channel,
  3862. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  3863. (scan_ch->type & 1) ?
  3864. active_dwell : passive_dwell);
  3865. scan_ch++;
  3866. added++;
  3867. }
  3868. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  3869. return added;
  3870. }
  3871. static void iwl3945_init_hw_rates(struct iwl_priv *priv,
  3872. struct ieee80211_rate *rates)
  3873. {
  3874. int i;
  3875. for (i = 0; i < IWL_RATE_COUNT; i++) {
  3876. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  3877. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  3878. rates[i].hw_value_short = i;
  3879. rates[i].flags = 0;
  3880. if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  3881. /*
  3882. * If CCK != 1M then set short preamble rate flag.
  3883. */
  3884. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  3885. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  3886. }
  3887. }
  3888. }
  3889. /**
  3890. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  3891. */
  3892. static int iwl3945_init_geos(struct iwl_priv *priv)
  3893. {
  3894. struct iwl_channel_info *ch;
  3895. struct ieee80211_supported_band *sband;
  3896. struct ieee80211_channel *channels;
  3897. struct ieee80211_channel *geo_ch;
  3898. struct ieee80211_rate *rates;
  3899. int i = 0;
  3900. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  3901. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  3902. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  3903. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  3904. return 0;
  3905. }
  3906. channels = kzalloc(sizeof(struct ieee80211_channel) *
  3907. priv->channel_count, GFP_KERNEL);
  3908. if (!channels)
  3909. return -ENOMEM;
  3910. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  3911. GFP_KERNEL);
  3912. if (!rates) {
  3913. kfree(channels);
  3914. return -ENOMEM;
  3915. }
  3916. /* 5.2GHz channels start after the 2.4GHz channels */
  3917. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  3918. sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  3919. /* just OFDM */
  3920. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  3921. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  3922. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  3923. sband->channels = channels;
  3924. /* OFDM & CCK */
  3925. sband->bitrates = rates;
  3926. sband->n_bitrates = IWL_RATE_COUNT;
  3927. priv->ieee_channels = channels;
  3928. priv->ieee_rates = rates;
  3929. iwl3945_init_hw_rates(priv, rates);
  3930. for (i = 0; i < priv->channel_count; i++) {
  3931. ch = &priv->channel_info[i];
  3932. /* FIXME: might be removed if scan is OK*/
  3933. if (!is_channel_valid(ch))
  3934. continue;
  3935. if (is_channel_a_band(ch))
  3936. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  3937. else
  3938. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  3939. geo_ch = &sband->channels[sband->n_channels++];
  3940. geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
  3941. geo_ch->max_power = ch->max_power_avg;
  3942. geo_ch->max_antenna_gain = 0xff;
  3943. geo_ch->hw_value = ch->channel;
  3944. if (is_channel_valid(ch)) {
  3945. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  3946. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  3947. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  3948. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  3949. if (ch->flags & EEPROM_CHANNEL_RADAR)
  3950. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  3951. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  3952. priv->max_channel_txpower_limit =
  3953. ch->max_power_avg;
  3954. } else {
  3955. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  3956. }
  3957. /* Save flags for reg domain usage */
  3958. geo_ch->orig_flags = geo_ch->flags;
  3959. IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
  3960. ch->channel, geo_ch->center_freq,
  3961. is_channel_a_band(ch) ? "5.2" : "2.4",
  3962. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  3963. "restricted" : "valid",
  3964. geo_ch->flags);
  3965. }
  3966. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  3967. priv->cfg->sku & IWL_SKU_A) {
  3968. IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
  3969. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  3970. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  3971. priv->cfg->sku &= ~IWL_SKU_A;
  3972. }
  3973. IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  3974. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  3975. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  3976. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  3977. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  3978. &priv->bands[IEEE80211_BAND_2GHZ];
  3979. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  3980. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  3981. &priv->bands[IEEE80211_BAND_5GHZ];
  3982. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  3983. return 0;
  3984. }
  3985. /*
  3986. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  3987. */
  3988. static void iwl3945_free_geos(struct iwl_priv *priv)
  3989. {
  3990. kfree(priv->ieee_channels);
  3991. kfree(priv->ieee_rates);
  3992. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  3993. }
  3994. /******************************************************************************
  3995. *
  3996. * uCode download functions
  3997. *
  3998. ******************************************************************************/
  3999. static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
  4000. {
  4001. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  4002. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  4003. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4004. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  4005. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4006. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4007. }
  4008. /**
  4009. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4010. * looking at all data.
  4011. */
  4012. static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
  4013. {
  4014. u32 val;
  4015. u32 save_len = len;
  4016. int rc = 0;
  4017. u32 errcnt;
  4018. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4019. rc = iwl_grab_nic_access(priv);
  4020. if (rc)
  4021. return rc;
  4022. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4023. IWL39_RTC_INST_LOWER_BOUND);
  4024. errcnt = 0;
  4025. for (; len > 0; len -= sizeof(u32), image++) {
  4026. /* read data comes through single port, auto-incr addr */
  4027. /* NOTE: Use the debugless read so we don't flood kernel log
  4028. * if IWL_DL_IO is set */
  4029. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4030. if (val != le32_to_cpu(*image)) {
  4031. IWL_ERR(priv, "uCode INST section is invalid at "
  4032. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4033. save_len - len, val, le32_to_cpu(*image));
  4034. rc = -EIO;
  4035. errcnt++;
  4036. if (errcnt >= 20)
  4037. break;
  4038. }
  4039. }
  4040. iwl_release_nic_access(priv);
  4041. if (!errcnt)
  4042. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4043. return rc;
  4044. }
  4045. /**
  4046. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4047. * using sample data 100 bytes apart. If these sample points are good,
  4048. * it's a pretty good bet that everything between them is good, too.
  4049. */
  4050. static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  4051. {
  4052. u32 val;
  4053. int rc = 0;
  4054. u32 errcnt = 0;
  4055. u32 i;
  4056. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4057. rc = iwl_grab_nic_access(priv);
  4058. if (rc)
  4059. return rc;
  4060. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4061. /* read data comes through single port, auto-incr addr */
  4062. /* NOTE: Use the debugless read so we don't flood kernel log
  4063. * if IWL_DL_IO is set */
  4064. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4065. i + IWL39_RTC_INST_LOWER_BOUND);
  4066. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4067. if (val != le32_to_cpu(*image)) {
  4068. #if 0 /* Enable this if you want to see details */
  4069. IWL_ERR(priv, "uCode INST section is invalid at "
  4070. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4071. i, val, *image);
  4072. #endif
  4073. rc = -EIO;
  4074. errcnt++;
  4075. if (errcnt >= 3)
  4076. break;
  4077. }
  4078. }
  4079. iwl_release_nic_access(priv);
  4080. return rc;
  4081. }
  4082. /**
  4083. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4084. * and verify its contents
  4085. */
  4086. static int iwl3945_verify_ucode(struct iwl_priv *priv)
  4087. {
  4088. __le32 *image;
  4089. u32 len;
  4090. int rc = 0;
  4091. /* Try bootstrap */
  4092. image = (__le32 *)priv->ucode_boot.v_addr;
  4093. len = priv->ucode_boot.len;
  4094. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4095. if (rc == 0) {
  4096. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4097. return 0;
  4098. }
  4099. /* Try initialize */
  4100. image = (__le32 *)priv->ucode_init.v_addr;
  4101. len = priv->ucode_init.len;
  4102. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4103. if (rc == 0) {
  4104. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4105. return 0;
  4106. }
  4107. /* Try runtime/protocol */
  4108. image = (__le32 *)priv->ucode_code.v_addr;
  4109. len = priv->ucode_code.len;
  4110. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4111. if (rc == 0) {
  4112. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4113. return 0;
  4114. }
  4115. IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4116. /* Since nothing seems to match, show first several data entries in
  4117. * instruction SRAM, so maybe visual inspection will give a clue.
  4118. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4119. image = (__le32 *)priv->ucode_boot.v_addr;
  4120. len = priv->ucode_boot.len;
  4121. rc = iwl3945_verify_inst_full(priv, image, len);
  4122. return rc;
  4123. }
  4124. static void iwl3945_nic_start(struct iwl_priv *priv)
  4125. {
  4126. /* Remove all resets to allow NIC to operate */
  4127. iwl_write32(priv, CSR_RESET, 0);
  4128. }
  4129. /**
  4130. * iwl3945_read_ucode - Read uCode images from disk file.
  4131. *
  4132. * Copy into buffers for card to fetch via bus-mastering
  4133. */
  4134. static int iwl3945_read_ucode(struct iwl_priv *priv)
  4135. {
  4136. struct iwl_ucode *ucode;
  4137. int ret = -EINVAL, index;
  4138. const struct firmware *ucode_raw;
  4139. /* firmware file name contains uCode/driver compatibility version */
  4140. const char *name_pre = priv->cfg->fw_name_pre;
  4141. const unsigned int api_max = priv->cfg->ucode_api_max;
  4142. const unsigned int api_min = priv->cfg->ucode_api_min;
  4143. char buf[25];
  4144. u8 *src;
  4145. size_t len;
  4146. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4147. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4148. * request_firmware() is synchronous, file is in memory on return. */
  4149. for (index = api_max; index >= api_min; index--) {
  4150. sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
  4151. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  4152. if (ret < 0) {
  4153. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  4154. buf, ret);
  4155. if (ret == -ENOENT)
  4156. continue;
  4157. else
  4158. goto error;
  4159. } else {
  4160. if (index < api_max)
  4161. IWL_ERR(priv, "Loaded firmware %s, "
  4162. "which is deprecated. "
  4163. " Please use API v%u instead.\n",
  4164. buf, api_max);
  4165. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4166. buf, ucode_raw->size);
  4167. break;
  4168. }
  4169. }
  4170. if (ret < 0)
  4171. goto error;
  4172. /* Make sure that we got at least our header! */
  4173. if (ucode_raw->size < sizeof(*ucode)) {
  4174. IWL_ERR(priv, "File size way too small!\n");
  4175. ret = -EINVAL;
  4176. goto err_release;
  4177. }
  4178. /* Data from ucode file: header followed by uCode images */
  4179. ucode = (void *)ucode_raw->data;
  4180. priv->ucode_ver = le32_to_cpu(ucode->ver);
  4181. api_ver = IWL_UCODE_API(priv->ucode_ver);
  4182. inst_size = le32_to_cpu(ucode->inst_size);
  4183. data_size = le32_to_cpu(ucode->data_size);
  4184. init_size = le32_to_cpu(ucode->init_size);
  4185. init_data_size = le32_to_cpu(ucode->init_data_size);
  4186. boot_size = le32_to_cpu(ucode->boot_size);
  4187. /* api_ver should match the api version forming part of the
  4188. * firmware filename ... but we don't check for that and only rely
  4189. * on the API version read from firware header from here on forward */
  4190. if (api_ver < api_min || api_ver > api_max) {
  4191. IWL_ERR(priv, "Driver unable to support your firmware API. "
  4192. "Driver supports v%u, firmware is v%u.\n",
  4193. api_max, api_ver);
  4194. priv->ucode_ver = 0;
  4195. ret = -EINVAL;
  4196. goto err_release;
  4197. }
  4198. if (api_ver != api_max)
  4199. IWL_ERR(priv, "Firmware has old API version. Expected %u, "
  4200. "got %u. New firmware can be obtained "
  4201. "from http://www.intellinuxwireless.org.\n",
  4202. api_max, api_ver);
  4203. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  4204. IWL_UCODE_MAJOR(priv->ucode_ver),
  4205. IWL_UCODE_MINOR(priv->ucode_ver),
  4206. IWL_UCODE_API(priv->ucode_ver),
  4207. IWL_UCODE_SERIAL(priv->ucode_ver));
  4208. IWL_DEBUG_INFO("f/w package hdr ucode version raw = 0x%x\n",
  4209. priv->ucode_ver);
  4210. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4211. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4212. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4213. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4214. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4215. /* Verify size of file vs. image size info in file's header */
  4216. if (ucode_raw->size < sizeof(*ucode) +
  4217. inst_size + data_size + init_size +
  4218. init_data_size + boot_size) {
  4219. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4220. (int)ucode_raw->size);
  4221. ret = -EINVAL;
  4222. goto err_release;
  4223. }
  4224. /* Verify that uCode images will fit in card's SRAM */
  4225. if (inst_size > IWL39_MAX_INST_SIZE) {
  4226. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4227. inst_size);
  4228. ret = -EINVAL;
  4229. goto err_release;
  4230. }
  4231. if (data_size > IWL39_MAX_DATA_SIZE) {
  4232. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4233. data_size);
  4234. ret = -EINVAL;
  4235. goto err_release;
  4236. }
  4237. if (init_size > IWL39_MAX_INST_SIZE) {
  4238. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4239. init_size);
  4240. ret = -EINVAL;
  4241. goto err_release;
  4242. }
  4243. if (init_data_size > IWL39_MAX_DATA_SIZE) {
  4244. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4245. init_data_size);
  4246. ret = -EINVAL;
  4247. goto err_release;
  4248. }
  4249. if (boot_size > IWL39_MAX_BSM_SIZE) {
  4250. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4251. boot_size);
  4252. ret = -EINVAL;
  4253. goto err_release;
  4254. }
  4255. /* Allocate ucode buffers for card's bus-master loading ... */
  4256. /* Runtime instructions and 2 copies of data:
  4257. * 1) unmodified from disk
  4258. * 2) backup cache for save/restore during power-downs */
  4259. priv->ucode_code.len = inst_size;
  4260. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4261. priv->ucode_data.len = data_size;
  4262. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4263. priv->ucode_data_backup.len = data_size;
  4264. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4265. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4266. !priv->ucode_data_backup.v_addr)
  4267. goto err_pci_alloc;
  4268. /* Initialization instructions and data */
  4269. if (init_size && init_data_size) {
  4270. priv->ucode_init.len = init_size;
  4271. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4272. priv->ucode_init_data.len = init_data_size;
  4273. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4274. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4275. goto err_pci_alloc;
  4276. }
  4277. /* Bootstrap (instructions only, no data) */
  4278. if (boot_size) {
  4279. priv->ucode_boot.len = boot_size;
  4280. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4281. if (!priv->ucode_boot.v_addr)
  4282. goto err_pci_alloc;
  4283. }
  4284. /* Copy images into buffers for card's bus-master reads ... */
  4285. /* Runtime instructions (first block of data in file) */
  4286. src = &ucode->data[0];
  4287. len = priv->ucode_code.len;
  4288. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4289. memcpy(priv->ucode_code.v_addr, src, len);
  4290. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4291. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4292. /* Runtime data (2nd block)
  4293. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4294. src = &ucode->data[inst_size];
  4295. len = priv->ucode_data.len;
  4296. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4297. memcpy(priv->ucode_data.v_addr, src, len);
  4298. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4299. /* Initialization instructions (3rd block) */
  4300. if (init_size) {
  4301. src = &ucode->data[inst_size + data_size];
  4302. len = priv->ucode_init.len;
  4303. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4304. len);
  4305. memcpy(priv->ucode_init.v_addr, src, len);
  4306. }
  4307. /* Initialization data (4th block) */
  4308. if (init_data_size) {
  4309. src = &ucode->data[inst_size + data_size + init_size];
  4310. len = priv->ucode_init_data.len;
  4311. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4312. (int)len);
  4313. memcpy(priv->ucode_init_data.v_addr, src, len);
  4314. }
  4315. /* Bootstrap instructions (5th block) */
  4316. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4317. len = priv->ucode_boot.len;
  4318. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4319. (int)len);
  4320. memcpy(priv->ucode_boot.v_addr, src, len);
  4321. /* We have our copies now, allow OS release its copies */
  4322. release_firmware(ucode_raw);
  4323. return 0;
  4324. err_pci_alloc:
  4325. IWL_ERR(priv, "failed to allocate pci memory\n");
  4326. ret = -ENOMEM;
  4327. iwl3945_dealloc_ucode_pci(priv);
  4328. err_release:
  4329. release_firmware(ucode_raw);
  4330. error:
  4331. return ret;
  4332. }
  4333. /**
  4334. * iwl3945_set_ucode_ptrs - Set uCode address location
  4335. *
  4336. * Tell initialization uCode where to find runtime uCode.
  4337. *
  4338. * BSM registers initially contain pointers to initialization uCode.
  4339. * We need to replace them to load runtime uCode inst and data,
  4340. * and to save runtime data when powering down.
  4341. */
  4342. static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
  4343. {
  4344. dma_addr_t pinst;
  4345. dma_addr_t pdata;
  4346. int rc = 0;
  4347. unsigned long flags;
  4348. /* bits 31:0 for 3945 */
  4349. pinst = priv->ucode_code.p_addr;
  4350. pdata = priv->ucode_data_backup.p_addr;
  4351. spin_lock_irqsave(&priv->lock, flags);
  4352. rc = iwl_grab_nic_access(priv);
  4353. if (rc) {
  4354. spin_unlock_irqrestore(&priv->lock, flags);
  4355. return rc;
  4356. }
  4357. /* Tell bootstrap uCode where to find image to load */
  4358. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4359. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4360. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  4361. priv->ucode_data.len);
  4362. /* Inst byte count must be last to set up, bit 31 signals uCode
  4363. * that all new ptr/size info is in place */
  4364. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  4365. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  4366. iwl_release_nic_access(priv);
  4367. spin_unlock_irqrestore(&priv->lock, flags);
  4368. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  4369. return rc;
  4370. }
  4371. /**
  4372. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  4373. *
  4374. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  4375. *
  4376. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  4377. */
  4378. static void iwl3945_init_alive_start(struct iwl_priv *priv)
  4379. {
  4380. /* Check alive response for "valid" sign from uCode */
  4381. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  4382. /* We had an error bringing up the hardware, so take it
  4383. * all the way back down so we can try again */
  4384. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  4385. goto restart;
  4386. }
  4387. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  4388. * This is a paranoid check, because we would not have gotten the
  4389. * "initialize" alive if code weren't properly loaded. */
  4390. if (iwl3945_verify_ucode(priv)) {
  4391. /* Runtime instruction load was bad;
  4392. * take it all the way back down so we can try again */
  4393. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  4394. goto restart;
  4395. }
  4396. /* Send pointers to protocol/runtime uCode image ... init code will
  4397. * load and launch runtime uCode, which will send us another "Alive"
  4398. * notification. */
  4399. IWL_DEBUG_INFO("Initialization Alive received.\n");
  4400. if (iwl3945_set_ucode_ptrs(priv)) {
  4401. /* Runtime instruction load won't happen;
  4402. * take it all the way back down so we can try again */
  4403. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  4404. goto restart;
  4405. }
  4406. return;
  4407. restart:
  4408. queue_work(priv->workqueue, &priv->restart);
  4409. }
  4410. /* temporary */
  4411. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw,
  4412. struct sk_buff *skb);
  4413. /**
  4414. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  4415. * from protocol/runtime uCode (initialization uCode's
  4416. * Alive gets handled by iwl3945_init_alive_start()).
  4417. */
  4418. static void iwl3945_alive_start(struct iwl_priv *priv)
  4419. {
  4420. int rc = 0;
  4421. int thermal_spin = 0;
  4422. u32 rfkill;
  4423. IWL_DEBUG_INFO("Runtime Alive received.\n");
  4424. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  4425. /* We had an error bringing up the hardware, so take it
  4426. * all the way back down so we can try again */
  4427. IWL_DEBUG_INFO("Alive failed.\n");
  4428. goto restart;
  4429. }
  4430. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  4431. * This is a paranoid check, because we would not have gotten the
  4432. * "runtime" alive if code weren't properly loaded. */
  4433. if (iwl3945_verify_ucode(priv)) {
  4434. /* Runtime instruction load was bad;
  4435. * take it all the way back down so we can try again */
  4436. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  4437. goto restart;
  4438. }
  4439. iwl3945_clear_stations_table(priv);
  4440. rc = iwl_grab_nic_access(priv);
  4441. if (rc) {
  4442. IWL_WARN(priv, "Can not read RFKILL status from adapter\n");
  4443. return;
  4444. }
  4445. rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
  4446. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  4447. iwl_release_nic_access(priv);
  4448. if (rfkill & 0x1) {
  4449. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4450. /* if RFKILL is not on, then wait for thermal
  4451. * sensor in adapter to kick in */
  4452. while (iwl3945_hw_get_temperature(priv) == 0) {
  4453. thermal_spin++;
  4454. udelay(10);
  4455. }
  4456. if (thermal_spin)
  4457. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  4458. thermal_spin * 10);
  4459. } else
  4460. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4461. /* After the ALIVE response, we can send commands to 3945 uCode */
  4462. set_bit(STATUS_ALIVE, &priv->status);
  4463. /* Clear out the uCode error bit if it is set */
  4464. clear_bit(STATUS_FW_ERROR, &priv->status);
  4465. if (iwl_is_rfkill(priv))
  4466. return;
  4467. ieee80211_wake_queues(priv->hw);
  4468. priv->active_rate = priv->rates_mask;
  4469. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  4470. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  4471. if (iwl3945_is_associated(priv)) {
  4472. struct iwl3945_rxon_cmd *active_rxon =
  4473. (struct iwl3945_rxon_cmd *)(&priv->active39_rxon);
  4474. memcpy(&priv->staging39_rxon, &priv->active39_rxon,
  4475. sizeof(priv->staging39_rxon));
  4476. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4477. } else {
  4478. /* Initialize our rx_config data */
  4479. iwl3945_connection_init_rx_config(priv, priv->iw_mode);
  4480. memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  4481. }
  4482. /* Configure Bluetooth device coexistence support */
  4483. iwl3945_send_bt_config(priv);
  4484. /* Configure the adapter for unassociated operation */
  4485. iwl3945_commit_rxon(priv);
  4486. iwl3945_reg_txpower_periodic(priv);
  4487. iwl3945_led_register(priv);
  4488. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  4489. set_bit(STATUS_READY, &priv->status);
  4490. wake_up_interruptible(&priv->wait_command_queue);
  4491. if (priv->error_recovering)
  4492. iwl3945_error_recovery(priv);
  4493. /* reassociate for ADHOC mode */
  4494. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  4495. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  4496. priv->vif);
  4497. if (beacon)
  4498. iwl3945_mac_beacon_update(priv->hw, beacon);
  4499. }
  4500. return;
  4501. restart:
  4502. queue_work(priv->workqueue, &priv->restart);
  4503. }
  4504. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
  4505. static void __iwl3945_down(struct iwl_priv *priv)
  4506. {
  4507. unsigned long flags;
  4508. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  4509. struct ieee80211_conf *conf = NULL;
  4510. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  4511. conf = ieee80211_get_hw_conf(priv->hw);
  4512. if (!exit_pending)
  4513. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4514. iwl3945_led_unregister(priv);
  4515. iwl3945_clear_stations_table(priv);
  4516. /* Unblock any waiting calls */
  4517. wake_up_interruptible_all(&priv->wait_command_queue);
  4518. /* Wipe out the EXIT_PENDING status bit if we are not actually
  4519. * exiting the module */
  4520. if (!exit_pending)
  4521. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4522. /* stop and reset the on-board processor */
  4523. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  4524. /* tell the device to stop sending interrupts */
  4525. spin_lock_irqsave(&priv->lock, flags);
  4526. iwl3945_disable_interrupts(priv);
  4527. spin_unlock_irqrestore(&priv->lock, flags);
  4528. iwl_synchronize_irq(priv);
  4529. if (priv->mac80211_registered)
  4530. ieee80211_stop_queues(priv->hw);
  4531. /* If we have not previously called iwl3945_init() then
  4532. * clear all bits but the RF Kill and SUSPEND bits and return */
  4533. if (!iwl_is_init(priv)) {
  4534. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4535. STATUS_RF_KILL_HW |
  4536. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4537. STATUS_RF_KILL_SW |
  4538. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4539. STATUS_GEO_CONFIGURED |
  4540. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4541. STATUS_IN_SUSPEND |
  4542. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4543. STATUS_EXIT_PENDING;
  4544. goto exit;
  4545. }
  4546. /* ...otherwise clear out all the status bits but the RF Kill and
  4547. * SUSPEND bits and continue taking the NIC down. */
  4548. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4549. STATUS_RF_KILL_HW |
  4550. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4551. STATUS_RF_KILL_SW |
  4552. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4553. STATUS_GEO_CONFIGURED |
  4554. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4555. STATUS_IN_SUSPEND |
  4556. test_bit(STATUS_FW_ERROR, &priv->status) <<
  4557. STATUS_FW_ERROR |
  4558. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4559. STATUS_EXIT_PENDING;
  4560. spin_lock_irqsave(&priv->lock, flags);
  4561. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  4562. spin_unlock_irqrestore(&priv->lock, flags);
  4563. iwl3945_hw_txq_ctx_stop(priv);
  4564. iwl3945_hw_rxq_stop(priv);
  4565. spin_lock_irqsave(&priv->lock, flags);
  4566. if (!iwl_grab_nic_access(priv)) {
  4567. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  4568. APMG_CLK_VAL_DMA_CLK_RQT);
  4569. iwl_release_nic_access(priv);
  4570. }
  4571. spin_unlock_irqrestore(&priv->lock, flags);
  4572. udelay(5);
  4573. priv->cfg->ops->lib->apm_ops.reset(priv);
  4574. exit:
  4575. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  4576. if (priv->ibss_beacon)
  4577. dev_kfree_skb(priv->ibss_beacon);
  4578. priv->ibss_beacon = NULL;
  4579. /* clear out any free frames */
  4580. iwl3945_clear_free_frames(priv);
  4581. }
  4582. static void iwl3945_down(struct iwl_priv *priv)
  4583. {
  4584. mutex_lock(&priv->mutex);
  4585. __iwl3945_down(priv);
  4586. mutex_unlock(&priv->mutex);
  4587. iwl3945_cancel_deferred_work(priv);
  4588. }
  4589. #define MAX_HW_RESTARTS 5
  4590. static int __iwl3945_up(struct iwl_priv *priv)
  4591. {
  4592. int rc, i;
  4593. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4594. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  4595. return -EIO;
  4596. }
  4597. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  4598. IWL_WARN(priv, "Radio disabled by SW RF kill (module "
  4599. "parameter)\n");
  4600. return -ENODEV;
  4601. }
  4602. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  4603. IWL_ERR(priv, "ucode not available for device bring up\n");
  4604. return -EIO;
  4605. }
  4606. /* If platform's RF_KILL switch is NOT set to KILL */
  4607. if (iwl_read32(priv, CSR_GP_CNTRL) &
  4608. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  4609. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4610. else {
  4611. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4612. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  4613. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  4614. return -ENODEV;
  4615. }
  4616. }
  4617. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  4618. rc = iwl3945_hw_nic_init(priv);
  4619. if (rc) {
  4620. IWL_ERR(priv, "Unable to int nic\n");
  4621. return rc;
  4622. }
  4623. /* make sure rfkill handshake bits are cleared */
  4624. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4625. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  4626. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  4627. /* clear (again), then enable host interrupts */
  4628. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  4629. iwl3945_enable_interrupts(priv);
  4630. /* really make sure rfkill handshake bits are cleared */
  4631. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4632. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4633. /* Copy original ucode data image from disk into backup cache.
  4634. * This will be used to initialize the on-board processor's
  4635. * data SRAM for a clean start when the runtime program first loads. */
  4636. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  4637. priv->ucode_data.len);
  4638. /* We return success when we resume from suspend and rf_kill is on. */
  4639. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  4640. return 0;
  4641. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  4642. iwl3945_clear_stations_table(priv);
  4643. /* load bootstrap state machine,
  4644. * load bootstrap program into processor's memory,
  4645. * prepare to load the "initialize" uCode */
  4646. priv->cfg->ops->lib->load_ucode(priv);
  4647. if (rc) {
  4648. IWL_ERR(priv,
  4649. "Unable to set up bootstrap uCode: %d\n", rc);
  4650. continue;
  4651. }
  4652. /* start card; "initialize" will load runtime ucode */
  4653. iwl3945_nic_start(priv);
  4654. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  4655. return 0;
  4656. }
  4657. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4658. __iwl3945_down(priv);
  4659. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4660. /* tried to restart and config the device for as long as our
  4661. * patience could withstand */
  4662. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  4663. return -EIO;
  4664. }
  4665. /*****************************************************************************
  4666. *
  4667. * Workqueue callbacks
  4668. *
  4669. *****************************************************************************/
  4670. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  4671. {
  4672. struct iwl_priv *priv =
  4673. container_of(data, struct iwl_priv, init_alive_start.work);
  4674. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4675. return;
  4676. mutex_lock(&priv->mutex);
  4677. iwl3945_init_alive_start(priv);
  4678. mutex_unlock(&priv->mutex);
  4679. }
  4680. static void iwl3945_bg_alive_start(struct work_struct *data)
  4681. {
  4682. struct iwl_priv *priv =
  4683. container_of(data, struct iwl_priv, alive_start.work);
  4684. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4685. return;
  4686. mutex_lock(&priv->mutex);
  4687. iwl3945_alive_start(priv);
  4688. mutex_unlock(&priv->mutex);
  4689. }
  4690. static void iwl3945_bg_rf_kill(struct work_struct *work)
  4691. {
  4692. struct iwl_priv *priv = container_of(work, struct iwl_priv, rf_kill);
  4693. wake_up_interruptible(&priv->wait_command_queue);
  4694. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4695. return;
  4696. mutex_lock(&priv->mutex);
  4697. if (!iwl_is_rfkill(priv)) {
  4698. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  4699. "HW and/or SW RF Kill no longer active, restarting "
  4700. "device\n");
  4701. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  4702. queue_work(priv->workqueue, &priv->restart);
  4703. } else {
  4704. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  4705. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  4706. "disabled by SW switch\n");
  4707. else
  4708. IWL_WARN(priv, "Radio Frequency Kill Switch is On:\n"
  4709. "Kill switch must be turned off for "
  4710. "wireless networking to work.\n");
  4711. }
  4712. mutex_unlock(&priv->mutex);
  4713. iwl3945_rfkill_set_hw_state(priv);
  4714. }
  4715. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  4716. static void iwl3945_bg_scan_check(struct work_struct *data)
  4717. {
  4718. struct iwl_priv *priv =
  4719. container_of(data, struct iwl_priv, scan_check.work);
  4720. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4721. return;
  4722. mutex_lock(&priv->mutex);
  4723. if (test_bit(STATUS_SCANNING, &priv->status) ||
  4724. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  4725. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  4726. "Scan completion watchdog resetting adapter (%dms)\n",
  4727. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  4728. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  4729. iwl3945_send_scan_abort(priv);
  4730. }
  4731. mutex_unlock(&priv->mutex);
  4732. }
  4733. static void iwl3945_bg_request_scan(struct work_struct *data)
  4734. {
  4735. struct iwl_priv *priv =
  4736. container_of(data, struct iwl_priv, request_scan);
  4737. struct iwl_host_cmd cmd = {
  4738. .id = REPLY_SCAN_CMD,
  4739. .len = sizeof(struct iwl3945_scan_cmd),
  4740. .meta.flags = CMD_SIZE_HUGE,
  4741. };
  4742. int rc = 0;
  4743. struct iwl3945_scan_cmd *scan;
  4744. struct ieee80211_conf *conf = NULL;
  4745. u8 n_probes = 2;
  4746. enum ieee80211_band band;
  4747. DECLARE_SSID_BUF(ssid);
  4748. conf = ieee80211_get_hw_conf(priv->hw);
  4749. mutex_lock(&priv->mutex);
  4750. if (!iwl_is_ready(priv)) {
  4751. IWL_WARN(priv, "request scan called when driver not ready.\n");
  4752. goto done;
  4753. }
  4754. /* Make sure the scan wasn't canceled before this queued work
  4755. * was given the chance to run... */
  4756. if (!test_bit(STATUS_SCANNING, &priv->status))
  4757. goto done;
  4758. /* This should never be called or scheduled if there is currently
  4759. * a scan active in the hardware. */
  4760. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  4761. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  4762. "Ignoring second request.\n");
  4763. rc = -EIO;
  4764. goto done;
  4765. }
  4766. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4767. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  4768. goto done;
  4769. }
  4770. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  4771. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  4772. goto done;
  4773. }
  4774. if (iwl_is_rfkill(priv)) {
  4775. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  4776. goto done;
  4777. }
  4778. if (!test_bit(STATUS_READY, &priv->status)) {
  4779. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  4780. goto done;
  4781. }
  4782. if (!priv->scan_bands) {
  4783. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  4784. goto done;
  4785. }
  4786. if (!priv->scan39) {
  4787. priv->scan39 = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  4788. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  4789. if (!priv->scan39) {
  4790. rc = -ENOMEM;
  4791. goto done;
  4792. }
  4793. }
  4794. scan = priv->scan39;
  4795. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  4796. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  4797. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  4798. if (iwl3945_is_associated(priv)) {
  4799. u16 interval = 0;
  4800. u32 extra;
  4801. u32 suspend_time = 100;
  4802. u32 scan_suspend_time = 100;
  4803. unsigned long flags;
  4804. IWL_DEBUG_INFO("Scanning while associated...\n");
  4805. spin_lock_irqsave(&priv->lock, flags);
  4806. interval = priv->beacon_int;
  4807. spin_unlock_irqrestore(&priv->lock, flags);
  4808. scan->suspend_time = 0;
  4809. scan->max_out_time = cpu_to_le32(200 * 1024);
  4810. if (!interval)
  4811. interval = suspend_time;
  4812. /*
  4813. * suspend time format:
  4814. * 0-19: beacon interval in usec (time before exec.)
  4815. * 20-23: 0
  4816. * 24-31: number of beacons (suspend between channels)
  4817. */
  4818. extra = (suspend_time / interval) << 24;
  4819. scan_suspend_time = 0xFF0FFFFF &
  4820. (extra | ((suspend_time % interval) * 1024));
  4821. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  4822. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  4823. scan_suspend_time, interval);
  4824. }
  4825. /* We should add the ability for user to lock to PASSIVE ONLY */
  4826. if (priv->one_direct_scan) {
  4827. IWL_DEBUG_SCAN
  4828. ("Kicking off one direct scan for '%s'\n",
  4829. print_ssid(ssid, priv->direct_ssid,
  4830. priv->direct_ssid_len));
  4831. scan->direct_scan[0].id = WLAN_EID_SSID;
  4832. scan->direct_scan[0].len = priv->direct_ssid_len;
  4833. memcpy(scan->direct_scan[0].ssid,
  4834. priv->direct_ssid, priv->direct_ssid_len);
  4835. n_probes++;
  4836. } else
  4837. IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
  4838. /* We don't build a direct scan probe request; the uCode will do
  4839. * that based on the direct_mask added to each channel entry */
  4840. scan->tx_cmd.len = cpu_to_le16(
  4841. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  4842. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  4843. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  4844. scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
  4845. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  4846. /* flags + rate selection */
  4847. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
  4848. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  4849. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  4850. scan->good_CRC_th = 0;
  4851. band = IEEE80211_BAND_2GHZ;
  4852. } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
  4853. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  4854. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  4855. band = IEEE80211_BAND_5GHZ;
  4856. } else {
  4857. IWL_WARN(priv, "Invalid scan band count\n");
  4858. goto done;
  4859. }
  4860. /* select Rx antennas */
  4861. scan->flags |= iwl3945_get_antenna_flags(priv);
  4862. if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
  4863. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  4864. scan->channel_count =
  4865. iwl3945_get_channels_for_scan(priv, band, 1, /* active */
  4866. n_probes,
  4867. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  4868. if (scan->channel_count == 0) {
  4869. IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count);
  4870. goto done;
  4871. }
  4872. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  4873. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  4874. cmd.data = scan;
  4875. scan->len = cpu_to_le16(cmd.len);
  4876. set_bit(STATUS_SCAN_HW, &priv->status);
  4877. rc = iwl3945_send_cmd_sync(priv, &cmd);
  4878. if (rc)
  4879. goto done;
  4880. queue_delayed_work(priv->workqueue, &priv->scan_check,
  4881. IWL_SCAN_CHECK_WATCHDOG);
  4882. mutex_unlock(&priv->mutex);
  4883. return;
  4884. done:
  4885. /* can not perform scan make sure we clear scanning
  4886. * bits from status so next scan request can be performed.
  4887. * if we dont clear scanning status bit here all next scan
  4888. * will fail
  4889. */
  4890. clear_bit(STATUS_SCAN_HW, &priv->status);
  4891. clear_bit(STATUS_SCANNING, &priv->status);
  4892. /* inform mac80211 scan aborted */
  4893. queue_work(priv->workqueue, &priv->scan_completed);
  4894. mutex_unlock(&priv->mutex);
  4895. }
  4896. static void iwl3945_bg_up(struct work_struct *data)
  4897. {
  4898. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  4899. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4900. return;
  4901. mutex_lock(&priv->mutex);
  4902. __iwl3945_up(priv);
  4903. mutex_unlock(&priv->mutex);
  4904. iwl3945_rfkill_set_hw_state(priv);
  4905. }
  4906. static void iwl3945_bg_restart(struct work_struct *data)
  4907. {
  4908. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  4909. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4910. return;
  4911. iwl3945_down(priv);
  4912. queue_work(priv->workqueue, &priv->up);
  4913. }
  4914. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  4915. {
  4916. struct iwl_priv *priv =
  4917. container_of(data, struct iwl_priv, rx_replenish);
  4918. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4919. return;
  4920. mutex_lock(&priv->mutex);
  4921. iwl3945_rx_replenish(priv);
  4922. mutex_unlock(&priv->mutex);
  4923. }
  4924. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  4925. static void iwl3945_post_associate(struct iwl_priv *priv)
  4926. {
  4927. int rc = 0;
  4928. struct ieee80211_conf *conf = NULL;
  4929. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  4930. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  4931. return;
  4932. }
  4933. IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
  4934. priv->assoc_id, priv->active39_rxon.bssid_addr);
  4935. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4936. return;
  4937. if (!priv->vif || !priv->is_open)
  4938. return;
  4939. iwl3945_scan_cancel_timeout(priv, 200);
  4940. conf = ieee80211_get_hw_conf(priv->hw);
  4941. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4942. iwl3945_commit_rxon(priv);
  4943. memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
  4944. iwl3945_setup_rxon_timing(priv);
  4945. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  4946. sizeof(priv->rxon_timing), &priv->rxon_timing);
  4947. if (rc)
  4948. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  4949. "Attempting to continue.\n");
  4950. priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  4951. priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  4952. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  4953. priv->assoc_id, priv->beacon_int);
  4954. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  4955. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  4956. else
  4957. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  4958. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  4959. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  4960. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  4961. else
  4962. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  4963. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  4964. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  4965. }
  4966. iwl3945_commit_rxon(priv);
  4967. switch (priv->iw_mode) {
  4968. case NL80211_IFTYPE_STATION:
  4969. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  4970. break;
  4971. case NL80211_IFTYPE_ADHOC:
  4972. priv->assoc_id = 1;
  4973. iwl3945_add_station(priv, priv->bssid, 0, 0);
  4974. iwl3945_sync_sta(priv, IWL_STA_ID,
  4975. (priv->band == IEEE80211_BAND_5GHZ) ?
  4976. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  4977. CMD_ASYNC);
  4978. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  4979. iwl3945_send_beacon_cmd(priv);
  4980. break;
  4981. default:
  4982. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  4983. __func__, priv->iw_mode);
  4984. break;
  4985. }
  4986. iwl3945_activate_qos(priv, 0);
  4987. /* we have just associated, don't start scan too early */
  4988. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  4989. }
  4990. static void iwl3945_bg_abort_scan(struct work_struct *work)
  4991. {
  4992. struct iwl_priv *priv = container_of(work, struct iwl_priv, abort_scan);
  4993. if (!iwl_is_ready(priv))
  4994. return;
  4995. mutex_lock(&priv->mutex);
  4996. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  4997. iwl3945_send_scan_abort(priv);
  4998. mutex_unlock(&priv->mutex);
  4999. }
  5000. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
  5001. static void iwl3945_bg_scan_completed(struct work_struct *work)
  5002. {
  5003. struct iwl_priv *priv =
  5004. container_of(work, struct iwl_priv, scan_completed);
  5005. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5006. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5007. return;
  5008. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  5009. iwl3945_mac_config(priv->hw, 0);
  5010. ieee80211_scan_completed(priv->hw);
  5011. /* Since setting the TXPOWER may have been deferred while
  5012. * performing the scan, fire one off */
  5013. mutex_lock(&priv->mutex);
  5014. iwl3945_hw_reg_send_txpower(priv);
  5015. mutex_unlock(&priv->mutex);
  5016. }
  5017. /*****************************************************************************
  5018. *
  5019. * mac80211 entry point functions
  5020. *
  5021. *****************************************************************************/
  5022. #define UCODE_READY_TIMEOUT (2 * HZ)
  5023. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5024. {
  5025. struct iwl_priv *priv = hw->priv;
  5026. int ret;
  5027. IWL_DEBUG_MAC80211("enter\n");
  5028. if (pci_enable_device(priv->pci_dev)) {
  5029. IWL_ERR(priv, "Fail to pci_enable_device\n");
  5030. return -ENODEV;
  5031. }
  5032. pci_restore_state(priv->pci_dev);
  5033. pci_enable_msi(priv->pci_dev);
  5034. ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  5035. DRV_NAME, priv);
  5036. if (ret) {
  5037. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  5038. goto out_disable_msi;
  5039. }
  5040. /* we should be verifying the device is ready to be opened */
  5041. mutex_lock(&priv->mutex);
  5042. memset(&priv->staging39_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  5043. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  5044. * ucode filename and max sizes are card-specific. */
  5045. if (!priv->ucode_code.len) {
  5046. ret = iwl3945_read_ucode(priv);
  5047. if (ret) {
  5048. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  5049. mutex_unlock(&priv->mutex);
  5050. goto out_release_irq;
  5051. }
  5052. }
  5053. ret = __iwl3945_up(priv);
  5054. mutex_unlock(&priv->mutex);
  5055. iwl3945_rfkill_set_hw_state(priv);
  5056. if (ret)
  5057. goto out_release_irq;
  5058. IWL_DEBUG_INFO("Start UP work.\n");
  5059. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  5060. return 0;
  5061. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  5062. * mac80211 will not be run successfully. */
  5063. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  5064. test_bit(STATUS_READY, &priv->status),
  5065. UCODE_READY_TIMEOUT);
  5066. if (!ret) {
  5067. if (!test_bit(STATUS_READY, &priv->status)) {
  5068. IWL_ERR(priv,
  5069. "Wait for START_ALIVE timeout after %dms.\n",
  5070. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  5071. ret = -ETIMEDOUT;
  5072. goto out_release_irq;
  5073. }
  5074. }
  5075. priv->is_open = 1;
  5076. IWL_DEBUG_MAC80211("leave\n");
  5077. return 0;
  5078. out_release_irq:
  5079. free_irq(priv->pci_dev->irq, priv);
  5080. out_disable_msi:
  5081. pci_disable_msi(priv->pci_dev);
  5082. pci_disable_device(priv->pci_dev);
  5083. priv->is_open = 0;
  5084. IWL_DEBUG_MAC80211("leave - failed\n");
  5085. return ret;
  5086. }
  5087. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5088. {
  5089. struct iwl_priv *priv = hw->priv;
  5090. IWL_DEBUG_MAC80211("enter\n");
  5091. if (!priv->is_open) {
  5092. IWL_DEBUG_MAC80211("leave - skip\n");
  5093. return;
  5094. }
  5095. priv->is_open = 0;
  5096. if (iwl_is_ready_rf(priv)) {
  5097. /* stop mac, cancel any scan request and clear
  5098. * RXON_FILTER_ASSOC_MSK BIT
  5099. */
  5100. mutex_lock(&priv->mutex);
  5101. iwl3945_scan_cancel_timeout(priv, 100);
  5102. mutex_unlock(&priv->mutex);
  5103. }
  5104. iwl3945_down(priv);
  5105. flush_workqueue(priv->workqueue);
  5106. free_irq(priv->pci_dev->irq, priv);
  5107. pci_disable_msi(priv->pci_dev);
  5108. pci_save_state(priv->pci_dev);
  5109. pci_disable_device(priv->pci_dev);
  5110. IWL_DEBUG_MAC80211("leave\n");
  5111. }
  5112. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  5113. {
  5114. struct iwl_priv *priv = hw->priv;
  5115. IWL_DEBUG_MAC80211("enter\n");
  5116. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5117. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  5118. if (iwl3945_tx_skb(priv, skb))
  5119. dev_kfree_skb_any(skb);
  5120. IWL_DEBUG_MAC80211("leave\n");
  5121. return NETDEV_TX_OK;
  5122. }
  5123. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5124. struct ieee80211_if_init_conf *conf)
  5125. {
  5126. struct iwl_priv *priv = hw->priv;
  5127. unsigned long flags;
  5128. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5129. if (priv->vif) {
  5130. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5131. return -EOPNOTSUPP;
  5132. }
  5133. spin_lock_irqsave(&priv->lock, flags);
  5134. priv->vif = conf->vif;
  5135. priv->iw_mode = conf->type;
  5136. spin_unlock_irqrestore(&priv->lock, flags);
  5137. mutex_lock(&priv->mutex);
  5138. if (conf->mac_addr) {
  5139. IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
  5140. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5141. }
  5142. if (iwl_is_ready(priv))
  5143. iwl3945_set_mode(priv, conf->type);
  5144. mutex_unlock(&priv->mutex);
  5145. IWL_DEBUG_MAC80211("leave\n");
  5146. return 0;
  5147. }
  5148. /**
  5149. * iwl3945_mac_config - mac80211 config callback
  5150. *
  5151. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5152. * be set inappropriately and the driver currently sets the hardware up to
  5153. * use it whenever needed.
  5154. */
  5155. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
  5156. {
  5157. struct iwl_priv *priv = hw->priv;
  5158. const struct iwl_channel_info *ch_info;
  5159. struct ieee80211_conf *conf = &hw->conf;
  5160. unsigned long flags;
  5161. int ret = 0;
  5162. mutex_lock(&priv->mutex);
  5163. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5164. if (!iwl_is_ready(priv)) {
  5165. IWL_DEBUG_MAC80211("leave - not ready\n");
  5166. ret = -EIO;
  5167. goto out;
  5168. }
  5169. if (unlikely(!iwl3945_mod_params.disable_hw_scan &&
  5170. test_bit(STATUS_SCANNING, &priv->status))) {
  5171. IWL_DEBUG_MAC80211("leave - scanning\n");
  5172. set_bit(STATUS_CONF_PENDING, &priv->status);
  5173. mutex_unlock(&priv->mutex);
  5174. return 0;
  5175. }
  5176. spin_lock_irqsave(&priv->lock, flags);
  5177. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5178. conf->channel->hw_value);
  5179. if (!is_channel_valid(ch_info)) {
  5180. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
  5181. conf->channel->hw_value, conf->channel->band);
  5182. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5183. spin_unlock_irqrestore(&priv->lock, flags);
  5184. ret = -EINVAL;
  5185. goto out;
  5186. }
  5187. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5188. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5189. /* The list of supported rates and rate mask can be different
  5190. * for each phymode; since the phymode may have changed, reset
  5191. * the rate mask to what mac80211 lists */
  5192. iwl3945_set_rate(priv);
  5193. spin_unlock_irqrestore(&priv->lock, flags);
  5194. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5195. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5196. iwl3945_hw_channel_switch(priv, conf->channel);
  5197. goto out;
  5198. }
  5199. #endif
  5200. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5201. if (!conf->radio_enabled) {
  5202. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5203. goto out;
  5204. }
  5205. if (iwl_is_rfkill(priv)) {
  5206. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5207. ret = -EIO;
  5208. goto out;
  5209. }
  5210. iwl3945_set_rate(priv);
  5211. if (memcmp(&priv->active39_rxon,
  5212. &priv->staging39_rxon, sizeof(priv->staging39_rxon)))
  5213. iwl3945_commit_rxon(priv);
  5214. else
  5215. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5216. IWL_DEBUG_MAC80211("leave\n");
  5217. out:
  5218. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5219. mutex_unlock(&priv->mutex);
  5220. return ret;
  5221. }
  5222. static void iwl3945_config_ap(struct iwl_priv *priv)
  5223. {
  5224. int rc = 0;
  5225. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5226. return;
  5227. /* The following should be done only at AP bring up */
  5228. if (!(iwl3945_is_associated(priv))) {
  5229. /* RXON - unassoc (to set timing command) */
  5230. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5231. iwl3945_commit_rxon(priv);
  5232. /* RXON Timing */
  5233. memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
  5234. iwl3945_setup_rxon_timing(priv);
  5235. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5236. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5237. if (rc)
  5238. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  5239. "Attempting to continue.\n");
  5240. /* FIXME: what should be the assoc_id for AP? */
  5241. priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5242. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5243. priv->staging39_rxon.flags |=
  5244. RXON_FLG_SHORT_PREAMBLE_MSK;
  5245. else
  5246. priv->staging39_rxon.flags &=
  5247. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5248. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5249. if (priv->assoc_capability &
  5250. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5251. priv->staging39_rxon.flags |=
  5252. RXON_FLG_SHORT_SLOT_MSK;
  5253. else
  5254. priv->staging39_rxon.flags &=
  5255. ~RXON_FLG_SHORT_SLOT_MSK;
  5256. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  5257. priv->staging39_rxon.flags &=
  5258. ~RXON_FLG_SHORT_SLOT_MSK;
  5259. }
  5260. /* restore RXON assoc */
  5261. priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5262. iwl3945_commit_rxon(priv);
  5263. iwl3945_add_station(priv, iwl_bcast_addr, 0, 0);
  5264. }
  5265. iwl3945_send_beacon_cmd(priv);
  5266. /* FIXME - we need to add code here to detect a totally new
  5267. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5268. * clear sta table, add BCAST sta... */
  5269. }
  5270. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5271. struct ieee80211_vif *vif,
  5272. struct ieee80211_if_conf *conf)
  5273. {
  5274. struct iwl_priv *priv = hw->priv;
  5275. int rc;
  5276. if (conf == NULL)
  5277. return -EIO;
  5278. if (priv->vif != vif) {
  5279. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5280. return 0;
  5281. }
  5282. /* handle this temporarily here */
  5283. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  5284. conf->changed & IEEE80211_IFCC_BEACON) {
  5285. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  5286. if (!beacon)
  5287. return -ENOMEM;
  5288. mutex_lock(&priv->mutex);
  5289. rc = iwl3945_mac_beacon_update(hw, beacon);
  5290. mutex_unlock(&priv->mutex);
  5291. if (rc)
  5292. return rc;
  5293. }
  5294. if (!iwl_is_alive(priv))
  5295. return -EAGAIN;
  5296. mutex_lock(&priv->mutex);
  5297. if (conf->bssid)
  5298. IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
  5299. /*
  5300. * very dubious code was here; the probe filtering flag is never set:
  5301. *
  5302. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5303. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5304. */
  5305. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  5306. if (!conf->bssid) {
  5307. conf->bssid = priv->mac_addr;
  5308. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5309. IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
  5310. conf->bssid);
  5311. }
  5312. if (priv->ibss_beacon)
  5313. dev_kfree_skb(priv->ibss_beacon);
  5314. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  5315. }
  5316. if (iwl_is_rfkill(priv))
  5317. goto done;
  5318. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5319. !is_multicast_ether_addr(conf->bssid)) {
  5320. /* If there is currently a HW scan going on in the background
  5321. * then we need to cancel it else the RXON below will fail. */
  5322. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5323. IWL_WARN(priv, "Aborted scan still in progress "
  5324. "after 100ms\n");
  5325. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5326. mutex_unlock(&priv->mutex);
  5327. return -EAGAIN;
  5328. }
  5329. memcpy(priv->staging39_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5330. /* TODO: Audit driver for usage of these members and see
  5331. * if mac80211 deprecates them (priv->bssid looks like it
  5332. * shouldn't be there, but I haven't scanned the IBSS code
  5333. * to verify) - jpk */
  5334. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5335. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5336. iwl3945_config_ap(priv);
  5337. else {
  5338. rc = iwl3945_commit_rxon(priv);
  5339. if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
  5340. iwl3945_add_station(priv,
  5341. priv->active39_rxon.bssid_addr, 1, 0);
  5342. }
  5343. } else {
  5344. iwl3945_scan_cancel_timeout(priv, 100);
  5345. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5346. iwl3945_commit_rxon(priv);
  5347. }
  5348. done:
  5349. IWL_DEBUG_MAC80211("leave\n");
  5350. mutex_unlock(&priv->mutex);
  5351. return 0;
  5352. }
  5353. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  5354. unsigned int changed_flags,
  5355. unsigned int *total_flags,
  5356. int mc_count, struct dev_addr_list *mc_list)
  5357. {
  5358. struct iwl_priv *priv = hw->priv;
  5359. __le32 *filter_flags = &priv->staging39_rxon.filter_flags;
  5360. IWL_DEBUG_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
  5361. changed_flags, *total_flags);
  5362. if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
  5363. if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
  5364. *filter_flags |= RXON_FILTER_PROMISC_MSK;
  5365. else
  5366. *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
  5367. }
  5368. if (changed_flags & FIF_ALLMULTI) {
  5369. if (*total_flags & FIF_ALLMULTI)
  5370. *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
  5371. else
  5372. *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
  5373. }
  5374. if (changed_flags & FIF_CONTROL) {
  5375. if (*total_flags & FIF_CONTROL)
  5376. *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
  5377. else
  5378. *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
  5379. }
  5380. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  5381. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  5382. *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
  5383. else
  5384. *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
  5385. }
  5386. /* We avoid iwl_commit_rxon here to commit the new filter flags
  5387. * since mac80211 will call ieee80211_hw_config immediately.
  5388. * (mc_list is not supported at this time). Otherwise, we need to
  5389. * queue a background iwl_commit_rxon work.
  5390. */
  5391. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  5392. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  5393. }
  5394. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  5395. struct ieee80211_if_init_conf *conf)
  5396. {
  5397. struct iwl_priv *priv = hw->priv;
  5398. IWL_DEBUG_MAC80211("enter\n");
  5399. mutex_lock(&priv->mutex);
  5400. if (iwl_is_ready_rf(priv)) {
  5401. iwl3945_scan_cancel_timeout(priv, 100);
  5402. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5403. iwl3945_commit_rxon(priv);
  5404. }
  5405. if (priv->vif == conf->vif) {
  5406. priv->vif = NULL;
  5407. memset(priv->bssid, 0, ETH_ALEN);
  5408. }
  5409. mutex_unlock(&priv->mutex);
  5410. IWL_DEBUG_MAC80211("leave\n");
  5411. }
  5412. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  5413. static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
  5414. struct ieee80211_vif *vif,
  5415. struct ieee80211_bss_conf *bss_conf,
  5416. u32 changes)
  5417. {
  5418. struct iwl_priv *priv = hw->priv;
  5419. IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
  5420. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  5421. IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
  5422. bss_conf->use_short_preamble);
  5423. if (bss_conf->use_short_preamble)
  5424. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5425. else
  5426. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5427. }
  5428. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  5429. IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
  5430. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  5431. priv->staging39_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  5432. else
  5433. priv->staging39_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  5434. }
  5435. if (changes & BSS_CHANGED_ASSOC) {
  5436. IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
  5437. /* This should never happen as this function should
  5438. * never be called from interrupt context. */
  5439. if (WARN_ON_ONCE(in_interrupt()))
  5440. return;
  5441. if (bss_conf->assoc) {
  5442. priv->assoc_id = bss_conf->aid;
  5443. priv->beacon_int = bss_conf->beacon_int;
  5444. priv->timestamp = bss_conf->timestamp;
  5445. priv->assoc_capability = bss_conf->assoc_capability;
  5446. priv->next_scan_jiffies = jiffies +
  5447. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  5448. mutex_lock(&priv->mutex);
  5449. iwl3945_post_associate(priv);
  5450. mutex_unlock(&priv->mutex);
  5451. } else {
  5452. priv->assoc_id = 0;
  5453. IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
  5454. }
  5455. } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
  5456. IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
  5457. iwl3945_send_rxon_assoc(priv);
  5458. }
  5459. }
  5460. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  5461. {
  5462. int rc = 0;
  5463. unsigned long flags;
  5464. struct iwl_priv *priv = hw->priv;
  5465. DECLARE_SSID_BUF(ssid_buf);
  5466. IWL_DEBUG_MAC80211("enter\n");
  5467. mutex_lock(&priv->mutex);
  5468. spin_lock_irqsave(&priv->lock, flags);
  5469. if (!iwl_is_ready_rf(priv)) {
  5470. rc = -EIO;
  5471. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  5472. goto out_unlock;
  5473. }
  5474. /* we don't schedule scan within next_scan_jiffies period */
  5475. if (priv->next_scan_jiffies &&
  5476. time_after(priv->next_scan_jiffies, jiffies)) {
  5477. rc = -EAGAIN;
  5478. goto out_unlock;
  5479. }
  5480. /* if we just finished scan ask for delay for a broadcast scan */
  5481. if ((len == 0) && priv->last_scan_jiffies &&
  5482. time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
  5483. jiffies)) {
  5484. rc = -EAGAIN;
  5485. goto out_unlock;
  5486. }
  5487. if (len) {
  5488. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  5489. print_ssid(ssid_buf, ssid, len), (int)len);
  5490. priv->one_direct_scan = 1;
  5491. priv->direct_ssid_len = (u8)
  5492. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  5493. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  5494. } else
  5495. priv->one_direct_scan = 0;
  5496. rc = iwl3945_scan_initiate(priv);
  5497. IWL_DEBUG_MAC80211("leave\n");
  5498. out_unlock:
  5499. spin_unlock_irqrestore(&priv->lock, flags);
  5500. mutex_unlock(&priv->mutex);
  5501. return rc;
  5502. }
  5503. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  5504. const u8 *local_addr, const u8 *addr,
  5505. struct ieee80211_key_conf *key)
  5506. {
  5507. struct iwl_priv *priv = hw->priv;
  5508. int rc = 0;
  5509. u8 sta_id;
  5510. IWL_DEBUG_MAC80211("enter\n");
  5511. if (iwl3945_mod_params.sw_crypto) {
  5512. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  5513. return -EOPNOTSUPP;
  5514. }
  5515. if (is_zero_ether_addr(addr))
  5516. /* only support pairwise keys */
  5517. return -EOPNOTSUPP;
  5518. sta_id = iwl3945_hw_find_station(priv, addr);
  5519. if (sta_id == IWL_INVALID_STATION) {
  5520. IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
  5521. addr);
  5522. return -EINVAL;
  5523. }
  5524. mutex_lock(&priv->mutex);
  5525. iwl3945_scan_cancel_timeout(priv, 100);
  5526. switch (cmd) {
  5527. case SET_KEY:
  5528. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  5529. if (!rc) {
  5530. iwl3945_set_rxon_hwcrypto(priv, 1);
  5531. iwl3945_commit_rxon(priv);
  5532. key->hw_key_idx = sta_id;
  5533. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  5534. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  5535. }
  5536. break;
  5537. case DISABLE_KEY:
  5538. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  5539. if (!rc) {
  5540. iwl3945_set_rxon_hwcrypto(priv, 0);
  5541. iwl3945_commit_rxon(priv);
  5542. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  5543. }
  5544. break;
  5545. default:
  5546. rc = -EINVAL;
  5547. }
  5548. IWL_DEBUG_MAC80211("leave\n");
  5549. mutex_unlock(&priv->mutex);
  5550. return rc;
  5551. }
  5552. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  5553. const struct ieee80211_tx_queue_params *params)
  5554. {
  5555. struct iwl_priv *priv = hw->priv;
  5556. unsigned long flags;
  5557. int q;
  5558. IWL_DEBUG_MAC80211("enter\n");
  5559. if (!iwl_is_ready_rf(priv)) {
  5560. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5561. return -EIO;
  5562. }
  5563. if (queue >= AC_NUM) {
  5564. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  5565. return 0;
  5566. }
  5567. q = AC_NUM - 1 - queue;
  5568. spin_lock_irqsave(&priv->lock, flags);
  5569. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  5570. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  5571. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  5572. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  5573. cpu_to_le16((params->txop * 32));
  5574. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  5575. priv->qos_data.qos_active = 1;
  5576. spin_unlock_irqrestore(&priv->lock, flags);
  5577. mutex_lock(&priv->mutex);
  5578. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5579. iwl3945_activate_qos(priv, 1);
  5580. else if (priv->assoc_id && iwl3945_is_associated(priv))
  5581. iwl3945_activate_qos(priv, 0);
  5582. mutex_unlock(&priv->mutex);
  5583. IWL_DEBUG_MAC80211("leave\n");
  5584. return 0;
  5585. }
  5586. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  5587. struct ieee80211_tx_queue_stats *stats)
  5588. {
  5589. struct iwl_priv *priv = hw->priv;
  5590. int i, avail;
  5591. struct iwl3945_tx_queue *txq;
  5592. struct iwl_queue *q;
  5593. unsigned long flags;
  5594. IWL_DEBUG_MAC80211("enter\n");
  5595. if (!iwl_is_ready_rf(priv)) {
  5596. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5597. return -EIO;
  5598. }
  5599. spin_lock_irqsave(&priv->lock, flags);
  5600. for (i = 0; i < AC_NUM; i++) {
  5601. txq = &priv->txq39[i];
  5602. q = &txq->q;
  5603. avail = iwl_queue_space(q);
  5604. stats[i].len = q->n_window - avail;
  5605. stats[i].limit = q->n_window - q->high_mark;
  5606. stats[i].count = q->n_window;
  5607. }
  5608. spin_unlock_irqrestore(&priv->lock, flags);
  5609. IWL_DEBUG_MAC80211("leave\n");
  5610. return 0;
  5611. }
  5612. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  5613. {
  5614. struct iwl_priv *priv = hw->priv;
  5615. unsigned long flags;
  5616. mutex_lock(&priv->mutex);
  5617. IWL_DEBUG_MAC80211("enter\n");
  5618. iwl_reset_qos(priv);
  5619. spin_lock_irqsave(&priv->lock, flags);
  5620. priv->assoc_id = 0;
  5621. priv->assoc_capability = 0;
  5622. priv->call_post_assoc_from_beacon = 0;
  5623. /* new association get rid of ibss beacon skb */
  5624. if (priv->ibss_beacon)
  5625. dev_kfree_skb(priv->ibss_beacon);
  5626. priv->ibss_beacon = NULL;
  5627. priv->beacon_int = priv->hw->conf.beacon_int;
  5628. priv->timestamp = 0;
  5629. if ((priv->iw_mode == NL80211_IFTYPE_STATION))
  5630. priv->beacon_int = 0;
  5631. spin_unlock_irqrestore(&priv->lock, flags);
  5632. if (!iwl_is_ready_rf(priv)) {
  5633. IWL_DEBUG_MAC80211("leave - not ready\n");
  5634. mutex_unlock(&priv->mutex);
  5635. return;
  5636. }
  5637. /* we are restarting association process
  5638. * clear RXON_FILTER_ASSOC_MSK bit
  5639. */
  5640. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  5641. iwl3945_scan_cancel_timeout(priv, 100);
  5642. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5643. iwl3945_commit_rxon(priv);
  5644. }
  5645. /* Per mac80211.h: This is only used in IBSS mode... */
  5646. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5647. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  5648. mutex_unlock(&priv->mutex);
  5649. return;
  5650. }
  5651. iwl3945_set_rate(priv);
  5652. mutex_unlock(&priv->mutex);
  5653. IWL_DEBUG_MAC80211("leave\n");
  5654. }
  5655. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  5656. {
  5657. struct iwl_priv *priv = hw->priv;
  5658. unsigned long flags;
  5659. IWL_DEBUG_MAC80211("enter\n");
  5660. if (!iwl_is_ready_rf(priv)) {
  5661. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5662. return -EIO;
  5663. }
  5664. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5665. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  5666. return -EIO;
  5667. }
  5668. spin_lock_irqsave(&priv->lock, flags);
  5669. if (priv->ibss_beacon)
  5670. dev_kfree_skb(priv->ibss_beacon);
  5671. priv->ibss_beacon = skb;
  5672. priv->assoc_id = 0;
  5673. IWL_DEBUG_MAC80211("leave\n");
  5674. spin_unlock_irqrestore(&priv->lock, flags);
  5675. iwl_reset_qos(priv);
  5676. iwl3945_post_associate(priv);
  5677. return 0;
  5678. }
  5679. /*****************************************************************************
  5680. *
  5681. * sysfs attributes
  5682. *
  5683. *****************************************************************************/
  5684. #ifdef CONFIG_IWL3945_DEBUG
  5685. /*
  5686. * The following adds a new attribute to the sysfs representation
  5687. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  5688. * used for controlling the debug level.
  5689. *
  5690. * See the level definitions in iwl for details.
  5691. */
  5692. static ssize_t show_debug_level(struct device *d,
  5693. struct device_attribute *attr, char *buf)
  5694. {
  5695. struct iwl_priv *priv = d->driver_data;
  5696. return sprintf(buf, "0x%08X\n", priv->debug_level);
  5697. }
  5698. static ssize_t store_debug_level(struct device *d,
  5699. struct device_attribute *attr,
  5700. const char *buf, size_t count)
  5701. {
  5702. struct iwl_priv *priv = d->driver_data;
  5703. unsigned long val;
  5704. int ret;
  5705. ret = strict_strtoul(buf, 0, &val);
  5706. if (ret)
  5707. IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
  5708. else
  5709. priv->debug_level = val;
  5710. return strnlen(buf, count);
  5711. }
  5712. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  5713. show_debug_level, store_debug_level);
  5714. #endif /* CONFIG_IWL3945_DEBUG */
  5715. static ssize_t show_temperature(struct device *d,
  5716. struct device_attribute *attr, char *buf)
  5717. {
  5718. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5719. if (!iwl_is_alive(priv))
  5720. return -EAGAIN;
  5721. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  5722. }
  5723. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  5724. static ssize_t show_tx_power(struct device *d,
  5725. struct device_attribute *attr, char *buf)
  5726. {
  5727. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5728. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  5729. }
  5730. static ssize_t store_tx_power(struct device *d,
  5731. struct device_attribute *attr,
  5732. const char *buf, size_t count)
  5733. {
  5734. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5735. char *p = (char *)buf;
  5736. u32 val;
  5737. val = simple_strtoul(p, &p, 10);
  5738. if (p == buf)
  5739. IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
  5740. else
  5741. iwl3945_hw_reg_set_txpower(priv, val);
  5742. return count;
  5743. }
  5744. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  5745. static ssize_t show_flags(struct device *d,
  5746. struct device_attribute *attr, char *buf)
  5747. {
  5748. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5749. return sprintf(buf, "0x%04X\n", priv->active39_rxon.flags);
  5750. }
  5751. static ssize_t store_flags(struct device *d,
  5752. struct device_attribute *attr,
  5753. const char *buf, size_t count)
  5754. {
  5755. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5756. u32 flags = simple_strtoul(buf, NULL, 0);
  5757. mutex_lock(&priv->mutex);
  5758. if (le32_to_cpu(priv->staging39_rxon.flags) != flags) {
  5759. /* Cancel any currently running scans... */
  5760. if (iwl3945_scan_cancel_timeout(priv, 100))
  5761. IWL_WARN(priv, "Could not cancel scan.\n");
  5762. else {
  5763. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  5764. flags);
  5765. priv->staging39_rxon.flags = cpu_to_le32(flags);
  5766. iwl3945_commit_rxon(priv);
  5767. }
  5768. }
  5769. mutex_unlock(&priv->mutex);
  5770. return count;
  5771. }
  5772. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  5773. static ssize_t show_filter_flags(struct device *d,
  5774. struct device_attribute *attr, char *buf)
  5775. {
  5776. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5777. return sprintf(buf, "0x%04X\n",
  5778. le32_to_cpu(priv->active39_rxon.filter_flags));
  5779. }
  5780. static ssize_t store_filter_flags(struct device *d,
  5781. struct device_attribute *attr,
  5782. const char *buf, size_t count)
  5783. {
  5784. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5785. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  5786. mutex_lock(&priv->mutex);
  5787. if (le32_to_cpu(priv->staging39_rxon.filter_flags) != filter_flags) {
  5788. /* Cancel any currently running scans... */
  5789. if (iwl3945_scan_cancel_timeout(priv, 100))
  5790. IWL_WARN(priv, "Could not cancel scan.\n");
  5791. else {
  5792. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  5793. "0x%04X\n", filter_flags);
  5794. priv->staging39_rxon.filter_flags =
  5795. cpu_to_le32(filter_flags);
  5796. iwl3945_commit_rxon(priv);
  5797. }
  5798. }
  5799. mutex_unlock(&priv->mutex);
  5800. return count;
  5801. }
  5802. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  5803. store_filter_flags);
  5804. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  5805. static ssize_t show_measurement(struct device *d,
  5806. struct device_attribute *attr, char *buf)
  5807. {
  5808. struct iwl_priv *priv = dev_get_drvdata(d);
  5809. struct iwl_spectrum_notification measure_report;
  5810. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  5811. u8 *data = (u8 *)&measure_report;
  5812. unsigned long flags;
  5813. spin_lock_irqsave(&priv->lock, flags);
  5814. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  5815. spin_unlock_irqrestore(&priv->lock, flags);
  5816. return 0;
  5817. }
  5818. memcpy(&measure_report, &priv->measure_report, size);
  5819. priv->measurement_status = 0;
  5820. spin_unlock_irqrestore(&priv->lock, flags);
  5821. while (size && (PAGE_SIZE - len)) {
  5822. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  5823. PAGE_SIZE - len, 1);
  5824. len = strlen(buf);
  5825. if (PAGE_SIZE - len)
  5826. buf[len++] = '\n';
  5827. ofs += 16;
  5828. size -= min(size, 16U);
  5829. }
  5830. return len;
  5831. }
  5832. static ssize_t store_measurement(struct device *d,
  5833. struct device_attribute *attr,
  5834. const char *buf, size_t count)
  5835. {
  5836. struct iwl_priv *priv = dev_get_drvdata(d);
  5837. struct ieee80211_measurement_params params = {
  5838. .channel = le16_to_cpu(priv->active39_rxon.channel),
  5839. .start_time = cpu_to_le64(priv->last_tsf),
  5840. .duration = cpu_to_le16(1),
  5841. };
  5842. u8 type = IWL_MEASURE_BASIC;
  5843. u8 buffer[32];
  5844. u8 channel;
  5845. if (count) {
  5846. char *p = buffer;
  5847. strncpy(buffer, buf, min(sizeof(buffer), count));
  5848. channel = simple_strtoul(p, NULL, 0);
  5849. if (channel)
  5850. params.channel = channel;
  5851. p = buffer;
  5852. while (*p && *p != ' ')
  5853. p++;
  5854. if (*p)
  5855. type = simple_strtoul(p + 1, NULL, 0);
  5856. }
  5857. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  5858. "channel %d (for '%s')\n", type, params.channel, buf);
  5859. iwl3945_get_measurement(priv, &params, type);
  5860. return count;
  5861. }
  5862. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  5863. show_measurement, store_measurement);
  5864. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  5865. static ssize_t store_retry_rate(struct device *d,
  5866. struct device_attribute *attr,
  5867. const char *buf, size_t count)
  5868. {
  5869. struct iwl_priv *priv = dev_get_drvdata(d);
  5870. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  5871. if (priv->retry_rate <= 0)
  5872. priv->retry_rate = 1;
  5873. return count;
  5874. }
  5875. static ssize_t show_retry_rate(struct device *d,
  5876. struct device_attribute *attr, char *buf)
  5877. {
  5878. struct iwl_priv *priv = dev_get_drvdata(d);
  5879. return sprintf(buf, "%d", priv->retry_rate);
  5880. }
  5881. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  5882. store_retry_rate);
  5883. static ssize_t store_power_level(struct device *d,
  5884. struct device_attribute *attr,
  5885. const char *buf, size_t count)
  5886. {
  5887. struct iwl_priv *priv = dev_get_drvdata(d);
  5888. int rc;
  5889. int mode;
  5890. mode = simple_strtoul(buf, NULL, 0);
  5891. mutex_lock(&priv->mutex);
  5892. if (!iwl_is_ready(priv)) {
  5893. rc = -EAGAIN;
  5894. goto out;
  5895. }
  5896. if ((mode < 1) || (mode > IWL39_POWER_LIMIT) ||
  5897. (mode == IWL39_POWER_AC))
  5898. mode = IWL39_POWER_AC;
  5899. else
  5900. mode |= IWL_POWER_ENABLED;
  5901. if (mode != priv->power_mode) {
  5902. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  5903. if (rc) {
  5904. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  5905. goto out;
  5906. }
  5907. priv->power_mode = mode;
  5908. }
  5909. rc = count;
  5910. out:
  5911. mutex_unlock(&priv->mutex);
  5912. return rc;
  5913. }
  5914. #define MAX_WX_STRING 80
  5915. /* Values are in microsecond */
  5916. static const s32 timeout_duration[] = {
  5917. 350000,
  5918. 250000,
  5919. 75000,
  5920. 37000,
  5921. 25000,
  5922. };
  5923. static const s32 period_duration[] = {
  5924. 400000,
  5925. 700000,
  5926. 1000000,
  5927. 1000000,
  5928. 1000000
  5929. };
  5930. static ssize_t show_power_level(struct device *d,
  5931. struct device_attribute *attr, char *buf)
  5932. {
  5933. struct iwl_priv *priv = dev_get_drvdata(d);
  5934. int level = IWL_POWER_LEVEL(priv->power_mode);
  5935. char *p = buf;
  5936. p += sprintf(p, "%d ", level);
  5937. switch (level) {
  5938. case IWL_POWER_MODE_CAM:
  5939. case IWL39_POWER_AC:
  5940. p += sprintf(p, "(AC)");
  5941. break;
  5942. case IWL39_POWER_BATTERY:
  5943. p += sprintf(p, "(BATTERY)");
  5944. break;
  5945. default:
  5946. p += sprintf(p,
  5947. "(Timeout %dms, Period %dms)",
  5948. timeout_duration[level - 1] / 1000,
  5949. period_duration[level - 1] / 1000);
  5950. }
  5951. if (!(priv->power_mode & IWL_POWER_ENABLED))
  5952. p += sprintf(p, " OFF\n");
  5953. else
  5954. p += sprintf(p, " \n");
  5955. return p - buf + 1;
  5956. }
  5957. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  5958. store_power_level);
  5959. static ssize_t show_channels(struct device *d,
  5960. struct device_attribute *attr, char *buf)
  5961. {
  5962. /* all this shit doesn't belong into sysfs anyway */
  5963. return 0;
  5964. }
  5965. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  5966. static ssize_t show_statistics(struct device *d,
  5967. struct device_attribute *attr, char *buf)
  5968. {
  5969. struct iwl_priv *priv = dev_get_drvdata(d);
  5970. u32 size = sizeof(struct iwl3945_notif_statistics);
  5971. u32 len = 0, ofs = 0;
  5972. u8 *data = (u8 *)&priv->statistics_39;
  5973. int rc = 0;
  5974. if (!iwl_is_alive(priv))
  5975. return -EAGAIN;
  5976. mutex_lock(&priv->mutex);
  5977. rc = iwl3945_send_statistics_request(priv);
  5978. mutex_unlock(&priv->mutex);
  5979. if (rc) {
  5980. len = sprintf(buf,
  5981. "Error sending statistics request: 0x%08X\n", rc);
  5982. return len;
  5983. }
  5984. while (size && (PAGE_SIZE - len)) {
  5985. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  5986. PAGE_SIZE - len, 1);
  5987. len = strlen(buf);
  5988. if (PAGE_SIZE - len)
  5989. buf[len++] = '\n';
  5990. ofs += 16;
  5991. size -= min(size, 16U);
  5992. }
  5993. return len;
  5994. }
  5995. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  5996. static ssize_t show_antenna(struct device *d,
  5997. struct device_attribute *attr, char *buf)
  5998. {
  5999. struct iwl_priv *priv = dev_get_drvdata(d);
  6000. if (!iwl_is_alive(priv))
  6001. return -EAGAIN;
  6002. return sprintf(buf, "%d\n", priv->antenna);
  6003. }
  6004. static ssize_t store_antenna(struct device *d,
  6005. struct device_attribute *attr,
  6006. const char *buf, size_t count)
  6007. {
  6008. int ant;
  6009. struct iwl_priv *priv = dev_get_drvdata(d);
  6010. if (count == 0)
  6011. return 0;
  6012. if (sscanf(buf, "%1i", &ant) != 1) {
  6013. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6014. return count;
  6015. }
  6016. if ((ant >= 0) && (ant <= 2)) {
  6017. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6018. priv->antenna = (enum iwl3945_antenna)ant;
  6019. } else
  6020. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6021. return count;
  6022. }
  6023. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6024. static ssize_t show_status(struct device *d,
  6025. struct device_attribute *attr, char *buf)
  6026. {
  6027. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  6028. if (!iwl_is_alive(priv))
  6029. return -EAGAIN;
  6030. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6031. }
  6032. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6033. static ssize_t dump_error_log(struct device *d,
  6034. struct device_attribute *attr,
  6035. const char *buf, size_t count)
  6036. {
  6037. char *p = (char *)buf;
  6038. if (p[0] == '1')
  6039. iwl3945_dump_nic_error_log((struct iwl_priv *)d->driver_data);
  6040. return strnlen(buf, count);
  6041. }
  6042. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6043. static ssize_t dump_event_log(struct device *d,
  6044. struct device_attribute *attr,
  6045. const char *buf, size_t count)
  6046. {
  6047. char *p = (char *)buf;
  6048. if (p[0] == '1')
  6049. iwl3945_dump_nic_event_log((struct iwl_priv *)d->driver_data);
  6050. return strnlen(buf, count);
  6051. }
  6052. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6053. /*****************************************************************************
  6054. *
  6055. * driver setup and tear down
  6056. *
  6057. *****************************************************************************/
  6058. static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
  6059. {
  6060. priv->workqueue = create_workqueue(DRV_NAME);
  6061. init_waitqueue_head(&priv->wait_command_queue);
  6062. INIT_WORK(&priv->up, iwl3945_bg_up);
  6063. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6064. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6065. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6066. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6067. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6068. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6069. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6070. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6071. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6072. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6073. iwl3945_hw_setup_deferred_work(priv);
  6074. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6075. iwl3945_irq_tasklet, (unsigned long)priv);
  6076. }
  6077. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
  6078. {
  6079. iwl3945_hw_cancel_deferred_work(priv);
  6080. cancel_delayed_work_sync(&priv->init_alive_start);
  6081. cancel_delayed_work(&priv->scan_check);
  6082. cancel_delayed_work(&priv->alive_start);
  6083. cancel_work_sync(&priv->beacon_update);
  6084. }
  6085. static struct attribute *iwl3945_sysfs_entries[] = {
  6086. &dev_attr_antenna.attr,
  6087. &dev_attr_channels.attr,
  6088. &dev_attr_dump_errors.attr,
  6089. &dev_attr_dump_events.attr,
  6090. &dev_attr_flags.attr,
  6091. &dev_attr_filter_flags.attr,
  6092. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6093. &dev_attr_measurement.attr,
  6094. #endif
  6095. &dev_attr_power_level.attr,
  6096. &dev_attr_retry_rate.attr,
  6097. &dev_attr_statistics.attr,
  6098. &dev_attr_status.attr,
  6099. &dev_attr_temperature.attr,
  6100. &dev_attr_tx_power.attr,
  6101. #ifdef CONFIG_IWL3945_DEBUG
  6102. &dev_attr_debug_level.attr,
  6103. #endif
  6104. NULL
  6105. };
  6106. static struct attribute_group iwl3945_attribute_group = {
  6107. .name = NULL, /* put in device directory */
  6108. .attrs = iwl3945_sysfs_entries,
  6109. };
  6110. static struct ieee80211_ops iwl3945_hw_ops = {
  6111. .tx = iwl3945_mac_tx,
  6112. .start = iwl3945_mac_start,
  6113. .stop = iwl3945_mac_stop,
  6114. .add_interface = iwl3945_mac_add_interface,
  6115. .remove_interface = iwl3945_mac_remove_interface,
  6116. .config = iwl3945_mac_config,
  6117. .config_interface = iwl3945_mac_config_interface,
  6118. .configure_filter = iwl3945_configure_filter,
  6119. .set_key = iwl3945_mac_set_key,
  6120. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6121. .conf_tx = iwl3945_mac_conf_tx,
  6122. .reset_tsf = iwl3945_mac_reset_tsf,
  6123. .bss_info_changed = iwl3945_bss_info_changed,
  6124. .hw_scan = iwl3945_mac_hw_scan
  6125. };
  6126. int iwl3945_init_drv(struct iwl_priv *priv)
  6127. {
  6128. int ret;
  6129. priv->retry_rate = 1;
  6130. priv->ibss_beacon = NULL;
  6131. spin_lock_init(&priv->lock);
  6132. spin_lock_init(&priv->power_data.lock);
  6133. spin_lock_init(&priv->sta_lock);
  6134. spin_lock_init(&priv->hcmd_lock);
  6135. INIT_LIST_HEAD(&priv->free_frames);
  6136. mutex_init(&priv->mutex);
  6137. /* Clear the driver's (not device's) station table */
  6138. iwl3945_clear_stations_table(priv);
  6139. priv->data_retry_limit = -1;
  6140. priv->ieee_channels = NULL;
  6141. priv->ieee_rates = NULL;
  6142. priv->band = IEEE80211_BAND_2GHZ;
  6143. priv->iw_mode = NL80211_IFTYPE_STATION;
  6144. iwl_reset_qos(priv);
  6145. priv->qos_data.qos_active = 0;
  6146. priv->qos_data.qos_cap.val = 0;
  6147. priv->rates_mask = IWL_RATES_MASK;
  6148. /* If power management is turned on, default to AC mode */
  6149. priv->power_mode = IWL_POWER_AC;
  6150. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6151. ret = iwl3945_init_channel_map(priv);
  6152. if (ret) {
  6153. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  6154. goto err;
  6155. }
  6156. ret = iwl3945_init_geos(priv);
  6157. if (ret) {
  6158. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  6159. goto err_free_channel_map;
  6160. }
  6161. return 0;
  6162. err_free_channel_map:
  6163. iwl3945_free_channel_map(priv);
  6164. err:
  6165. return ret;
  6166. }
  6167. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6168. {
  6169. int err = 0;
  6170. struct iwl_priv *priv;
  6171. struct ieee80211_hw *hw;
  6172. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  6173. unsigned long flags;
  6174. /***********************
  6175. * 1. Allocating HW data
  6176. * ********************/
  6177. /* mac80211 allocates memory for this device instance, including
  6178. * space for this driver's private structure */
  6179. hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
  6180. if (hw == NULL) {
  6181. printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
  6182. err = -ENOMEM;
  6183. goto out;
  6184. }
  6185. priv = hw->priv;
  6186. SET_IEEE80211_DEV(hw, &pdev->dev);
  6187. if ((iwl3945_mod_params.num_of_queues > IWL39_MAX_NUM_QUEUES) ||
  6188. (iwl3945_mod_params.num_of_queues < IWL_MIN_NUM_QUEUES)) {
  6189. IWL_ERR(priv,
  6190. "invalid queues_num, should be between %d and %d\n",
  6191. IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
  6192. err = -EINVAL;
  6193. goto out;
  6194. }
  6195. /*
  6196. * Disabling hardware scan means that mac80211 will perform scans
  6197. * "the hard way", rather than using device's scan.
  6198. */
  6199. if (iwl3945_mod_params.disable_hw_scan) {
  6200. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6201. iwl3945_hw_ops.hw_scan = NULL;
  6202. }
  6203. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6204. priv->cfg = cfg;
  6205. priv->pci_dev = pdev;
  6206. #ifdef CONFIG_IWL3945_DEBUG
  6207. priv->debug_level = iwl3945_mod_params.debug;
  6208. atomic_set(&priv->restrict_refcnt, 0);
  6209. #endif
  6210. hw->rate_control_algorithm = "iwl-3945-rs";
  6211. hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
  6212. /* Select antenna (may be helpful if only one antenna is connected) */
  6213. priv->antenna = (enum iwl3945_antenna)iwl3945_mod_params.antenna;
  6214. /* Tell mac80211 our characteristics */
  6215. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  6216. IEEE80211_HW_NOISE_DBM;
  6217. hw->wiphy->interface_modes =
  6218. BIT(NL80211_IFTYPE_STATION) |
  6219. BIT(NL80211_IFTYPE_ADHOC);
  6220. hw->wiphy->fw_handles_regulatory = true;
  6221. /* 4 EDCA QOS priorities */
  6222. hw->queues = 4;
  6223. /***************************
  6224. * 2. Initializing PCI bus
  6225. * *************************/
  6226. if (pci_enable_device(pdev)) {
  6227. err = -ENODEV;
  6228. goto out_ieee80211_free_hw;
  6229. }
  6230. pci_set_master(pdev);
  6231. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6232. if (!err)
  6233. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6234. if (err) {
  6235. IWL_WARN(priv, "No suitable DMA available.\n");
  6236. goto out_pci_disable_device;
  6237. }
  6238. pci_set_drvdata(pdev, priv);
  6239. err = pci_request_regions(pdev, DRV_NAME);
  6240. if (err)
  6241. goto out_pci_disable_device;
  6242. /***********************
  6243. * 3. Read REV Register
  6244. * ********************/
  6245. priv->hw_base = pci_iomap(pdev, 0, 0);
  6246. if (!priv->hw_base) {
  6247. err = -ENODEV;
  6248. goto out_pci_release_regions;
  6249. }
  6250. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6251. (unsigned long long) pci_resource_len(pdev, 0));
  6252. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6253. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6254. * PCI Tx retries from interfering with C3 CPU state */
  6255. pci_write_config_byte(pdev, 0x41, 0x00);
  6256. /* amp init */
  6257. err = priv->cfg->ops->lib->apm_ops.init(priv);
  6258. if (err < 0) {
  6259. IWL_DEBUG_INFO("Failed to init APMG\n");
  6260. goto out_iounmap;
  6261. }
  6262. /***********************
  6263. * 4. Read EEPROM
  6264. * ********************/
  6265. /* Read the EEPROM */
  6266. err = iwl3945_eeprom_init(priv);
  6267. if (err) {
  6268. IWL_ERR(priv, "Unable to init EEPROM\n");
  6269. goto out_remove_sysfs;
  6270. }
  6271. /* MAC Address location in EEPROM same for 3945/4965 */
  6272. get_eeprom_mac(priv, priv->mac_addr);
  6273. IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
  6274. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  6275. /***********************
  6276. * 5. Setup HW Constants
  6277. * ********************/
  6278. /* Device-specific setup */
  6279. if (iwl3945_hw_set_hw_params(priv)) {
  6280. IWL_ERR(priv, "failed to set hw settings\n");
  6281. goto out_iounmap;
  6282. }
  6283. /***********************
  6284. * 6. Setup priv
  6285. * ********************/
  6286. err = iwl3945_init_drv(priv);
  6287. if (err) {
  6288. IWL_ERR(priv, "initializing driver failed\n");
  6289. goto out_free_geos;
  6290. }
  6291. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
  6292. priv->cfg->name);
  6293. /***********************************
  6294. * 7. Initialize Module Parameters
  6295. * **********************************/
  6296. /* Initialize module parameter values here */
  6297. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6298. if (iwl3945_mod_params.disable) {
  6299. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6300. IWL_DEBUG_INFO("Radio disabled.\n");
  6301. }
  6302. /***********************
  6303. * 8. Setup Services
  6304. * ********************/
  6305. spin_lock_irqsave(&priv->lock, flags);
  6306. iwl3945_disable_interrupts(priv);
  6307. spin_unlock_irqrestore(&priv->lock, flags);
  6308. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6309. if (err) {
  6310. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  6311. goto out_release_irq;
  6312. }
  6313. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6314. iwl3945_setup_deferred_work(priv);
  6315. iwl3945_setup_rx_handlers(priv);
  6316. /***********************
  6317. * 9. Conclude
  6318. * ********************/
  6319. pci_save_state(pdev);
  6320. pci_disable_device(pdev);
  6321. /*********************************
  6322. * 10. Setup and Register mac80211
  6323. * *******************************/
  6324. err = ieee80211_register_hw(priv->hw);
  6325. if (err) {
  6326. IWL_ERR(priv, "Failed to register network device: %d\n", err);
  6327. goto out_remove_sysfs;
  6328. }
  6329. priv->hw->conf.beacon_int = 100;
  6330. priv->mac80211_registered = 1;
  6331. err = iwl3945_rfkill_init(priv);
  6332. if (err)
  6333. IWL_ERR(priv, "Unable to initialize RFKILL system. "
  6334. "Ignoring error: %d\n", err);
  6335. return 0;
  6336. out_remove_sysfs:
  6337. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6338. out_free_geos:
  6339. iwl3945_free_geos(priv);
  6340. out_release_irq:
  6341. destroy_workqueue(priv->workqueue);
  6342. priv->workqueue = NULL;
  6343. iwl3945_unset_hw_params(priv);
  6344. out_iounmap:
  6345. pci_iounmap(pdev, priv->hw_base);
  6346. out_pci_release_regions:
  6347. pci_release_regions(pdev);
  6348. out_pci_disable_device:
  6349. pci_disable_device(pdev);
  6350. pci_set_drvdata(pdev, NULL);
  6351. out_ieee80211_free_hw:
  6352. ieee80211_free_hw(priv->hw);
  6353. out:
  6354. return err;
  6355. }
  6356. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  6357. {
  6358. struct iwl_priv *priv = pci_get_drvdata(pdev);
  6359. unsigned long flags;
  6360. if (!priv)
  6361. return;
  6362. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  6363. set_bit(STATUS_EXIT_PENDING, &priv->status);
  6364. if (priv->mac80211_registered) {
  6365. ieee80211_unregister_hw(priv->hw);
  6366. priv->mac80211_registered = 0;
  6367. } else {
  6368. iwl3945_down(priv);
  6369. }
  6370. /* make sure we flush any pending irq or
  6371. * tasklet for the driver
  6372. */
  6373. spin_lock_irqsave(&priv->lock, flags);
  6374. iwl3945_disable_interrupts(priv);
  6375. spin_unlock_irqrestore(&priv->lock, flags);
  6376. iwl_synchronize_irq(priv);
  6377. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6378. iwl3945_rfkill_unregister(priv);
  6379. iwl3945_dealloc_ucode_pci(priv);
  6380. if (priv->rxq.bd)
  6381. iwl3945_rx_queue_free(priv, &priv->rxq);
  6382. iwl3945_hw_txq_ctx_free(priv);
  6383. iwl3945_unset_hw_params(priv);
  6384. iwl3945_clear_stations_table(priv);
  6385. /*netif_stop_queue(dev); */
  6386. flush_workqueue(priv->workqueue);
  6387. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  6388. * priv->workqueue... so we can't take down the workqueue
  6389. * until now... */
  6390. destroy_workqueue(priv->workqueue);
  6391. priv->workqueue = NULL;
  6392. pci_iounmap(pdev, priv->hw_base);
  6393. pci_release_regions(pdev);
  6394. pci_disable_device(pdev);
  6395. pci_set_drvdata(pdev, NULL);
  6396. iwl3945_free_channel_map(priv);
  6397. iwl3945_free_geos(priv);
  6398. kfree(priv->scan39);
  6399. if (priv->ibss_beacon)
  6400. dev_kfree_skb(priv->ibss_beacon);
  6401. ieee80211_free_hw(priv->hw);
  6402. }
  6403. #ifdef CONFIG_PM
  6404. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  6405. {
  6406. struct iwl_priv *priv = pci_get_drvdata(pdev);
  6407. if (priv->is_open) {
  6408. set_bit(STATUS_IN_SUSPEND, &priv->status);
  6409. iwl3945_mac_stop(priv->hw);
  6410. priv->is_open = 1;
  6411. }
  6412. pci_set_power_state(pdev, PCI_D3hot);
  6413. return 0;
  6414. }
  6415. static int iwl3945_pci_resume(struct pci_dev *pdev)
  6416. {
  6417. struct iwl_priv *priv = pci_get_drvdata(pdev);
  6418. pci_set_power_state(pdev, PCI_D0);
  6419. if (priv->is_open)
  6420. iwl3945_mac_start(priv->hw);
  6421. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  6422. return 0;
  6423. }
  6424. #endif /* CONFIG_PM */
  6425. /*************** RFKILL FUNCTIONS **********/
  6426. #ifdef CONFIG_IWL3945_RFKILL
  6427. /* software rf-kill from user */
  6428. static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
  6429. {
  6430. struct iwl_priv *priv = data;
  6431. int err = 0;
  6432. if (!priv->rfkill)
  6433. return 0;
  6434. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  6435. return 0;
  6436. IWL_DEBUG_RF_KILL("we received soft RFKILL set to state %d\n", state);
  6437. mutex_lock(&priv->mutex);
  6438. switch (state) {
  6439. case RFKILL_STATE_UNBLOCKED:
  6440. if (iwl_is_rfkill_hw(priv)) {
  6441. err = -EBUSY;
  6442. goto out_unlock;
  6443. }
  6444. iwl3945_radio_kill_sw(priv, 0);
  6445. break;
  6446. case RFKILL_STATE_SOFT_BLOCKED:
  6447. iwl3945_radio_kill_sw(priv, 1);
  6448. break;
  6449. default:
  6450. IWL_WARN(priv, "received unexpected RFKILL state %d\n", state);
  6451. break;
  6452. }
  6453. out_unlock:
  6454. mutex_unlock(&priv->mutex);
  6455. return err;
  6456. }
  6457. int iwl3945_rfkill_init(struct iwl_priv *priv)
  6458. {
  6459. struct device *device = wiphy_dev(priv->hw->wiphy);
  6460. int ret = 0;
  6461. BUG_ON(device == NULL);
  6462. IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
  6463. priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
  6464. if (!priv->rfkill) {
  6465. IWL_ERR(priv, "Unable to allocate rfkill device.\n");
  6466. ret = -ENOMEM;
  6467. goto error;
  6468. }
  6469. priv->rfkill->name = priv->cfg->name;
  6470. priv->rfkill->data = priv;
  6471. priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
  6472. priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
  6473. priv->rfkill->user_claim_unsupported = 1;
  6474. priv->rfkill->dev.class->suspend = NULL;
  6475. priv->rfkill->dev.class->resume = NULL;
  6476. ret = rfkill_register(priv->rfkill);
  6477. if (ret) {
  6478. IWL_ERR(priv, "Unable to register rfkill: %d\n", ret);
  6479. goto freed_rfkill;
  6480. }
  6481. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6482. return ret;
  6483. freed_rfkill:
  6484. if (priv->rfkill != NULL)
  6485. rfkill_free(priv->rfkill);
  6486. priv->rfkill = NULL;
  6487. error:
  6488. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6489. return ret;
  6490. }
  6491. void iwl3945_rfkill_unregister(struct iwl_priv *priv)
  6492. {
  6493. if (priv->rfkill)
  6494. rfkill_unregister(priv->rfkill);
  6495. priv->rfkill = NULL;
  6496. }
  6497. /* set rf-kill to the right state. */
  6498. void iwl3945_rfkill_set_hw_state(struct iwl_priv *priv)
  6499. {
  6500. if (!priv->rfkill)
  6501. return;
  6502. if (iwl_is_rfkill_hw(priv)) {
  6503. rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
  6504. return;
  6505. }
  6506. if (!iwl_is_rfkill_sw(priv))
  6507. rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
  6508. else
  6509. rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
  6510. }
  6511. #endif
  6512. /*****************************************************************************
  6513. *
  6514. * driver and module entry point
  6515. *
  6516. *****************************************************************************/
  6517. static struct pci_driver iwl3945_driver = {
  6518. .name = DRV_NAME,
  6519. .id_table = iwl3945_hw_card_ids,
  6520. .probe = iwl3945_pci_probe,
  6521. .remove = __devexit_p(iwl3945_pci_remove),
  6522. #ifdef CONFIG_PM
  6523. .suspend = iwl3945_pci_suspend,
  6524. .resume = iwl3945_pci_resume,
  6525. #endif
  6526. };
  6527. static int __init iwl3945_init(void)
  6528. {
  6529. int ret;
  6530. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  6531. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  6532. ret = iwl3945_rate_control_register();
  6533. if (ret) {
  6534. printk(KERN_ERR DRV_NAME
  6535. "Unable to register rate control algorithm: %d\n", ret);
  6536. return ret;
  6537. }
  6538. ret = pci_register_driver(&iwl3945_driver);
  6539. if (ret) {
  6540. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  6541. goto error_register;
  6542. }
  6543. return ret;
  6544. error_register:
  6545. iwl3945_rate_control_unregister();
  6546. return ret;
  6547. }
  6548. static void __exit iwl3945_exit(void)
  6549. {
  6550. pci_unregister_driver(&iwl3945_driver);
  6551. iwl3945_rate_control_unregister();
  6552. }
  6553. MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
  6554. module_param_named(antenna, iwl3945_mod_params.antenna, int, 0444);
  6555. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  6556. module_param_named(disable, iwl3945_mod_params.disable, int, 0444);
  6557. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  6558. module_param_named(hwcrypto, iwl3945_mod_params.sw_crypto, int, 0444);
  6559. MODULE_PARM_DESC(hwcrypto,
  6560. "using hardware crypto engine (default 0 [software])\n");
  6561. module_param_named(debug, iwl3945_mod_params.debug, uint, 0444);
  6562. MODULE_PARM_DESC(debug, "debug output mask");
  6563. module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, int, 0444);
  6564. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  6565. module_param_named(queues_num, iwl3945_mod_params.num_of_queues, int, 0444);
  6566. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  6567. module_exit(iwl3945_exit);
  6568. module_init(iwl3945_init);