netxen_nic_init.c 39 KB

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  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen Inc,
  26. * 18922 Forge Drive
  27. * Cupertino, CA 95014-0701
  28. *
  29. */
  30. #include <linux/netdevice.h>
  31. #include <linux/delay.h>
  32. #include "netxen_nic.h"
  33. #include "netxen_nic_hw.h"
  34. struct crb_addr_pair {
  35. u32 addr;
  36. u32 data;
  37. };
  38. #define NETXEN_MAX_CRB_XFORM 60
  39. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  40. #define NETXEN_ADDR_ERROR (0xffffffff)
  41. #define crb_addr_transform(name) \
  42. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  43. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  44. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  45. static void
  46. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  47. struct nx_host_rds_ring *rds_ring);
  48. static void crb_addr_transform_setup(void)
  49. {
  50. crb_addr_transform(XDMA);
  51. crb_addr_transform(TIMR);
  52. crb_addr_transform(SRE);
  53. crb_addr_transform(SQN3);
  54. crb_addr_transform(SQN2);
  55. crb_addr_transform(SQN1);
  56. crb_addr_transform(SQN0);
  57. crb_addr_transform(SQS3);
  58. crb_addr_transform(SQS2);
  59. crb_addr_transform(SQS1);
  60. crb_addr_transform(SQS0);
  61. crb_addr_transform(RPMX7);
  62. crb_addr_transform(RPMX6);
  63. crb_addr_transform(RPMX5);
  64. crb_addr_transform(RPMX4);
  65. crb_addr_transform(RPMX3);
  66. crb_addr_transform(RPMX2);
  67. crb_addr_transform(RPMX1);
  68. crb_addr_transform(RPMX0);
  69. crb_addr_transform(ROMUSB);
  70. crb_addr_transform(SN);
  71. crb_addr_transform(QMN);
  72. crb_addr_transform(QMS);
  73. crb_addr_transform(PGNI);
  74. crb_addr_transform(PGND);
  75. crb_addr_transform(PGN3);
  76. crb_addr_transform(PGN2);
  77. crb_addr_transform(PGN1);
  78. crb_addr_transform(PGN0);
  79. crb_addr_transform(PGSI);
  80. crb_addr_transform(PGSD);
  81. crb_addr_transform(PGS3);
  82. crb_addr_transform(PGS2);
  83. crb_addr_transform(PGS1);
  84. crb_addr_transform(PGS0);
  85. crb_addr_transform(PS);
  86. crb_addr_transform(PH);
  87. crb_addr_transform(NIU);
  88. crb_addr_transform(I2Q);
  89. crb_addr_transform(EG);
  90. crb_addr_transform(MN);
  91. crb_addr_transform(MS);
  92. crb_addr_transform(CAS2);
  93. crb_addr_transform(CAS1);
  94. crb_addr_transform(CAS0);
  95. crb_addr_transform(CAM);
  96. crb_addr_transform(C2C1);
  97. crb_addr_transform(C2C0);
  98. crb_addr_transform(SMB);
  99. crb_addr_transform(OCM0);
  100. crb_addr_transform(I2C0);
  101. }
  102. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  103. {
  104. struct netxen_recv_context *recv_ctx;
  105. struct nx_host_rds_ring *rds_ring;
  106. struct netxen_rx_buffer *rx_buf;
  107. int i, ring;
  108. recv_ctx = &adapter->recv_ctx;
  109. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  110. rds_ring = &recv_ctx->rds_rings[ring];
  111. for (i = 0; i < rds_ring->num_desc; ++i) {
  112. rx_buf = &(rds_ring->rx_buf_arr[i]);
  113. if (rx_buf->state == NETXEN_BUFFER_FREE)
  114. continue;
  115. pci_unmap_single(adapter->pdev,
  116. rx_buf->dma,
  117. rds_ring->dma_size,
  118. PCI_DMA_FROMDEVICE);
  119. if (rx_buf->skb != NULL)
  120. dev_kfree_skb_any(rx_buf->skb);
  121. }
  122. }
  123. }
  124. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  125. {
  126. struct netxen_cmd_buffer *cmd_buf;
  127. struct netxen_skb_frag *buffrag;
  128. int i, j;
  129. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  130. cmd_buf = tx_ring->cmd_buf_arr;
  131. for (i = 0; i < tx_ring->num_desc; i++) {
  132. buffrag = cmd_buf->frag_array;
  133. if (buffrag->dma) {
  134. pci_unmap_single(adapter->pdev, buffrag->dma,
  135. buffrag->length, PCI_DMA_TODEVICE);
  136. buffrag->dma = 0ULL;
  137. }
  138. for (j = 0; j < cmd_buf->frag_count; j++) {
  139. buffrag++;
  140. if (buffrag->dma) {
  141. pci_unmap_page(adapter->pdev, buffrag->dma,
  142. buffrag->length,
  143. PCI_DMA_TODEVICE);
  144. buffrag->dma = 0ULL;
  145. }
  146. }
  147. if (cmd_buf->skb) {
  148. dev_kfree_skb_any(cmd_buf->skb);
  149. cmd_buf->skb = NULL;
  150. }
  151. cmd_buf++;
  152. }
  153. }
  154. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  155. {
  156. struct netxen_recv_context *recv_ctx;
  157. struct nx_host_rds_ring *rds_ring;
  158. struct nx_host_tx_ring *tx_ring;
  159. int ring;
  160. recv_ctx = &adapter->recv_ctx;
  161. if (recv_ctx->rds_rings == NULL)
  162. goto skip_rds;
  163. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  164. rds_ring = &recv_ctx->rds_rings[ring];
  165. vfree(rds_ring->rx_buf_arr);
  166. rds_ring->rx_buf_arr = NULL;
  167. }
  168. kfree(recv_ctx->rds_rings);
  169. skip_rds:
  170. if (adapter->tx_ring == NULL)
  171. return;
  172. tx_ring = adapter->tx_ring;
  173. vfree(tx_ring->cmd_buf_arr);
  174. }
  175. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  176. {
  177. struct netxen_recv_context *recv_ctx;
  178. struct nx_host_rds_ring *rds_ring;
  179. struct nx_host_sds_ring *sds_ring;
  180. struct nx_host_tx_ring *tx_ring;
  181. struct netxen_rx_buffer *rx_buf;
  182. int ring, i, size;
  183. struct netxen_cmd_buffer *cmd_buf_arr;
  184. struct net_device *netdev = adapter->netdev;
  185. struct pci_dev *pdev = adapter->pdev;
  186. size = sizeof(struct nx_host_tx_ring);
  187. tx_ring = kzalloc(size, GFP_KERNEL);
  188. if (tx_ring == NULL) {
  189. dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
  190. netdev->name);
  191. return -ENOMEM;
  192. }
  193. adapter->tx_ring = tx_ring;
  194. tx_ring->num_desc = adapter->num_txd;
  195. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  196. cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  197. if (cmd_buf_arr == NULL) {
  198. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  199. netdev->name);
  200. return -ENOMEM;
  201. }
  202. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  203. tx_ring->cmd_buf_arr = cmd_buf_arr;
  204. recv_ctx = &adapter->recv_ctx;
  205. size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
  206. rds_ring = kzalloc(size, GFP_KERNEL);
  207. if (rds_ring == NULL) {
  208. dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
  209. netdev->name);
  210. return -ENOMEM;
  211. }
  212. recv_ctx->rds_rings = rds_ring;
  213. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  214. rds_ring = &recv_ctx->rds_rings[ring];
  215. switch (ring) {
  216. case RCV_RING_NORMAL:
  217. rds_ring->num_desc = adapter->num_rxd;
  218. if (adapter->ahw.cut_through) {
  219. rds_ring->dma_size =
  220. NX_CT_DEFAULT_RX_BUF_LEN;
  221. rds_ring->skb_size =
  222. NX_CT_DEFAULT_RX_BUF_LEN;
  223. } else {
  224. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  225. rds_ring->dma_size =
  226. NX_P3_RX_BUF_MAX_LEN;
  227. else
  228. rds_ring->dma_size =
  229. NX_P2_RX_BUF_MAX_LEN;
  230. rds_ring->skb_size =
  231. rds_ring->dma_size + NET_IP_ALIGN;
  232. }
  233. break;
  234. case RCV_RING_JUMBO:
  235. rds_ring->num_desc = adapter->num_jumbo_rxd;
  236. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  237. rds_ring->dma_size =
  238. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  239. else
  240. rds_ring->dma_size =
  241. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  242. rds_ring->skb_size =
  243. rds_ring->dma_size + NET_IP_ALIGN;
  244. break;
  245. case RCV_RING_LRO:
  246. rds_ring->num_desc = adapter->num_lro_rxd;
  247. rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
  248. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  249. break;
  250. }
  251. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  252. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  253. if (rds_ring->rx_buf_arr == NULL) {
  254. printk(KERN_ERR "%s: Failed to allocate "
  255. "rx buffer ring %d\n",
  256. netdev->name, ring);
  257. /* free whatever was already allocated */
  258. goto err_out;
  259. }
  260. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  261. INIT_LIST_HEAD(&rds_ring->free_list);
  262. /*
  263. * Now go through all of them, set reference handles
  264. * and put them in the queues.
  265. */
  266. rx_buf = rds_ring->rx_buf_arr;
  267. for (i = 0; i < rds_ring->num_desc; i++) {
  268. list_add_tail(&rx_buf->list,
  269. &rds_ring->free_list);
  270. rx_buf->ref_handle = i;
  271. rx_buf->state = NETXEN_BUFFER_FREE;
  272. rx_buf++;
  273. }
  274. spin_lock_init(&rds_ring->lock);
  275. }
  276. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  277. sds_ring = &recv_ctx->sds_rings[ring];
  278. sds_ring->irq = adapter->msix_entries[ring].vector;
  279. sds_ring->adapter = adapter;
  280. sds_ring->num_desc = adapter->num_rxd;
  281. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  282. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  283. }
  284. return 0;
  285. err_out:
  286. netxen_free_sw_resources(adapter);
  287. return -ENOMEM;
  288. }
  289. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  290. {
  291. adapter->init_port = netxen_niu_xg_init_port;
  292. adapter->stop_port = netxen_niu_disable_xg_port;
  293. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  294. adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
  295. adapter->set_multi = netxen_p2_nic_set_multi;
  296. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  297. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  298. } else {
  299. adapter->set_mtu = nx_fw_cmd_set_mtu;
  300. adapter->set_promisc = netxen_p3_nic_set_promisc;
  301. adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
  302. adapter->set_multi = netxen_p3_nic_set_multi;
  303. }
  304. if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
  305. adapter->phy_read = netxen_niu_gbe_phy_read;
  306. adapter->phy_write = netxen_niu_gbe_phy_write;
  307. }
  308. }
  309. /*
  310. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  311. * address to external PCI CRB address.
  312. */
  313. static u32 netxen_decode_crb_addr(u32 addr)
  314. {
  315. int i;
  316. u32 base_addr, offset, pci_base;
  317. crb_addr_transform_setup();
  318. pci_base = NETXEN_ADDR_ERROR;
  319. base_addr = addr & 0xfff00000;
  320. offset = addr & 0x000fffff;
  321. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  322. if (crb_addr_xform[i] == base_addr) {
  323. pci_base = i << 20;
  324. break;
  325. }
  326. }
  327. if (pci_base == NETXEN_ADDR_ERROR)
  328. return pci_base;
  329. else
  330. return (pci_base + offset);
  331. }
  332. static long rom_max_timeout = 100;
  333. static long rom_lock_timeout = 10000;
  334. static int rom_lock(struct netxen_adapter *adapter)
  335. {
  336. int iter;
  337. u32 done = 0;
  338. int timeout = 0;
  339. while (!done) {
  340. /* acquire semaphore2 from PCI HW block */
  341. done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK));
  342. if (done == 1)
  343. break;
  344. if (timeout >= rom_lock_timeout)
  345. return -EIO;
  346. timeout++;
  347. /*
  348. * Yield CPU
  349. */
  350. if (!in_atomic())
  351. schedule();
  352. else {
  353. for (iter = 0; iter < 20; iter++)
  354. cpu_relax(); /*This a nop instr on i386 */
  355. }
  356. }
  357. NXWR32(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  358. return 0;
  359. }
  360. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  361. {
  362. long timeout = 0;
  363. long done = 0;
  364. cond_resched();
  365. while (done == 0) {
  366. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  367. done &= 2;
  368. timeout++;
  369. if (timeout >= rom_max_timeout) {
  370. printk("Timeout reached waiting for rom done");
  371. return -EIO;
  372. }
  373. }
  374. return 0;
  375. }
  376. static void netxen_rom_unlock(struct netxen_adapter *adapter)
  377. {
  378. /* release semaphore2 */
  379. NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK));
  380. }
  381. static int do_rom_fast_read(struct netxen_adapter *adapter,
  382. int addr, int *valp)
  383. {
  384. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  385. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  386. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  387. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  388. if (netxen_wait_rom_done(adapter)) {
  389. printk("Error waiting for rom done\n");
  390. return -EIO;
  391. }
  392. /* reset abyte_cnt and dummy_byte_cnt */
  393. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  394. udelay(10);
  395. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  396. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  397. return 0;
  398. }
  399. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  400. u8 *bytes, size_t size)
  401. {
  402. int addridx;
  403. int ret = 0;
  404. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  405. int v;
  406. ret = do_rom_fast_read(adapter, addridx, &v);
  407. if (ret != 0)
  408. break;
  409. *(__le32 *)bytes = cpu_to_le32(v);
  410. bytes += 4;
  411. }
  412. return ret;
  413. }
  414. int
  415. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  416. u8 *bytes, size_t size)
  417. {
  418. int ret;
  419. ret = rom_lock(adapter);
  420. if (ret < 0)
  421. return ret;
  422. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  423. netxen_rom_unlock(adapter);
  424. return ret;
  425. }
  426. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  427. {
  428. int ret;
  429. if (rom_lock(adapter) != 0)
  430. return -EIO;
  431. ret = do_rom_fast_read(adapter, addr, valp);
  432. netxen_rom_unlock(adapter);
  433. return ret;
  434. }
  435. #define NETXEN_BOARDTYPE 0x4008
  436. #define NETXEN_BOARDNUM 0x400c
  437. #define NETXEN_CHIPNUM 0x4010
  438. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  439. {
  440. int addr, val;
  441. int i, n, init_delay = 0;
  442. struct crb_addr_pair *buf;
  443. unsigned offset;
  444. u32 off;
  445. /* resetall */
  446. rom_lock(adapter);
  447. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
  448. netxen_rom_unlock(adapter);
  449. if (verbose) {
  450. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  451. printk("P2 ROM board type: 0x%08x\n", val);
  452. else
  453. printk("Could not read board type\n");
  454. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  455. printk("P2 ROM board num: 0x%08x\n", val);
  456. else
  457. printk("Could not read board number\n");
  458. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  459. printk("P2 ROM chip num: 0x%08x\n", val);
  460. else
  461. printk("Could not read chip number\n");
  462. }
  463. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  464. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  465. (n != 0xcafecafe) ||
  466. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  467. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  468. "n: %08x\n", netxen_nic_driver_name, n);
  469. return -EIO;
  470. }
  471. offset = n & 0xffffU;
  472. n = (n >> 16) & 0xffffU;
  473. } else {
  474. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  475. !(n & 0x80000000)) {
  476. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  477. "n: %08x\n", netxen_nic_driver_name, n);
  478. return -EIO;
  479. }
  480. offset = 1;
  481. n &= ~0x80000000;
  482. }
  483. if (n < 1024) {
  484. if (verbose)
  485. printk(KERN_DEBUG "%s: %d CRB init values found"
  486. " in ROM.\n", netxen_nic_driver_name, n);
  487. } else {
  488. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  489. " initialized.\n", __func__, n);
  490. return -EIO;
  491. }
  492. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  493. if (buf == NULL) {
  494. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  495. netxen_nic_driver_name);
  496. return -ENOMEM;
  497. }
  498. for (i = 0; i < n; i++) {
  499. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  500. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  501. kfree(buf);
  502. return -EIO;
  503. }
  504. buf[i].addr = addr;
  505. buf[i].data = val;
  506. if (verbose)
  507. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  508. netxen_nic_driver_name,
  509. (u32)netxen_decode_crb_addr(addr), val);
  510. }
  511. for (i = 0; i < n; i++) {
  512. off = netxen_decode_crb_addr(buf[i].addr);
  513. if (off == NETXEN_ADDR_ERROR) {
  514. printk(KERN_ERR"CRB init value out of range %x\n",
  515. buf[i].addr);
  516. continue;
  517. }
  518. off += NETXEN_PCI_CRBSPACE;
  519. /* skipping cold reboot MAGIC */
  520. if (off == NETXEN_CAM_RAM(0x1fc))
  521. continue;
  522. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  523. /* do not reset PCI */
  524. if (off == (ROMUSB_GLB + 0xbc))
  525. continue;
  526. if (off == (ROMUSB_GLB + 0xa8))
  527. continue;
  528. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  529. continue;
  530. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  531. continue;
  532. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  533. continue;
  534. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  535. buf[i].data = 0x1020;
  536. /* skip the function enable register */
  537. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  538. continue;
  539. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  540. continue;
  541. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  542. continue;
  543. }
  544. if (off == NETXEN_ADDR_ERROR) {
  545. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  546. netxen_nic_driver_name, buf[i].addr);
  547. continue;
  548. }
  549. init_delay = 1;
  550. /* After writing this register, HW needs time for CRB */
  551. /* to quiet down (else crb_window returns 0xffffffff) */
  552. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  553. init_delay = 1000;
  554. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  555. /* hold xdma in reset also */
  556. buf[i].data = NETXEN_NIC_XDMA_RESET;
  557. buf[i].data = 0x8000ff;
  558. }
  559. }
  560. NXWR32(adapter, off, buf[i].data);
  561. msleep(init_delay);
  562. }
  563. kfree(buf);
  564. /* disable_peg_cache_all */
  565. /* unreset_net_cache */
  566. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  567. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  568. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  569. }
  570. /* p2dn replyCount */
  571. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  572. /* disable_peg_cache 0 */
  573. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  574. /* disable_peg_cache 1 */
  575. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  576. /* peg_clr_all */
  577. /* peg_clr 0 */
  578. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  579. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  580. /* peg_clr 1 */
  581. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  582. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  583. /* peg_clr 2 */
  584. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  585. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  586. /* peg_clr 3 */
  587. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  588. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  589. return 0;
  590. }
  591. int
  592. netxen_need_fw_reset(struct netxen_adapter *adapter)
  593. {
  594. u32 count, old_count;
  595. u32 val, version, major, minor, build;
  596. int i, timeout;
  597. u8 fw_type;
  598. /* NX2031 firmware doesn't support heartbit */
  599. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  600. return 1;
  601. /* last attempt had failed */
  602. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  603. return 1;
  604. old_count = count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  605. for (i = 0; i < 10; i++) {
  606. timeout = msleep_interruptible(200);
  607. if (timeout) {
  608. NXWR32(adapter, CRB_CMDPEG_STATE,
  609. PHAN_INITIALIZE_FAILED);
  610. return -EINTR;
  611. }
  612. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  613. if (count != old_count)
  614. break;
  615. }
  616. /* firmware is dead */
  617. if (count == old_count)
  618. return 1;
  619. /* check if we have got newer or different file firmware */
  620. if (adapter->fw) {
  621. const struct firmware *fw = adapter->fw;
  622. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  623. version = NETXEN_DECODE_VERSION(val);
  624. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  625. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  626. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  627. if (version > NETXEN_VERSION_CODE(major, minor, build))
  628. return 1;
  629. if (version == NETXEN_VERSION_CODE(major, minor, build)) {
  630. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  631. fw_type = (val & 0x4) ?
  632. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  633. if (adapter->fw_type != fw_type)
  634. return 1;
  635. }
  636. }
  637. return 0;
  638. }
  639. static char *fw_name[] = {
  640. "nxromimg.bin", "nx3fwct.bin", "nx3fwmn.bin", "flash",
  641. };
  642. int
  643. netxen_load_firmware(struct netxen_adapter *adapter)
  644. {
  645. u64 *ptr64;
  646. u32 i, flashaddr, size;
  647. const struct firmware *fw = adapter->fw;
  648. struct pci_dev *pdev = adapter->pdev;
  649. dev_info(&pdev->dev, "loading firmware from %s\n",
  650. fw_name[adapter->fw_type]);
  651. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  652. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  653. if (fw) {
  654. __le64 data;
  655. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  656. ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START];
  657. flashaddr = NETXEN_BOOTLD_START;
  658. for (i = 0; i < size; i++) {
  659. data = cpu_to_le64(ptr64[i]);
  660. adapter->pci_mem_write(adapter, flashaddr, &data, 8);
  661. flashaddr += 8;
  662. }
  663. size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET];
  664. size = (__force u32)cpu_to_le32(size) / 8;
  665. ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START];
  666. flashaddr = NETXEN_IMAGE_START;
  667. for (i = 0; i < size; i++) {
  668. data = cpu_to_le64(ptr64[i]);
  669. if (adapter->pci_mem_write(adapter,
  670. flashaddr, &data, 8))
  671. return -EIO;
  672. flashaddr += 8;
  673. }
  674. } else {
  675. u32 data;
  676. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 4;
  677. flashaddr = NETXEN_BOOTLD_START;
  678. for (i = 0; i < size; i++) {
  679. if (netxen_rom_fast_read(adapter,
  680. flashaddr, (int *)&data) != 0)
  681. return -EIO;
  682. if (adapter->pci_mem_write(adapter,
  683. flashaddr, &data, 4))
  684. return -EIO;
  685. flashaddr += 4;
  686. }
  687. }
  688. msleep(1);
  689. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  690. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  691. else {
  692. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  693. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  694. }
  695. return 0;
  696. }
  697. static int
  698. netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname)
  699. {
  700. __le32 val;
  701. u32 ver, min_ver, bios;
  702. struct pci_dev *pdev = adapter->pdev;
  703. const struct firmware *fw = adapter->fw;
  704. if (fw->size < NX_FW_MIN_SIZE)
  705. return -EINVAL;
  706. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  707. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  708. return -EINVAL;
  709. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  710. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  711. min_ver = NETXEN_VERSION_CODE(4, 0, 216);
  712. else
  713. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  714. ver = NETXEN_DECODE_VERSION(val);
  715. if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
  716. dev_err(&pdev->dev,
  717. "%s: firmware version %d.%d.%d unsupported\n",
  718. fwname, _major(ver), _minor(ver), _build(ver));
  719. return -EINVAL;
  720. }
  721. val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  722. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  723. if ((__force u32)val != bios) {
  724. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  725. fwname);
  726. return -EINVAL;
  727. }
  728. /* check if flashed firmware is newer */
  729. if (netxen_rom_fast_read(adapter,
  730. NX_FW_VERSION_OFFSET, (int *)&val))
  731. return -EIO;
  732. val = NETXEN_DECODE_VERSION(val);
  733. if (val > ver) {
  734. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  735. fwname);
  736. return -EINVAL;
  737. }
  738. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  739. return 0;
  740. }
  741. static int
  742. netxen_p3_has_mn(struct netxen_adapter *adapter)
  743. {
  744. u32 capability, flashed_ver;
  745. capability = 0;
  746. netxen_rom_fast_read(adapter,
  747. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  748. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  749. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  750. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  751. if (capability & NX_PEG_TUNE_MN_PRESENT)
  752. return 1;
  753. }
  754. return 0;
  755. }
  756. void netxen_request_firmware(struct netxen_adapter *adapter)
  757. {
  758. u8 fw_type;
  759. struct pci_dev *pdev = adapter->pdev;
  760. int rc = 0;
  761. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  762. fw_type = NX_P2_MN_ROMIMAGE;
  763. goto request_fw;
  764. }
  765. fw_type = netxen_p3_has_mn(adapter) ?
  766. NX_P3_MN_ROMIMAGE : NX_P3_CT_ROMIMAGE;
  767. request_fw:
  768. rc = request_firmware(&adapter->fw, fw_name[fw_type], &pdev->dev);
  769. if (rc != 0) {
  770. if (fw_type == NX_P3_MN_ROMIMAGE) {
  771. msleep(1);
  772. fw_type = NX_P3_CT_ROMIMAGE;
  773. goto request_fw;
  774. }
  775. fw_type = NX_FLASH_ROMIMAGE;
  776. adapter->fw = NULL;
  777. goto done;
  778. }
  779. rc = netxen_validate_firmware(adapter, fw_name[fw_type]);
  780. if (rc != 0) {
  781. release_firmware(adapter->fw);
  782. if (fw_type == NX_P3_MN_ROMIMAGE) {
  783. msleep(1);
  784. fw_type = NX_P3_CT_ROMIMAGE;
  785. goto request_fw;
  786. }
  787. fw_type = NX_FLASH_ROMIMAGE;
  788. adapter->fw = NULL;
  789. goto done;
  790. }
  791. done:
  792. adapter->fw_type = fw_type;
  793. }
  794. void
  795. netxen_release_firmware(struct netxen_adapter *adapter)
  796. {
  797. if (adapter->fw)
  798. release_firmware(adapter->fw);
  799. }
  800. int netxen_init_dummy_dma(struct netxen_adapter *adapter)
  801. {
  802. u64 addr;
  803. u32 hi, lo;
  804. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  805. return 0;
  806. adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
  807. NETXEN_HOST_DUMMY_DMA_SIZE,
  808. &adapter->dummy_dma.phys_addr);
  809. if (adapter->dummy_dma.addr == NULL) {
  810. dev_err(&adapter->pdev->dev,
  811. "ERROR: Could not allocate dummy DMA memory\n");
  812. return -ENOMEM;
  813. }
  814. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  815. hi = (addr >> 32) & 0xffffffff;
  816. lo = addr & 0xffffffff;
  817. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  818. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  819. return 0;
  820. }
  821. /*
  822. * NetXen DMA watchdog control:
  823. *
  824. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  825. * Bit 1 : disable_request => 1 req disable dma watchdog
  826. * Bit 2 : enable_request => 1 req enable dma watchdog
  827. * Bit 3-31 : unused
  828. */
  829. void netxen_free_dummy_dma(struct netxen_adapter *adapter)
  830. {
  831. int i = 100;
  832. u32 ctrl;
  833. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  834. return;
  835. if (!adapter->dummy_dma.addr)
  836. return;
  837. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  838. if ((ctrl & 0x1) != 0) {
  839. NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
  840. while ((ctrl & 0x1) != 0) {
  841. msleep(50);
  842. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  843. if (--i == 0)
  844. break;
  845. };
  846. }
  847. if (i) {
  848. pci_free_consistent(adapter->pdev,
  849. NETXEN_HOST_DUMMY_DMA_SIZE,
  850. adapter->dummy_dma.addr,
  851. adapter->dummy_dma.phys_addr);
  852. adapter->dummy_dma.addr = NULL;
  853. } else
  854. dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
  855. }
  856. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  857. {
  858. u32 val = 0;
  859. int retries = 60;
  860. if (pegtune_val)
  861. return 0;
  862. do {
  863. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  864. switch (val) {
  865. case PHAN_INITIALIZE_COMPLETE:
  866. case PHAN_INITIALIZE_ACK:
  867. return 0;
  868. case PHAN_INITIALIZE_FAILED:
  869. goto out_err;
  870. default:
  871. break;
  872. }
  873. msleep(500);
  874. } while (--retries);
  875. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  876. out_err:
  877. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  878. return -EIO;
  879. }
  880. static int
  881. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  882. {
  883. u32 val = 0;
  884. int retries = 2000;
  885. do {
  886. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  887. if (val == PHAN_PEG_RCV_INITIALIZED)
  888. return 0;
  889. msleep(10);
  890. } while (--retries);
  891. if (!retries) {
  892. printk(KERN_ERR "Receive Peg initialization not "
  893. "complete, state: 0x%x.\n", val);
  894. return -EIO;
  895. }
  896. return 0;
  897. }
  898. int netxen_init_firmware(struct netxen_adapter *adapter)
  899. {
  900. int err;
  901. err = netxen_receive_peg_ready(adapter);
  902. if (err)
  903. return err;
  904. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  905. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  906. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  907. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  908. return err;
  909. }
  910. static void
  911. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  912. {
  913. u32 cable_OUI;
  914. u16 cable_len;
  915. u16 link_speed;
  916. u8 link_status, module, duplex, autoneg;
  917. struct net_device *netdev = adapter->netdev;
  918. adapter->has_link_events = 1;
  919. cable_OUI = msg->body[1] & 0xffffffff;
  920. cable_len = (msg->body[1] >> 32) & 0xffff;
  921. link_speed = (msg->body[1] >> 48) & 0xffff;
  922. link_status = msg->body[2] & 0xff;
  923. duplex = (msg->body[2] >> 16) & 0xff;
  924. autoneg = (msg->body[2] >> 24) & 0xff;
  925. module = (msg->body[2] >> 8) & 0xff;
  926. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  927. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  928. netdev->name, cable_OUI, cable_len);
  929. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  930. printk(KERN_INFO "%s: unsupported cable length %d\n",
  931. netdev->name, cable_len);
  932. }
  933. netxen_advert_link_change(adapter, link_status);
  934. /* update link parameters */
  935. if (duplex == LINKEVENT_FULL_DUPLEX)
  936. adapter->link_duplex = DUPLEX_FULL;
  937. else
  938. adapter->link_duplex = DUPLEX_HALF;
  939. adapter->module_type = module;
  940. adapter->link_autoneg = autoneg;
  941. adapter->link_speed = link_speed;
  942. }
  943. static void
  944. netxen_handle_fw_message(int desc_cnt, int index,
  945. struct nx_host_sds_ring *sds_ring)
  946. {
  947. nx_fw_msg_t msg;
  948. struct status_desc *desc;
  949. int i = 0, opcode;
  950. while (desc_cnt > 0 && i < 8) {
  951. desc = &sds_ring->desc_head[index];
  952. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  953. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  954. index = get_next_index(index, sds_ring->num_desc);
  955. desc_cnt--;
  956. }
  957. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  958. switch (opcode) {
  959. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  960. netxen_handle_linkevent(sds_ring->adapter, &msg);
  961. break;
  962. default:
  963. break;
  964. }
  965. }
  966. static int
  967. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  968. struct nx_host_rds_ring *rds_ring,
  969. struct netxen_rx_buffer *buffer)
  970. {
  971. struct sk_buff *skb;
  972. dma_addr_t dma;
  973. struct pci_dev *pdev = adapter->pdev;
  974. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  975. if (!buffer->skb)
  976. return 1;
  977. skb = buffer->skb;
  978. if (!adapter->ahw.cut_through)
  979. skb_reserve(skb, 2);
  980. dma = pci_map_single(pdev, skb->data,
  981. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  982. if (pci_dma_mapping_error(pdev, dma)) {
  983. dev_kfree_skb_any(skb);
  984. buffer->skb = NULL;
  985. return 1;
  986. }
  987. buffer->skb = skb;
  988. buffer->dma = dma;
  989. buffer->state = NETXEN_BUFFER_BUSY;
  990. return 0;
  991. }
  992. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  993. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  994. {
  995. struct netxen_rx_buffer *buffer;
  996. struct sk_buff *skb;
  997. buffer = &rds_ring->rx_buf_arr[index];
  998. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  999. PCI_DMA_FROMDEVICE);
  1000. skb = buffer->skb;
  1001. if (!skb)
  1002. goto no_skb;
  1003. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  1004. adapter->stats.csummed++;
  1005. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1006. } else
  1007. skb->ip_summed = CHECKSUM_NONE;
  1008. skb->dev = adapter->netdev;
  1009. buffer->skb = NULL;
  1010. no_skb:
  1011. buffer->state = NETXEN_BUFFER_FREE;
  1012. return skb;
  1013. }
  1014. static struct netxen_rx_buffer *
  1015. netxen_process_rcv(struct netxen_adapter *adapter,
  1016. struct nx_host_sds_ring *sds_ring,
  1017. int ring, u64 sts_data0)
  1018. {
  1019. struct net_device *netdev = adapter->netdev;
  1020. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1021. struct netxen_rx_buffer *buffer;
  1022. struct sk_buff *skb;
  1023. struct nx_host_rds_ring *rds_ring;
  1024. int index, length, cksum, pkt_offset;
  1025. if (unlikely(ring >= adapter->max_rds_rings))
  1026. return NULL;
  1027. rds_ring = &recv_ctx->rds_rings[ring];
  1028. index = netxen_get_sts_refhandle(sts_data0);
  1029. if (unlikely(index >= rds_ring->num_desc))
  1030. return NULL;
  1031. buffer = &rds_ring->rx_buf_arr[index];
  1032. length = netxen_get_sts_totallength(sts_data0);
  1033. cksum = netxen_get_sts_status(sts_data0);
  1034. pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
  1035. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1036. if (!skb)
  1037. return buffer;
  1038. if (length > rds_ring->skb_size)
  1039. skb_put(skb, rds_ring->skb_size);
  1040. else
  1041. skb_put(skb, length);
  1042. if (pkt_offset)
  1043. skb_pull(skb, pkt_offset);
  1044. skb->protocol = eth_type_trans(skb, netdev);
  1045. napi_gro_receive(&sds_ring->napi, skb);
  1046. adapter->stats.rx_pkts++;
  1047. adapter->stats.rxbytes += length;
  1048. return buffer;
  1049. }
  1050. #define TCP_HDR_SIZE 20
  1051. #define TCP_TS_OPTION_SIZE 12
  1052. #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
  1053. static struct netxen_rx_buffer *
  1054. netxen_process_lro(struct netxen_adapter *adapter,
  1055. struct nx_host_sds_ring *sds_ring,
  1056. int ring, u64 sts_data0, u64 sts_data1)
  1057. {
  1058. struct net_device *netdev = adapter->netdev;
  1059. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1060. struct netxen_rx_buffer *buffer;
  1061. struct sk_buff *skb;
  1062. struct nx_host_rds_ring *rds_ring;
  1063. struct iphdr *iph;
  1064. struct tcphdr *th;
  1065. bool push, timestamp;
  1066. int l2_hdr_offset, l4_hdr_offset;
  1067. int index;
  1068. u16 lro_length, length, data_offset;
  1069. u32 seq_number;
  1070. if (unlikely(ring > adapter->max_rds_rings))
  1071. return NULL;
  1072. rds_ring = &recv_ctx->rds_rings[ring];
  1073. index = netxen_get_lro_sts_refhandle(sts_data0);
  1074. if (unlikely(index > rds_ring->num_desc))
  1075. return NULL;
  1076. buffer = &rds_ring->rx_buf_arr[index];
  1077. timestamp = netxen_get_lro_sts_timestamp(sts_data0);
  1078. lro_length = netxen_get_lro_sts_length(sts_data0);
  1079. l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
  1080. l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
  1081. push = netxen_get_lro_sts_push_flag(sts_data0);
  1082. seq_number = netxen_get_lro_sts_seq_number(sts_data1);
  1083. skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1084. if (!skb)
  1085. return buffer;
  1086. if (timestamp)
  1087. data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
  1088. else
  1089. data_offset = l4_hdr_offset + TCP_HDR_SIZE;
  1090. skb_put(skb, lro_length + data_offset);
  1091. skb->truesize = (skb->len + sizeof(struct sk_buff) +
  1092. ((unsigned long)skb->data - (unsigned long)skb->head));
  1093. skb_pull(skb, l2_hdr_offset);
  1094. skb->protocol = eth_type_trans(skb, netdev);
  1095. iph = (struct iphdr *)skb->data;
  1096. th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
  1097. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1098. iph->tot_len = htons(length);
  1099. iph->check = 0;
  1100. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1101. th->psh = push;
  1102. th->seq = htonl(seq_number);
  1103. length = skb->len;
  1104. netif_receive_skb(skb);
  1105. adapter->stats.lro_pkts++;
  1106. adapter->stats.rxbytes += length;
  1107. return buffer;
  1108. }
  1109. #define netxen_merge_rx_buffers(list, head) \
  1110. do { list_splice_tail_init(list, head); } while (0);
  1111. int
  1112. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1113. {
  1114. struct netxen_adapter *adapter = sds_ring->adapter;
  1115. struct list_head *cur;
  1116. struct status_desc *desc;
  1117. struct netxen_rx_buffer *rxbuf;
  1118. u32 consumer = sds_ring->consumer;
  1119. int count = 0;
  1120. u64 sts_data0, sts_data1;
  1121. int opcode, ring = 0, desc_cnt;
  1122. while (count < max) {
  1123. desc = &sds_ring->desc_head[consumer];
  1124. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1125. if (!(sts_data0 & STATUS_OWNER_HOST))
  1126. break;
  1127. desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
  1128. opcode = netxen_get_sts_opcode(sts_data0);
  1129. switch (opcode) {
  1130. case NETXEN_NIC_RXPKT_DESC:
  1131. case NETXEN_OLD_RXPKT_DESC:
  1132. case NETXEN_NIC_SYN_OFFLOAD:
  1133. ring = netxen_get_sts_type(sts_data0);
  1134. rxbuf = netxen_process_rcv(adapter, sds_ring,
  1135. ring, sts_data0);
  1136. break;
  1137. case NETXEN_NIC_LRO_DESC:
  1138. ring = netxen_get_lro_sts_type(sts_data0);
  1139. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1140. rxbuf = netxen_process_lro(adapter, sds_ring,
  1141. ring, sts_data0, sts_data1);
  1142. break;
  1143. case NETXEN_NIC_RESPONSE_DESC:
  1144. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1145. default:
  1146. goto skip;
  1147. }
  1148. WARN_ON(desc_cnt > 1);
  1149. if (rxbuf)
  1150. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1151. skip:
  1152. for (; desc_cnt > 0; desc_cnt--) {
  1153. desc = &sds_ring->desc_head[consumer];
  1154. desc->status_desc_data[0] =
  1155. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1156. consumer = get_next_index(consumer, sds_ring->num_desc);
  1157. }
  1158. count++;
  1159. }
  1160. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1161. struct nx_host_rds_ring *rds_ring =
  1162. &adapter->recv_ctx.rds_rings[ring];
  1163. if (!list_empty(&sds_ring->free_list[ring])) {
  1164. list_for_each(cur, &sds_ring->free_list[ring]) {
  1165. rxbuf = list_entry(cur,
  1166. struct netxen_rx_buffer, list);
  1167. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1168. }
  1169. spin_lock(&rds_ring->lock);
  1170. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1171. &rds_ring->free_list);
  1172. spin_unlock(&rds_ring->lock);
  1173. }
  1174. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1175. }
  1176. if (count) {
  1177. sds_ring->consumer = consumer;
  1178. NXWR32(adapter, sds_ring->crb_sts_consumer, consumer);
  1179. }
  1180. return count;
  1181. }
  1182. /* Process Command status ring */
  1183. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1184. {
  1185. u32 sw_consumer, hw_consumer;
  1186. int count = 0, i;
  1187. struct netxen_cmd_buffer *buffer;
  1188. struct pci_dev *pdev = adapter->pdev;
  1189. struct net_device *netdev = adapter->netdev;
  1190. struct netxen_skb_frag *frag;
  1191. int done = 0;
  1192. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1193. if (!spin_trylock(&adapter->tx_clean_lock))
  1194. return 1;
  1195. sw_consumer = tx_ring->sw_consumer;
  1196. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1197. while (sw_consumer != hw_consumer) {
  1198. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1199. if (buffer->skb) {
  1200. frag = &buffer->frag_array[0];
  1201. pci_unmap_single(pdev, frag->dma, frag->length,
  1202. PCI_DMA_TODEVICE);
  1203. frag->dma = 0ULL;
  1204. for (i = 1; i < buffer->frag_count; i++) {
  1205. frag++; /* Get the next frag */
  1206. pci_unmap_page(pdev, frag->dma, frag->length,
  1207. PCI_DMA_TODEVICE);
  1208. frag->dma = 0ULL;
  1209. }
  1210. adapter->stats.xmitfinished++;
  1211. dev_kfree_skb_any(buffer->skb);
  1212. buffer->skb = NULL;
  1213. }
  1214. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1215. if (++count >= MAX_STATUS_HANDLE)
  1216. break;
  1217. }
  1218. if (count && netif_running(netdev)) {
  1219. tx_ring->sw_consumer = sw_consumer;
  1220. smp_mb();
  1221. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
  1222. __netif_tx_lock(tx_ring->txq, smp_processor_id());
  1223. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
  1224. netif_wake_queue(netdev);
  1225. __netif_tx_unlock(tx_ring->txq);
  1226. }
  1227. }
  1228. /*
  1229. * If everything is freed up to consumer then check if the ring is full
  1230. * If the ring is full then check if more needs to be freed and
  1231. * schedule the call back again.
  1232. *
  1233. * This happens when there are 2 CPUs. One could be freeing and the
  1234. * other filling it. If the ring is full when we get out of here and
  1235. * the card has already interrupted the host then the host can miss the
  1236. * interrupt.
  1237. *
  1238. * There is still a possible race condition and the host could miss an
  1239. * interrupt. The card has to take care of this.
  1240. */
  1241. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1242. done = (sw_consumer == hw_consumer);
  1243. spin_unlock(&adapter->tx_clean_lock);
  1244. return (done);
  1245. }
  1246. void
  1247. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1248. struct nx_host_rds_ring *rds_ring)
  1249. {
  1250. struct rcv_desc *pdesc;
  1251. struct netxen_rx_buffer *buffer;
  1252. int producer, count = 0;
  1253. netxen_ctx_msg msg = 0;
  1254. struct list_head *head;
  1255. producer = rds_ring->producer;
  1256. spin_lock(&rds_ring->lock);
  1257. head = &rds_ring->free_list;
  1258. while (!list_empty(head)) {
  1259. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1260. if (!buffer->skb) {
  1261. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1262. break;
  1263. }
  1264. count++;
  1265. list_del(&buffer->list);
  1266. /* make a rcv descriptor */
  1267. pdesc = &rds_ring->desc_head[producer];
  1268. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1269. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1270. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1271. producer = get_next_index(producer, rds_ring->num_desc);
  1272. }
  1273. spin_unlock(&rds_ring->lock);
  1274. if (count) {
  1275. rds_ring->producer = producer;
  1276. NXWR32(adapter, rds_ring->crb_rcv_producer,
  1277. (producer-1) & (rds_ring->num_desc-1));
  1278. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  1279. /*
  1280. * Write a doorbell msg to tell phanmon of change in
  1281. * receive ring producer
  1282. * Only for firmware version < 4.0.0
  1283. */
  1284. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1285. netxen_set_msg_privid(msg);
  1286. netxen_set_msg_count(msg,
  1287. ((producer - 1) &
  1288. (rds_ring->num_desc - 1)));
  1289. netxen_set_msg_ctxid(msg, adapter->portnum);
  1290. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1291. writel(msg,
  1292. DB_NORMALIZE(adapter,
  1293. NETXEN_RCV_PRODUCER_OFFSET));
  1294. }
  1295. }
  1296. }
  1297. static void
  1298. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1299. struct nx_host_rds_ring *rds_ring)
  1300. {
  1301. struct rcv_desc *pdesc;
  1302. struct netxen_rx_buffer *buffer;
  1303. int producer, count = 0;
  1304. struct list_head *head;
  1305. producer = rds_ring->producer;
  1306. if (!spin_trylock(&rds_ring->lock))
  1307. return;
  1308. head = &rds_ring->free_list;
  1309. while (!list_empty(head)) {
  1310. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1311. if (!buffer->skb) {
  1312. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1313. break;
  1314. }
  1315. count++;
  1316. list_del(&buffer->list);
  1317. /* make a rcv descriptor */
  1318. pdesc = &rds_ring->desc_head[producer];
  1319. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1320. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1321. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1322. producer = get_next_index(producer, rds_ring->num_desc);
  1323. }
  1324. if (count) {
  1325. rds_ring->producer = producer;
  1326. NXWR32(adapter, rds_ring->crb_rcv_producer,
  1327. (producer - 1) & (rds_ring->num_desc - 1));
  1328. }
  1329. spin_unlock(&rds_ring->lock);
  1330. }
  1331. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1332. {
  1333. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1334. return;
  1335. }