8250_pci.c 53 KB

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  1. /*
  2. * linux/drivers/char/8250_pci.c
  3. *
  4. * Probe module for 8250/16550-type PCI serial ports.
  5. *
  6. * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  7. *
  8. * Copyright (C) 2001 Russell King, All Rights Reserved.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License.
  13. *
  14. * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
  15. */
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/pci.h>
  19. #include <linux/sched.h>
  20. #include <linux/string.h>
  21. #include <linux/kernel.h>
  22. #include <linux/slab.h>
  23. #include <linux/delay.h>
  24. #include <linux/tty.h>
  25. #include <linux/serial_core.h>
  26. #include <linux/8250_pci.h>
  27. #include <linux/bitops.h>
  28. #include <asm/byteorder.h>
  29. #include <asm/io.h>
  30. #include "8250.h"
  31. #undef SERIAL_DEBUG_PCI
  32. /*
  33. * init function returns:
  34. * > 0 - number of ports
  35. * = 0 - use board->num_ports
  36. * < 0 - error
  37. */
  38. struct pci_serial_quirk {
  39. u32 vendor;
  40. u32 device;
  41. u32 subvendor;
  42. u32 subdevice;
  43. int (*init)(struct pci_dev *dev);
  44. int (*setup)(struct serial_private *, struct pciserial_board *,
  45. struct uart_port *, int);
  46. void (*exit)(struct pci_dev *dev);
  47. };
  48. #define PCI_NUM_BAR_RESOURCES 6
  49. struct serial_private {
  50. struct pci_dev *dev;
  51. unsigned int nr;
  52. void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
  53. struct pci_serial_quirk *quirk;
  54. int line[0];
  55. };
  56. static void moan_device(const char *str, struct pci_dev *dev)
  57. {
  58. printk(KERN_WARNING "%s: %s\n"
  59. KERN_WARNING "Please send the output of lspci -vv, this\n"
  60. KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  61. KERN_WARNING "manufacturer and name of serial board or\n"
  62. KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
  63. pci_name(dev), str, dev->vendor, dev->device,
  64. dev->subsystem_vendor, dev->subsystem_device);
  65. }
  66. static int
  67. setup_port(struct serial_private *priv, struct uart_port *port,
  68. int bar, int offset, int regshift)
  69. {
  70. struct pci_dev *dev = priv->dev;
  71. unsigned long base, len;
  72. if (bar >= PCI_NUM_BAR_RESOURCES)
  73. return -EINVAL;
  74. base = pci_resource_start(dev, bar);
  75. if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  76. len = pci_resource_len(dev, bar);
  77. if (!priv->remapped_bar[bar])
  78. priv->remapped_bar[bar] = ioremap(base, len);
  79. if (!priv->remapped_bar[bar])
  80. return -ENOMEM;
  81. port->iotype = UPIO_MEM;
  82. port->iobase = 0;
  83. port->mapbase = base + offset;
  84. port->membase = priv->remapped_bar[bar] + offset;
  85. port->regshift = regshift;
  86. } else {
  87. port->iotype = UPIO_PORT;
  88. port->iobase = base + offset;
  89. port->mapbase = 0;
  90. port->membase = NULL;
  91. port->regshift = 0;
  92. }
  93. return 0;
  94. }
  95. /*
  96. * AFAVLAB uses a different mixture of BARs and offsets
  97. * Not that ugly ;) -- HW
  98. */
  99. static int
  100. afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
  101. struct uart_port *port, int idx)
  102. {
  103. unsigned int bar, offset = board->first_offset;
  104. bar = FL_GET_BASE(board->flags);
  105. if (idx < 4)
  106. bar += idx;
  107. else {
  108. bar = 4;
  109. offset += (idx - 4) * board->uart_offset;
  110. }
  111. return setup_port(priv, port, bar, offset, board->reg_shift);
  112. }
  113. /*
  114. * HP's Remote Management Console. The Diva chip came in several
  115. * different versions. N-class, L2000 and A500 have two Diva chips, each
  116. * with 3 UARTs (the third UART on the second chip is unused). Superdome
  117. * and Keystone have one Diva chip with 3 UARTs. Some later machines have
  118. * one Diva chip, but it has been expanded to 5 UARTs.
  119. */
  120. static int __devinit pci_hp_diva_init(struct pci_dev *dev)
  121. {
  122. int rc = 0;
  123. switch (dev->subsystem_device) {
  124. case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
  125. case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
  126. case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
  127. case PCI_DEVICE_ID_HP_DIVA_EVEREST:
  128. rc = 3;
  129. break;
  130. case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
  131. rc = 2;
  132. break;
  133. case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
  134. rc = 4;
  135. break;
  136. case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
  137. case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
  138. rc = 1;
  139. break;
  140. }
  141. return rc;
  142. }
  143. /*
  144. * HP's Diva chip puts the 4th/5th serial port further out, and
  145. * some serial ports are supposed to be hidden on certain models.
  146. */
  147. static int
  148. pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
  149. struct uart_port *port, int idx)
  150. {
  151. unsigned int offset = board->first_offset;
  152. unsigned int bar = FL_GET_BASE(board->flags);
  153. switch (priv->dev->subsystem_device) {
  154. case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
  155. if (idx == 3)
  156. idx++;
  157. break;
  158. case PCI_DEVICE_ID_HP_DIVA_EVEREST:
  159. if (idx > 0)
  160. idx++;
  161. if (idx > 2)
  162. idx++;
  163. break;
  164. }
  165. if (idx > 2)
  166. offset = 0x18;
  167. offset += idx * board->uart_offset;
  168. return setup_port(priv, port, bar, offset, board->reg_shift);
  169. }
  170. /*
  171. * Added for EKF Intel i960 serial boards
  172. */
  173. static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
  174. {
  175. unsigned long oldval;
  176. if (!(dev->subsystem_device & 0x1000))
  177. return -ENODEV;
  178. /* is firmware started? */
  179. pci_read_config_dword(dev, 0x44, (void*) &oldval);
  180. if (oldval == 0x00001000L) { /* RESET value */
  181. printk(KERN_DEBUG "Local i960 firmware missing");
  182. return -ENODEV;
  183. }
  184. return 0;
  185. }
  186. /*
  187. * Some PCI serial cards using the PLX 9050 PCI interface chip require
  188. * that the card interrupt be explicitly enabled or disabled. This
  189. * seems to be mainly needed on card using the PLX which also use I/O
  190. * mapped memory.
  191. */
  192. static int __devinit pci_plx9050_init(struct pci_dev *dev)
  193. {
  194. u8 irq_config;
  195. void __iomem *p;
  196. if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
  197. moan_device("no memory in bar 0", dev);
  198. return 0;
  199. }
  200. irq_config = 0x41;
  201. if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
  202. dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
  203. irq_config = 0x43;
  204. }
  205. if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
  206. (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
  207. /*
  208. * As the megawolf cards have the int pins active
  209. * high, and have 2 UART chips, both ints must be
  210. * enabled on the 9050. Also, the UARTS are set in
  211. * 16450 mode by default, so we have to enable the
  212. * 16C950 'enhanced' mode so that we can use the
  213. * deep FIFOs
  214. */
  215. irq_config = 0x5b;
  216. }
  217. /*
  218. * enable/disable interrupts
  219. */
  220. p = ioremap(pci_resource_start(dev, 0), 0x80);
  221. if (p == NULL)
  222. return -ENOMEM;
  223. writel(irq_config, p + 0x4c);
  224. /*
  225. * Read the register back to ensure that it took effect.
  226. */
  227. readl(p + 0x4c);
  228. iounmap(p);
  229. return 0;
  230. }
  231. static void __devexit pci_plx9050_exit(struct pci_dev *dev)
  232. {
  233. u8 __iomem *p;
  234. if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
  235. return;
  236. /*
  237. * disable interrupts
  238. */
  239. p = ioremap(pci_resource_start(dev, 0), 0x80);
  240. if (p != NULL) {
  241. writel(0, p + 0x4c);
  242. /*
  243. * Read the register back to ensure that it took effect.
  244. */
  245. readl(p + 0x4c);
  246. iounmap(p);
  247. }
  248. }
  249. /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
  250. static int
  251. sbs_setup(struct serial_private *priv, struct pciserial_board *board,
  252. struct uart_port *port, int idx)
  253. {
  254. unsigned int bar, offset = board->first_offset;
  255. bar = 0;
  256. if (idx < 4) {
  257. /* first four channels map to 0, 0x100, 0x200, 0x300 */
  258. offset += idx * board->uart_offset;
  259. } else if (idx < 8) {
  260. /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
  261. offset += idx * board->uart_offset + 0xC00;
  262. } else /* we have only 8 ports on PMC-OCTALPRO */
  263. return 1;
  264. return setup_port(priv, port, bar, offset, board->reg_shift);
  265. }
  266. /*
  267. * This does initialization for PMC OCTALPRO cards:
  268. * maps the device memory, resets the UARTs (needed, bc
  269. * if the module is removed and inserted again, the card
  270. * is in the sleep mode) and enables global interrupt.
  271. */
  272. /* global control register offset for SBS PMC-OctalPro */
  273. #define OCT_REG_CR_OFF 0x500
  274. static int __devinit sbs_init(struct pci_dev *dev)
  275. {
  276. u8 __iomem *p;
  277. p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
  278. if (p == NULL)
  279. return -ENOMEM;
  280. /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
  281. writeb(0x10,p + OCT_REG_CR_OFF);
  282. udelay(50);
  283. writeb(0x0,p + OCT_REG_CR_OFF);
  284. /* Set bit-2 (INTENABLE) of Control Register */
  285. writeb(0x4, p + OCT_REG_CR_OFF);
  286. iounmap(p);
  287. return 0;
  288. }
  289. /*
  290. * Disables the global interrupt of PMC-OctalPro
  291. */
  292. static void __devexit sbs_exit(struct pci_dev *dev)
  293. {
  294. u8 __iomem *p;
  295. p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
  296. if (p != NULL) {
  297. writeb(0, p + OCT_REG_CR_OFF);
  298. }
  299. iounmap(p);
  300. }
  301. /*
  302. * SIIG serial cards have an PCI interface chip which also controls
  303. * the UART clocking frequency. Each UART can be clocked independently
  304. * (except cards equiped with 4 UARTs) and initial clocking settings
  305. * are stored in the EEPROM chip. It can cause problems because this
  306. * version of serial driver doesn't support differently clocked UART's
  307. * on single PCI card. To prevent this, initialization functions set
  308. * high frequency clocking for all UART's on given card. It is safe (I
  309. * hope) because it doesn't touch EEPROM settings to prevent conflicts
  310. * with other OSes (like M$ DOS).
  311. *
  312. * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
  313. *
  314. * There is two family of SIIG serial cards with different PCI
  315. * interface chip and different configuration methods:
  316. * - 10x cards have control registers in IO and/or memory space;
  317. * - 20x cards have control registers in standard PCI configuration space.
  318. *
  319. * Note: all 10x cards have PCI device ids 0x10..
  320. * all 20x cards have PCI device ids 0x20..
  321. *
  322. * There are also Quartet Serial cards which use Oxford Semiconductor
  323. * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
  324. *
  325. * Note: some SIIG cards are probed by the parport_serial object.
  326. */
  327. #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
  328. #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
  329. static int pci_siig10x_init(struct pci_dev *dev)
  330. {
  331. u16 data;
  332. void __iomem *p;
  333. switch (dev->device & 0xfff8) {
  334. case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
  335. data = 0xffdf;
  336. break;
  337. case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
  338. data = 0xf7ff;
  339. break;
  340. default: /* 1S1P, 4S */
  341. data = 0xfffb;
  342. break;
  343. }
  344. p = ioremap(pci_resource_start(dev, 0), 0x80);
  345. if (p == NULL)
  346. return -ENOMEM;
  347. writew(readw(p + 0x28) & data, p + 0x28);
  348. readw(p + 0x28);
  349. iounmap(p);
  350. return 0;
  351. }
  352. #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
  353. #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
  354. static int pci_siig20x_init(struct pci_dev *dev)
  355. {
  356. u8 data;
  357. /* Change clock frequency for the first UART. */
  358. pci_read_config_byte(dev, 0x6f, &data);
  359. pci_write_config_byte(dev, 0x6f, data & 0xef);
  360. /* If this card has 2 UART, we have to do the same with second UART. */
  361. if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
  362. ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
  363. pci_read_config_byte(dev, 0x73, &data);
  364. pci_write_config_byte(dev, 0x73, data & 0xef);
  365. }
  366. return 0;
  367. }
  368. static int pci_siig_init(struct pci_dev *dev)
  369. {
  370. unsigned int type = dev->device & 0xff00;
  371. if (type == 0x1000)
  372. return pci_siig10x_init(dev);
  373. else if (type == 0x2000)
  374. return pci_siig20x_init(dev);
  375. moan_device("Unknown SIIG card", dev);
  376. return -ENODEV;
  377. }
  378. /*
  379. * Timedia has an explosion of boards, and to avoid the PCI table from
  380. * growing *huge*, we use this function to collapse some 70 entries
  381. * in the PCI table into one, for sanity's and compactness's sake.
  382. */
  383. static unsigned short timedia_single_port[] = {
  384. 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
  385. };
  386. static unsigned short timedia_dual_port[] = {
  387. 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
  388. 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
  389. 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
  390. 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
  391. 0xD079, 0
  392. };
  393. static unsigned short timedia_quad_port[] = {
  394. 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
  395. 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
  396. 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
  397. 0xB157, 0
  398. };
  399. static unsigned short timedia_eight_port[] = {
  400. 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
  401. 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
  402. };
  403. static struct timedia_struct {
  404. int num;
  405. unsigned short *ids;
  406. } timedia_data[] = {
  407. { 1, timedia_single_port },
  408. { 2, timedia_dual_port },
  409. { 4, timedia_quad_port },
  410. { 8, timedia_eight_port },
  411. { 0, NULL }
  412. };
  413. static int __devinit pci_timedia_init(struct pci_dev *dev)
  414. {
  415. unsigned short *ids;
  416. int i, j;
  417. for (i = 0; timedia_data[i].num; i++) {
  418. ids = timedia_data[i].ids;
  419. for (j = 0; ids[j]; j++)
  420. if (dev->subsystem_device == ids[j])
  421. return timedia_data[i].num;
  422. }
  423. return 0;
  424. }
  425. /*
  426. * Timedia/SUNIX uses a mixture of BARs and offsets
  427. * Ugh, this is ugly as all hell --- TYT
  428. */
  429. static int
  430. pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
  431. struct uart_port *port, int idx)
  432. {
  433. unsigned int bar = 0, offset = board->first_offset;
  434. switch (idx) {
  435. case 0:
  436. bar = 0;
  437. break;
  438. case 1:
  439. offset = board->uart_offset;
  440. bar = 0;
  441. break;
  442. case 2:
  443. bar = 1;
  444. break;
  445. case 3:
  446. offset = board->uart_offset;
  447. bar = 1;
  448. case 4: /* BAR 2 */
  449. case 5: /* BAR 3 */
  450. case 6: /* BAR 4 */
  451. case 7: /* BAR 5 */
  452. bar = idx - 2;
  453. }
  454. return setup_port(priv, port, bar, offset, board->reg_shift);
  455. }
  456. /*
  457. * Some Titan cards are also a little weird
  458. */
  459. static int
  460. titan_400l_800l_setup(struct serial_private *priv,
  461. struct pciserial_board *board,
  462. struct uart_port *port, int idx)
  463. {
  464. unsigned int bar, offset = board->first_offset;
  465. switch (idx) {
  466. case 0:
  467. bar = 1;
  468. break;
  469. case 1:
  470. bar = 2;
  471. break;
  472. default:
  473. bar = 4;
  474. offset = (idx - 2) * board->uart_offset;
  475. }
  476. return setup_port(priv, port, bar, offset, board->reg_shift);
  477. }
  478. static int __devinit pci_xircom_init(struct pci_dev *dev)
  479. {
  480. msleep(100);
  481. return 0;
  482. }
  483. static int __devinit pci_netmos_init(struct pci_dev *dev)
  484. {
  485. /* subdevice 0x00PS means <P> parallel, <S> serial */
  486. unsigned int num_serial = dev->subsystem_device & 0xf;
  487. if (num_serial == 0)
  488. return -ENODEV;
  489. return num_serial;
  490. }
  491. static int
  492. pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
  493. struct uart_port *port, int idx)
  494. {
  495. unsigned int bar, offset = board->first_offset, maxnr;
  496. bar = FL_GET_BASE(board->flags);
  497. if (board->flags & FL_BASE_BARS)
  498. bar += idx;
  499. else
  500. offset += idx * board->uart_offset;
  501. maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) /
  502. (8 << board->reg_shift);
  503. if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
  504. return 1;
  505. return setup_port(priv, port, bar, offset, board->reg_shift);
  506. }
  507. /* This should be in linux/pci_ids.h */
  508. #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
  509. #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
  510. #define PCI_DEVICE_ID_OCTPRO 0x0001
  511. #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
  512. #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
  513. #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
  514. #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
  515. /*
  516. * Master list of serial port init/setup/exit quirks.
  517. * This does not describe the general nature of the port.
  518. * (ie, baud base, number and location of ports, etc)
  519. *
  520. * This list is ordered alphabetically by vendor then device.
  521. * Specific entries must come before more generic entries.
  522. */
  523. static struct pci_serial_quirk pci_serial_quirks[] = {
  524. /*
  525. * AFAVLAB cards.
  526. * It is not clear whether this applies to all products.
  527. */
  528. {
  529. .vendor = PCI_VENDOR_ID_AFAVLAB,
  530. .device = PCI_ANY_ID,
  531. .subvendor = PCI_ANY_ID,
  532. .subdevice = PCI_ANY_ID,
  533. .setup = afavlab_setup,
  534. },
  535. /*
  536. * HP Diva
  537. */
  538. {
  539. .vendor = PCI_VENDOR_ID_HP,
  540. .device = PCI_DEVICE_ID_HP_DIVA,
  541. .subvendor = PCI_ANY_ID,
  542. .subdevice = PCI_ANY_ID,
  543. .init = pci_hp_diva_init,
  544. .setup = pci_hp_diva_setup,
  545. },
  546. /*
  547. * Intel
  548. */
  549. {
  550. .vendor = PCI_VENDOR_ID_INTEL,
  551. .device = PCI_DEVICE_ID_INTEL_80960_RP,
  552. .subvendor = 0xe4bf,
  553. .subdevice = PCI_ANY_ID,
  554. .init = pci_inteli960ni_init,
  555. .setup = pci_default_setup,
  556. },
  557. /*
  558. * Panacom
  559. */
  560. {
  561. .vendor = PCI_VENDOR_ID_PANACOM,
  562. .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
  563. .subvendor = PCI_ANY_ID,
  564. .subdevice = PCI_ANY_ID,
  565. .init = pci_plx9050_init,
  566. .setup = pci_default_setup,
  567. .exit = __devexit_p(pci_plx9050_exit),
  568. },
  569. {
  570. .vendor = PCI_VENDOR_ID_PANACOM,
  571. .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
  572. .subvendor = PCI_ANY_ID,
  573. .subdevice = PCI_ANY_ID,
  574. .init = pci_plx9050_init,
  575. .setup = pci_default_setup,
  576. .exit = __devexit_p(pci_plx9050_exit),
  577. },
  578. /*
  579. * PLX
  580. */
  581. {
  582. .vendor = PCI_VENDOR_ID_PLX,
  583. .device = PCI_DEVICE_ID_PLX_9050,
  584. .subvendor = PCI_SUBVENDOR_ID_EXSYS,
  585. .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
  586. .init = pci_plx9050_init,
  587. .setup = pci_default_setup,
  588. .exit = __devexit_p(pci_plx9050_exit),
  589. },
  590. {
  591. .vendor = PCI_VENDOR_ID_PLX,
  592. .device = PCI_DEVICE_ID_PLX_9050,
  593. .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
  594. .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
  595. .init = pci_plx9050_init,
  596. .setup = pci_default_setup,
  597. .exit = __devexit_p(pci_plx9050_exit),
  598. },
  599. {
  600. .vendor = PCI_VENDOR_ID_PLX,
  601. .device = PCI_DEVICE_ID_PLX_ROMULUS,
  602. .subvendor = PCI_VENDOR_ID_PLX,
  603. .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
  604. .init = pci_plx9050_init,
  605. .setup = pci_default_setup,
  606. .exit = __devexit_p(pci_plx9050_exit),
  607. },
  608. /*
  609. * SBS Technologies, Inc., PMC-OCTALPRO 232
  610. */
  611. {
  612. .vendor = PCI_VENDOR_ID_SBSMODULARIO,
  613. .device = PCI_DEVICE_ID_OCTPRO,
  614. .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
  615. .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
  616. .init = sbs_init,
  617. .setup = sbs_setup,
  618. .exit = __devexit_p(sbs_exit),
  619. },
  620. /*
  621. * SBS Technologies, Inc., PMC-OCTALPRO 422
  622. */
  623. {
  624. .vendor = PCI_VENDOR_ID_SBSMODULARIO,
  625. .device = PCI_DEVICE_ID_OCTPRO,
  626. .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
  627. .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
  628. .init = sbs_init,
  629. .setup = sbs_setup,
  630. .exit = __devexit_p(sbs_exit),
  631. },
  632. /*
  633. * SBS Technologies, Inc., P-Octal 232
  634. */
  635. {
  636. .vendor = PCI_VENDOR_ID_SBSMODULARIO,
  637. .device = PCI_DEVICE_ID_OCTPRO,
  638. .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
  639. .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
  640. .init = sbs_init,
  641. .setup = sbs_setup,
  642. .exit = __devexit_p(sbs_exit),
  643. },
  644. /*
  645. * SBS Technologies, Inc., P-Octal 422
  646. */
  647. {
  648. .vendor = PCI_VENDOR_ID_SBSMODULARIO,
  649. .device = PCI_DEVICE_ID_OCTPRO,
  650. .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
  651. .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
  652. .init = sbs_init,
  653. .setup = sbs_setup,
  654. .exit = __devexit_p(sbs_exit),
  655. },
  656. /*
  657. * SIIG cards.
  658. */
  659. {
  660. .vendor = PCI_VENDOR_ID_SIIG,
  661. .device = PCI_ANY_ID,
  662. .subvendor = PCI_ANY_ID,
  663. .subdevice = PCI_ANY_ID,
  664. .init = pci_siig_init,
  665. .setup = pci_default_setup,
  666. },
  667. /*
  668. * Titan cards
  669. */
  670. {
  671. .vendor = PCI_VENDOR_ID_TITAN,
  672. .device = PCI_DEVICE_ID_TITAN_400L,
  673. .subvendor = PCI_ANY_ID,
  674. .subdevice = PCI_ANY_ID,
  675. .setup = titan_400l_800l_setup,
  676. },
  677. {
  678. .vendor = PCI_VENDOR_ID_TITAN,
  679. .device = PCI_DEVICE_ID_TITAN_800L,
  680. .subvendor = PCI_ANY_ID,
  681. .subdevice = PCI_ANY_ID,
  682. .setup = titan_400l_800l_setup,
  683. },
  684. /*
  685. * Timedia cards
  686. */
  687. {
  688. .vendor = PCI_VENDOR_ID_TIMEDIA,
  689. .device = PCI_DEVICE_ID_TIMEDIA_1889,
  690. .subvendor = PCI_VENDOR_ID_TIMEDIA,
  691. .subdevice = PCI_ANY_ID,
  692. .init = pci_timedia_init,
  693. .setup = pci_timedia_setup,
  694. },
  695. {
  696. .vendor = PCI_VENDOR_ID_TIMEDIA,
  697. .device = PCI_ANY_ID,
  698. .subvendor = PCI_ANY_ID,
  699. .subdevice = PCI_ANY_ID,
  700. .setup = pci_timedia_setup,
  701. },
  702. /*
  703. * Xircom cards
  704. */
  705. {
  706. .vendor = PCI_VENDOR_ID_XIRCOM,
  707. .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
  708. .subvendor = PCI_ANY_ID,
  709. .subdevice = PCI_ANY_ID,
  710. .init = pci_xircom_init,
  711. .setup = pci_default_setup,
  712. },
  713. /*
  714. * Netmos cards
  715. */
  716. {
  717. .vendor = PCI_VENDOR_ID_NETMOS,
  718. .device = PCI_ANY_ID,
  719. .subvendor = PCI_ANY_ID,
  720. .subdevice = PCI_ANY_ID,
  721. .init = pci_netmos_init,
  722. .setup = pci_default_setup,
  723. },
  724. /*
  725. * Default "match everything" terminator entry
  726. */
  727. {
  728. .vendor = PCI_ANY_ID,
  729. .device = PCI_ANY_ID,
  730. .subvendor = PCI_ANY_ID,
  731. .subdevice = PCI_ANY_ID,
  732. .setup = pci_default_setup,
  733. }
  734. };
  735. static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
  736. {
  737. return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
  738. }
  739. static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
  740. {
  741. struct pci_serial_quirk *quirk;
  742. for (quirk = pci_serial_quirks; ; quirk++)
  743. if (quirk_id_matches(quirk->vendor, dev->vendor) &&
  744. quirk_id_matches(quirk->device, dev->device) &&
  745. quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
  746. quirk_id_matches(quirk->subdevice, dev->subsystem_device))
  747. break;
  748. return quirk;
  749. }
  750. static _INLINE_ int
  751. get_pci_irq(struct pci_dev *dev, struct pciserial_board *board)
  752. {
  753. if (board->flags & FL_NOIRQ)
  754. return 0;
  755. else
  756. return dev->irq;
  757. }
  758. /*
  759. * This is the configuration table for all of the PCI serial boards
  760. * which we support. It is directly indexed by the pci_board_num_t enum
  761. * value, which is encoded in the pci_device_id PCI probe table's
  762. * driver_data member.
  763. *
  764. * The makeup of these names are:
  765. * pbn_bn{_bt}_n_baud
  766. *
  767. * bn = PCI BAR number
  768. * bt = Index using PCI BARs
  769. * n = number of serial ports
  770. * baud = baud rate
  771. *
  772. * This table is sorted by (in order): baud, bt, bn, n.
  773. *
  774. * Please note: in theory if n = 1, _bt infix should make no difference.
  775. * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
  776. */
  777. enum pci_board_num_t {
  778. pbn_default = 0,
  779. pbn_b0_1_115200,
  780. pbn_b0_2_115200,
  781. pbn_b0_4_115200,
  782. pbn_b0_5_115200,
  783. pbn_b0_1_921600,
  784. pbn_b0_2_921600,
  785. pbn_b0_4_921600,
  786. pbn_b0_2_1130000,
  787. pbn_b0_4_1152000,
  788. pbn_b0_bt_1_115200,
  789. pbn_b0_bt_2_115200,
  790. pbn_b0_bt_8_115200,
  791. pbn_b0_bt_1_460800,
  792. pbn_b0_bt_2_460800,
  793. pbn_b0_bt_4_460800,
  794. pbn_b0_bt_1_921600,
  795. pbn_b0_bt_2_921600,
  796. pbn_b0_bt_4_921600,
  797. pbn_b0_bt_8_921600,
  798. pbn_b1_1_115200,
  799. pbn_b1_2_115200,
  800. pbn_b1_4_115200,
  801. pbn_b1_8_115200,
  802. pbn_b1_1_921600,
  803. pbn_b1_2_921600,
  804. pbn_b1_4_921600,
  805. pbn_b1_8_921600,
  806. pbn_b1_bt_2_921600,
  807. pbn_b1_1_1382400,
  808. pbn_b1_2_1382400,
  809. pbn_b1_4_1382400,
  810. pbn_b1_8_1382400,
  811. pbn_b2_1_115200,
  812. pbn_b2_8_115200,
  813. pbn_b2_1_460800,
  814. pbn_b2_4_460800,
  815. pbn_b2_8_460800,
  816. pbn_b2_16_460800,
  817. pbn_b2_1_921600,
  818. pbn_b2_4_921600,
  819. pbn_b2_8_921600,
  820. pbn_b2_bt_1_115200,
  821. pbn_b2_bt_2_115200,
  822. pbn_b2_bt_4_115200,
  823. pbn_b2_bt_2_921600,
  824. pbn_b2_bt_4_921600,
  825. pbn_b3_4_115200,
  826. pbn_b3_8_115200,
  827. /*
  828. * Board-specific versions.
  829. */
  830. pbn_panacom,
  831. pbn_panacom2,
  832. pbn_panacom4,
  833. pbn_exsys_4055,
  834. pbn_plx_romulus,
  835. pbn_oxsemi,
  836. pbn_intel_i960,
  837. pbn_sgi_ioc3,
  838. pbn_nec_nile4,
  839. pbn_computone_4,
  840. pbn_computone_6,
  841. pbn_computone_8,
  842. pbn_sbsxrsio,
  843. pbn_exar_XR17C152,
  844. pbn_exar_XR17C154,
  845. pbn_exar_XR17C158,
  846. };
  847. /*
  848. * uart_offset - the space between channels
  849. * reg_shift - describes how the UART registers are mapped
  850. * to PCI memory by the card.
  851. * For example IER register on SBS, Inc. PMC-OctPro is located at
  852. * offset 0x10 from the UART base, while UART_IER is defined as 1
  853. * in include/linux/serial_reg.h,
  854. * see first lines of serial_in() and serial_out() in 8250.c
  855. */
  856. static struct pciserial_board pci_boards[] __devinitdata = {
  857. [pbn_default] = {
  858. .flags = FL_BASE0,
  859. .num_ports = 1,
  860. .base_baud = 115200,
  861. .uart_offset = 8,
  862. },
  863. [pbn_b0_1_115200] = {
  864. .flags = FL_BASE0,
  865. .num_ports = 1,
  866. .base_baud = 115200,
  867. .uart_offset = 8,
  868. },
  869. [pbn_b0_2_115200] = {
  870. .flags = FL_BASE0,
  871. .num_ports = 2,
  872. .base_baud = 115200,
  873. .uart_offset = 8,
  874. },
  875. [pbn_b0_4_115200] = {
  876. .flags = FL_BASE0,
  877. .num_ports = 4,
  878. .base_baud = 115200,
  879. .uart_offset = 8,
  880. },
  881. [pbn_b0_5_115200] = {
  882. .flags = FL_BASE0,
  883. .num_ports = 5,
  884. .base_baud = 115200,
  885. .uart_offset = 8,
  886. },
  887. [pbn_b0_1_921600] = {
  888. .flags = FL_BASE0,
  889. .num_ports = 1,
  890. .base_baud = 921600,
  891. .uart_offset = 8,
  892. },
  893. [pbn_b0_2_921600] = {
  894. .flags = FL_BASE0,
  895. .num_ports = 2,
  896. .base_baud = 921600,
  897. .uart_offset = 8,
  898. },
  899. [pbn_b0_4_921600] = {
  900. .flags = FL_BASE0,
  901. .num_ports = 4,
  902. .base_baud = 921600,
  903. .uart_offset = 8,
  904. },
  905. [pbn_b0_2_1130000] = {
  906. .flags = FL_BASE0,
  907. .num_ports = 2,
  908. .base_baud = 1130000,
  909. .uart_offset = 8,
  910. },
  911. [pbn_b0_4_1152000] = {
  912. .flags = FL_BASE0,
  913. .num_ports = 4,
  914. .base_baud = 1152000,
  915. .uart_offset = 8,
  916. },
  917. [pbn_b0_bt_1_115200] = {
  918. .flags = FL_BASE0|FL_BASE_BARS,
  919. .num_ports = 1,
  920. .base_baud = 115200,
  921. .uart_offset = 8,
  922. },
  923. [pbn_b0_bt_2_115200] = {
  924. .flags = FL_BASE0|FL_BASE_BARS,
  925. .num_ports = 2,
  926. .base_baud = 115200,
  927. .uart_offset = 8,
  928. },
  929. [pbn_b0_bt_8_115200] = {
  930. .flags = FL_BASE0|FL_BASE_BARS,
  931. .num_ports = 8,
  932. .base_baud = 115200,
  933. .uart_offset = 8,
  934. },
  935. [pbn_b0_bt_1_460800] = {
  936. .flags = FL_BASE0|FL_BASE_BARS,
  937. .num_ports = 1,
  938. .base_baud = 460800,
  939. .uart_offset = 8,
  940. },
  941. [pbn_b0_bt_2_460800] = {
  942. .flags = FL_BASE0|FL_BASE_BARS,
  943. .num_ports = 2,
  944. .base_baud = 460800,
  945. .uart_offset = 8,
  946. },
  947. [pbn_b0_bt_4_460800] = {
  948. .flags = FL_BASE0|FL_BASE_BARS,
  949. .num_ports = 4,
  950. .base_baud = 460800,
  951. .uart_offset = 8,
  952. },
  953. [pbn_b0_bt_1_921600] = {
  954. .flags = FL_BASE0|FL_BASE_BARS,
  955. .num_ports = 1,
  956. .base_baud = 921600,
  957. .uart_offset = 8,
  958. },
  959. [pbn_b0_bt_2_921600] = {
  960. .flags = FL_BASE0|FL_BASE_BARS,
  961. .num_ports = 2,
  962. .base_baud = 921600,
  963. .uart_offset = 8,
  964. },
  965. [pbn_b0_bt_4_921600] = {
  966. .flags = FL_BASE0|FL_BASE_BARS,
  967. .num_ports = 4,
  968. .base_baud = 921600,
  969. .uart_offset = 8,
  970. },
  971. [pbn_b0_bt_8_921600] = {
  972. .flags = FL_BASE0|FL_BASE_BARS,
  973. .num_ports = 8,
  974. .base_baud = 921600,
  975. .uart_offset = 8,
  976. },
  977. [pbn_b1_1_115200] = {
  978. .flags = FL_BASE1,
  979. .num_ports = 1,
  980. .base_baud = 115200,
  981. .uart_offset = 8,
  982. },
  983. [pbn_b1_2_115200] = {
  984. .flags = FL_BASE1,
  985. .num_ports = 2,
  986. .base_baud = 115200,
  987. .uart_offset = 8,
  988. },
  989. [pbn_b1_4_115200] = {
  990. .flags = FL_BASE1,
  991. .num_ports = 4,
  992. .base_baud = 115200,
  993. .uart_offset = 8,
  994. },
  995. [pbn_b1_8_115200] = {
  996. .flags = FL_BASE1,
  997. .num_ports = 8,
  998. .base_baud = 115200,
  999. .uart_offset = 8,
  1000. },
  1001. [pbn_b1_1_921600] = {
  1002. .flags = FL_BASE1,
  1003. .num_ports = 1,
  1004. .base_baud = 921600,
  1005. .uart_offset = 8,
  1006. },
  1007. [pbn_b1_2_921600] = {
  1008. .flags = FL_BASE1,
  1009. .num_ports = 2,
  1010. .base_baud = 921600,
  1011. .uart_offset = 8,
  1012. },
  1013. [pbn_b1_4_921600] = {
  1014. .flags = FL_BASE1,
  1015. .num_ports = 4,
  1016. .base_baud = 921600,
  1017. .uart_offset = 8,
  1018. },
  1019. [pbn_b1_8_921600] = {
  1020. .flags = FL_BASE1,
  1021. .num_ports = 8,
  1022. .base_baud = 921600,
  1023. .uart_offset = 8,
  1024. },
  1025. [pbn_b1_bt_2_921600] = {
  1026. .flags = FL_BASE1|FL_BASE_BARS,
  1027. .num_ports = 2,
  1028. .base_baud = 921600,
  1029. .uart_offset = 8,
  1030. },
  1031. [pbn_b1_1_1382400] = {
  1032. .flags = FL_BASE1,
  1033. .num_ports = 1,
  1034. .base_baud = 1382400,
  1035. .uart_offset = 8,
  1036. },
  1037. [pbn_b1_2_1382400] = {
  1038. .flags = FL_BASE1,
  1039. .num_ports = 2,
  1040. .base_baud = 1382400,
  1041. .uart_offset = 8,
  1042. },
  1043. [pbn_b1_4_1382400] = {
  1044. .flags = FL_BASE1,
  1045. .num_ports = 4,
  1046. .base_baud = 1382400,
  1047. .uart_offset = 8,
  1048. },
  1049. [pbn_b1_8_1382400] = {
  1050. .flags = FL_BASE1,
  1051. .num_ports = 8,
  1052. .base_baud = 1382400,
  1053. .uart_offset = 8,
  1054. },
  1055. [pbn_b2_1_115200] = {
  1056. .flags = FL_BASE2,
  1057. .num_ports = 1,
  1058. .base_baud = 115200,
  1059. .uart_offset = 8,
  1060. },
  1061. [pbn_b2_8_115200] = {
  1062. .flags = FL_BASE2,
  1063. .num_ports = 8,
  1064. .base_baud = 115200,
  1065. .uart_offset = 8,
  1066. },
  1067. [pbn_b2_1_460800] = {
  1068. .flags = FL_BASE2,
  1069. .num_ports = 1,
  1070. .base_baud = 460800,
  1071. .uart_offset = 8,
  1072. },
  1073. [pbn_b2_4_460800] = {
  1074. .flags = FL_BASE2,
  1075. .num_ports = 4,
  1076. .base_baud = 460800,
  1077. .uart_offset = 8,
  1078. },
  1079. [pbn_b2_8_460800] = {
  1080. .flags = FL_BASE2,
  1081. .num_ports = 8,
  1082. .base_baud = 460800,
  1083. .uart_offset = 8,
  1084. },
  1085. [pbn_b2_16_460800] = {
  1086. .flags = FL_BASE2,
  1087. .num_ports = 16,
  1088. .base_baud = 460800,
  1089. .uart_offset = 8,
  1090. },
  1091. [pbn_b2_1_921600] = {
  1092. .flags = FL_BASE2,
  1093. .num_ports = 1,
  1094. .base_baud = 921600,
  1095. .uart_offset = 8,
  1096. },
  1097. [pbn_b2_4_921600] = {
  1098. .flags = FL_BASE2,
  1099. .num_ports = 4,
  1100. .base_baud = 921600,
  1101. .uart_offset = 8,
  1102. },
  1103. [pbn_b2_8_921600] = {
  1104. .flags = FL_BASE2,
  1105. .num_ports = 8,
  1106. .base_baud = 921600,
  1107. .uart_offset = 8,
  1108. },
  1109. [pbn_b2_bt_1_115200] = {
  1110. .flags = FL_BASE2|FL_BASE_BARS,
  1111. .num_ports = 1,
  1112. .base_baud = 115200,
  1113. .uart_offset = 8,
  1114. },
  1115. [pbn_b2_bt_2_115200] = {
  1116. .flags = FL_BASE2|FL_BASE_BARS,
  1117. .num_ports = 2,
  1118. .base_baud = 115200,
  1119. .uart_offset = 8,
  1120. },
  1121. [pbn_b2_bt_4_115200] = {
  1122. .flags = FL_BASE2|FL_BASE_BARS,
  1123. .num_ports = 4,
  1124. .base_baud = 115200,
  1125. .uart_offset = 8,
  1126. },
  1127. [pbn_b2_bt_2_921600] = {
  1128. .flags = FL_BASE2|FL_BASE_BARS,
  1129. .num_ports = 2,
  1130. .base_baud = 921600,
  1131. .uart_offset = 8,
  1132. },
  1133. [pbn_b2_bt_4_921600] = {
  1134. .flags = FL_BASE2|FL_BASE_BARS,
  1135. .num_ports = 4,
  1136. .base_baud = 921600,
  1137. .uart_offset = 8,
  1138. },
  1139. [pbn_b3_4_115200] = {
  1140. .flags = FL_BASE3,
  1141. .num_ports = 4,
  1142. .base_baud = 115200,
  1143. .uart_offset = 8,
  1144. },
  1145. [pbn_b3_8_115200] = {
  1146. .flags = FL_BASE3,
  1147. .num_ports = 8,
  1148. .base_baud = 115200,
  1149. .uart_offset = 8,
  1150. },
  1151. /*
  1152. * Entries following this are board-specific.
  1153. */
  1154. /*
  1155. * Panacom - IOMEM
  1156. */
  1157. [pbn_panacom] = {
  1158. .flags = FL_BASE2,
  1159. .num_ports = 2,
  1160. .base_baud = 921600,
  1161. .uart_offset = 0x400,
  1162. .reg_shift = 7,
  1163. },
  1164. [pbn_panacom2] = {
  1165. .flags = FL_BASE2|FL_BASE_BARS,
  1166. .num_ports = 2,
  1167. .base_baud = 921600,
  1168. .uart_offset = 0x400,
  1169. .reg_shift = 7,
  1170. },
  1171. [pbn_panacom4] = {
  1172. .flags = FL_BASE2|FL_BASE_BARS,
  1173. .num_ports = 4,
  1174. .base_baud = 921600,
  1175. .uart_offset = 0x400,
  1176. .reg_shift = 7,
  1177. },
  1178. [pbn_exsys_4055] = {
  1179. .flags = FL_BASE2,
  1180. .num_ports = 4,
  1181. .base_baud = 115200,
  1182. .uart_offset = 8,
  1183. },
  1184. /* I think this entry is broken - the first_offset looks wrong --rmk */
  1185. [pbn_plx_romulus] = {
  1186. .flags = FL_BASE2,
  1187. .num_ports = 4,
  1188. .base_baud = 921600,
  1189. .uart_offset = 8 << 2,
  1190. .reg_shift = 2,
  1191. .first_offset = 0x03,
  1192. },
  1193. /*
  1194. * This board uses the size of PCI Base region 0 to
  1195. * signal now many ports are available
  1196. */
  1197. [pbn_oxsemi] = {
  1198. .flags = FL_BASE0|FL_REGION_SZ_CAP,
  1199. .num_ports = 32,
  1200. .base_baud = 115200,
  1201. .uart_offset = 8,
  1202. },
  1203. /*
  1204. * EKF addition for i960 Boards form EKF with serial port.
  1205. * Max 256 ports.
  1206. */
  1207. [pbn_intel_i960] = {
  1208. .flags = FL_BASE0,
  1209. .num_ports = 32,
  1210. .base_baud = 921600,
  1211. .uart_offset = 8 << 2,
  1212. .reg_shift = 2,
  1213. .first_offset = 0x10000,
  1214. },
  1215. [pbn_sgi_ioc3] = {
  1216. .flags = FL_BASE0|FL_NOIRQ,
  1217. .num_ports = 1,
  1218. .base_baud = 458333,
  1219. .uart_offset = 8,
  1220. .reg_shift = 0,
  1221. .first_offset = 0x20178,
  1222. },
  1223. /*
  1224. * NEC Vrc-5074 (Nile 4) builtin UART.
  1225. */
  1226. [pbn_nec_nile4] = {
  1227. .flags = FL_BASE0,
  1228. .num_ports = 1,
  1229. .base_baud = 520833,
  1230. .uart_offset = 8 << 3,
  1231. .reg_shift = 3,
  1232. .first_offset = 0x300,
  1233. },
  1234. /*
  1235. * Computone - uses IOMEM.
  1236. */
  1237. [pbn_computone_4] = {
  1238. .flags = FL_BASE0,
  1239. .num_ports = 4,
  1240. .base_baud = 921600,
  1241. .uart_offset = 0x40,
  1242. .reg_shift = 2,
  1243. .first_offset = 0x200,
  1244. },
  1245. [pbn_computone_6] = {
  1246. .flags = FL_BASE0,
  1247. .num_ports = 6,
  1248. .base_baud = 921600,
  1249. .uart_offset = 0x40,
  1250. .reg_shift = 2,
  1251. .first_offset = 0x200,
  1252. },
  1253. [pbn_computone_8] = {
  1254. .flags = FL_BASE0,
  1255. .num_ports = 8,
  1256. .base_baud = 921600,
  1257. .uart_offset = 0x40,
  1258. .reg_shift = 2,
  1259. .first_offset = 0x200,
  1260. },
  1261. [pbn_sbsxrsio] = {
  1262. .flags = FL_BASE0,
  1263. .num_ports = 8,
  1264. .base_baud = 460800,
  1265. .uart_offset = 256,
  1266. .reg_shift = 4,
  1267. },
  1268. /*
  1269. * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
  1270. * Only basic 16550A support.
  1271. * XR17C15[24] are not tested, but they should work.
  1272. */
  1273. [pbn_exar_XR17C152] = {
  1274. .flags = FL_BASE0,
  1275. .num_ports = 2,
  1276. .base_baud = 921600,
  1277. .uart_offset = 0x200,
  1278. },
  1279. [pbn_exar_XR17C154] = {
  1280. .flags = FL_BASE0,
  1281. .num_ports = 4,
  1282. .base_baud = 921600,
  1283. .uart_offset = 0x200,
  1284. },
  1285. [pbn_exar_XR17C158] = {
  1286. .flags = FL_BASE0,
  1287. .num_ports = 8,
  1288. .base_baud = 921600,
  1289. .uart_offset = 0x200,
  1290. },
  1291. };
  1292. /*
  1293. * Given a complete unknown PCI device, try to use some heuristics to
  1294. * guess what the configuration might be, based on the pitiful PCI
  1295. * serial specs. Returns 0 on success, 1 on failure.
  1296. */
  1297. static int __devinit
  1298. serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
  1299. {
  1300. int num_iomem, num_port, first_port = -1, i;
  1301. /*
  1302. * If it is not a communications device or the programming
  1303. * interface is greater than 6, give up.
  1304. *
  1305. * (Should we try to make guesses for multiport serial devices
  1306. * later?)
  1307. */
  1308. if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
  1309. ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
  1310. (dev->class & 0xff) > 6)
  1311. return -ENODEV;
  1312. num_iomem = num_port = 0;
  1313. for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
  1314. if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
  1315. num_port++;
  1316. if (first_port == -1)
  1317. first_port = i;
  1318. }
  1319. if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
  1320. num_iomem++;
  1321. }
  1322. /*
  1323. * If there is 1 or 0 iomem regions, and exactly one port,
  1324. * use it. We guess the number of ports based on the IO
  1325. * region size.
  1326. */
  1327. if (num_iomem <= 1 && num_port == 1) {
  1328. board->flags = first_port;
  1329. board->num_ports = pci_resource_len(dev, first_port) / 8;
  1330. return 0;
  1331. }
  1332. /*
  1333. * Now guess if we've got a board which indexes by BARs.
  1334. * Each IO BAR should be 8 bytes, and they should follow
  1335. * consecutively.
  1336. */
  1337. first_port = -1;
  1338. num_port = 0;
  1339. for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
  1340. if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
  1341. pci_resource_len(dev, i) == 8 &&
  1342. (first_port == -1 || (first_port + num_port) == i)) {
  1343. num_port++;
  1344. if (first_port == -1)
  1345. first_port = i;
  1346. }
  1347. }
  1348. if (num_port > 1) {
  1349. board->flags = first_port | FL_BASE_BARS;
  1350. board->num_ports = num_port;
  1351. return 0;
  1352. }
  1353. return -ENODEV;
  1354. }
  1355. static inline int
  1356. serial_pci_matches(struct pciserial_board *board,
  1357. struct pciserial_board *guessed)
  1358. {
  1359. return
  1360. board->num_ports == guessed->num_ports &&
  1361. board->base_baud == guessed->base_baud &&
  1362. board->uart_offset == guessed->uart_offset &&
  1363. board->reg_shift == guessed->reg_shift &&
  1364. board->first_offset == guessed->first_offset;
  1365. }
  1366. struct serial_private *
  1367. pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
  1368. {
  1369. struct uart_port serial_port;
  1370. struct serial_private *priv;
  1371. struct pci_serial_quirk *quirk;
  1372. int rc, nr_ports, i;
  1373. nr_ports = board->num_ports;
  1374. /*
  1375. * Find an init and setup quirks.
  1376. */
  1377. quirk = find_quirk(dev);
  1378. /*
  1379. * Run the new-style initialization function.
  1380. * The initialization function returns:
  1381. * <0 - error
  1382. * 0 - use board->num_ports
  1383. * >0 - number of ports
  1384. */
  1385. if (quirk->init) {
  1386. rc = quirk->init(dev);
  1387. if (rc < 0) {
  1388. priv = ERR_PTR(rc);
  1389. goto err_out;
  1390. }
  1391. if (rc)
  1392. nr_ports = rc;
  1393. }
  1394. priv = kmalloc(sizeof(struct serial_private) +
  1395. sizeof(unsigned int) * nr_ports,
  1396. GFP_KERNEL);
  1397. if (!priv) {
  1398. priv = ERR_PTR(-ENOMEM);
  1399. goto err_deinit;
  1400. }
  1401. memset(priv, 0, sizeof(struct serial_private) +
  1402. sizeof(unsigned int) * nr_ports);
  1403. priv->dev = dev;
  1404. priv->quirk = quirk;
  1405. memset(&serial_port, 0, sizeof(struct uart_port));
  1406. serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
  1407. serial_port.uartclk = board->base_baud * 16;
  1408. serial_port.irq = get_pci_irq(dev, board);
  1409. serial_port.dev = &dev->dev;
  1410. for (i = 0; i < nr_ports; i++) {
  1411. if (quirk->setup(priv, board, &serial_port, i))
  1412. break;
  1413. #ifdef SERIAL_DEBUG_PCI
  1414. printk("Setup PCI port: port %x, irq %d, type %d\n",
  1415. serial_port.iobase, serial_port.irq, serial_port.iotype);
  1416. #endif
  1417. priv->line[i] = serial8250_register_port(&serial_port);
  1418. if (priv->line[i] < 0) {
  1419. printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
  1420. break;
  1421. }
  1422. }
  1423. priv->nr = i;
  1424. return priv;
  1425. err_deinit:
  1426. if (quirk->exit)
  1427. quirk->exit(dev);
  1428. err_out:
  1429. return priv;
  1430. }
  1431. EXPORT_SYMBOL_GPL(pciserial_init_ports);
  1432. void pciserial_remove_ports(struct serial_private *priv)
  1433. {
  1434. struct pci_serial_quirk *quirk;
  1435. int i;
  1436. for (i = 0; i < priv->nr; i++)
  1437. serial8250_unregister_port(priv->line[i]);
  1438. for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
  1439. if (priv->remapped_bar[i])
  1440. iounmap(priv->remapped_bar[i]);
  1441. priv->remapped_bar[i] = NULL;
  1442. }
  1443. /*
  1444. * Find the exit quirks.
  1445. */
  1446. quirk = find_quirk(priv->dev);
  1447. if (quirk->exit)
  1448. quirk->exit(priv->dev);
  1449. kfree(priv);
  1450. }
  1451. EXPORT_SYMBOL_GPL(pciserial_remove_ports);
  1452. void pciserial_suspend_ports(struct serial_private *priv)
  1453. {
  1454. int i;
  1455. for (i = 0; i < priv->nr; i++)
  1456. if (priv->line[i] >= 0)
  1457. serial8250_suspend_port(priv->line[i]);
  1458. }
  1459. EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
  1460. void pciserial_resume_ports(struct serial_private *priv)
  1461. {
  1462. int i;
  1463. /*
  1464. * Ensure that the board is correctly configured.
  1465. */
  1466. if (priv->quirk->init)
  1467. priv->quirk->init(priv->dev);
  1468. for (i = 0; i < priv->nr; i++)
  1469. if (priv->line[i] >= 0)
  1470. serial8250_resume_port(priv->line[i]);
  1471. }
  1472. EXPORT_SYMBOL_GPL(pciserial_resume_ports);
  1473. /*
  1474. * Probe one serial board. Unfortunately, there is no rhyme nor reason
  1475. * to the arrangement of serial ports on a PCI card.
  1476. */
  1477. static int __devinit
  1478. pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
  1479. {
  1480. struct serial_private *priv;
  1481. struct pciserial_board *board, tmp;
  1482. int rc;
  1483. if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
  1484. printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
  1485. ent->driver_data);
  1486. return -EINVAL;
  1487. }
  1488. board = &pci_boards[ent->driver_data];
  1489. rc = pci_enable_device(dev);
  1490. if (rc)
  1491. return rc;
  1492. if (ent->driver_data == pbn_default) {
  1493. /*
  1494. * Use a copy of the pci_board entry for this;
  1495. * avoid changing entries in the table.
  1496. */
  1497. memcpy(&tmp, board, sizeof(struct pciserial_board));
  1498. board = &tmp;
  1499. /*
  1500. * We matched one of our class entries. Try to
  1501. * determine the parameters of this board.
  1502. */
  1503. rc = serial_pci_guess_board(dev, board);
  1504. if (rc)
  1505. goto disable;
  1506. } else {
  1507. /*
  1508. * We matched an explicit entry. If we are able to
  1509. * detect this boards settings with our heuristic,
  1510. * then we no longer need this entry.
  1511. */
  1512. memcpy(&tmp, &pci_boards[pbn_default],
  1513. sizeof(struct pciserial_board));
  1514. rc = serial_pci_guess_board(dev, &tmp);
  1515. if (rc == 0 && serial_pci_matches(board, &tmp))
  1516. moan_device("Redundant entry in serial pci_table.",
  1517. dev);
  1518. }
  1519. priv = pciserial_init_ports(dev, board);
  1520. if (!IS_ERR(priv)) {
  1521. pci_set_drvdata(dev, priv);
  1522. return 0;
  1523. }
  1524. rc = PTR_ERR(priv);
  1525. disable:
  1526. pci_disable_device(dev);
  1527. return rc;
  1528. }
  1529. static void __devexit pciserial_remove_one(struct pci_dev *dev)
  1530. {
  1531. struct serial_private *priv = pci_get_drvdata(dev);
  1532. pci_set_drvdata(dev, NULL);
  1533. pciserial_remove_ports(priv);
  1534. pci_disable_device(dev);
  1535. }
  1536. static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
  1537. {
  1538. struct serial_private *priv = pci_get_drvdata(dev);
  1539. if (priv)
  1540. pciserial_suspend_ports(priv);
  1541. pci_save_state(dev);
  1542. pci_set_power_state(dev, pci_choose_state(dev, state));
  1543. return 0;
  1544. }
  1545. static int pciserial_resume_one(struct pci_dev *dev)
  1546. {
  1547. struct serial_private *priv = pci_get_drvdata(dev);
  1548. pci_set_power_state(dev, PCI_D0);
  1549. pci_restore_state(dev);
  1550. if (priv) {
  1551. /*
  1552. * The device may have been disabled. Re-enable it.
  1553. */
  1554. pci_enable_device(dev);
  1555. pciserial_resume_ports(priv);
  1556. }
  1557. return 0;
  1558. }
  1559. static struct pci_device_id serial_pci_tbl[] = {
  1560. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
  1561. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1562. PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
  1563. pbn_b1_8_1382400 },
  1564. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
  1565. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1566. PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
  1567. pbn_b1_4_1382400 },
  1568. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
  1569. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1570. PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
  1571. pbn_b1_2_1382400 },
  1572. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1573. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1574. PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
  1575. pbn_b1_8_1382400 },
  1576. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1577. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1578. PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
  1579. pbn_b1_4_1382400 },
  1580. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1581. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1582. PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
  1583. pbn_b1_2_1382400 },
  1584. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1585. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1586. PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
  1587. pbn_b1_8_921600 },
  1588. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1589. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1590. PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
  1591. pbn_b1_8_921600 },
  1592. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1593. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1594. PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
  1595. pbn_b1_4_921600 },
  1596. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1597. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1598. PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
  1599. pbn_b1_4_921600 },
  1600. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1601. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1602. PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
  1603. pbn_b1_2_921600 },
  1604. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1605. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1606. PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
  1607. pbn_b1_8_921600 },
  1608. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1609. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1610. PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
  1611. pbn_b1_8_921600 },
  1612. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  1613. PCI_SUBVENDOR_ID_CONNECT_TECH,
  1614. PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
  1615. pbn_b1_4_921600 },
  1616. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
  1617. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1618. pbn_b2_bt_1_115200 },
  1619. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
  1620. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1621. pbn_b2_bt_2_115200 },
  1622. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
  1623. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1624. pbn_b2_bt_4_115200 },
  1625. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
  1626. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1627. pbn_b2_bt_2_115200 },
  1628. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
  1629. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1630. pbn_b2_bt_4_115200 },
  1631. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
  1632. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1633. pbn_b2_8_115200 },
  1634. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
  1635. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1636. pbn_b2_8_115200 },
  1637. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
  1638. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1639. pbn_b2_bt_2_115200 },
  1640. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
  1641. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1642. pbn_b2_bt_2_921600 },
  1643. /*
  1644. * VScom SPCOM800, from sl@s.pl
  1645. */
  1646. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
  1647. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1648. pbn_b2_8_921600 },
  1649. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
  1650. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1651. pbn_b2_4_921600 },
  1652. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  1653. PCI_SUBVENDOR_ID_KEYSPAN,
  1654. PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
  1655. pbn_panacom },
  1656. { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
  1657. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1658. pbn_panacom4 },
  1659. { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
  1660. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1661. pbn_panacom2 },
  1662. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  1663. PCI_SUBVENDOR_ID_CHASE_PCIFAST,
  1664. PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
  1665. pbn_b2_4_460800 },
  1666. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  1667. PCI_SUBVENDOR_ID_CHASE_PCIFAST,
  1668. PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
  1669. pbn_b2_8_460800 },
  1670. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  1671. PCI_SUBVENDOR_ID_CHASE_PCIFAST,
  1672. PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
  1673. pbn_b2_16_460800 },
  1674. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  1675. PCI_SUBVENDOR_ID_CHASE_PCIFAST,
  1676. PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
  1677. pbn_b2_16_460800 },
  1678. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  1679. PCI_SUBVENDOR_ID_CHASE_PCIRAS,
  1680. PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
  1681. pbn_b2_4_460800 },
  1682. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  1683. PCI_SUBVENDOR_ID_CHASE_PCIRAS,
  1684. PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
  1685. pbn_b2_8_460800 },
  1686. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  1687. PCI_SUBVENDOR_ID_EXSYS,
  1688. PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
  1689. pbn_exsys_4055 },
  1690. /*
  1691. * Megawolf Romulus PCI Serial Card, from Mike Hudson
  1692. * (Exoray@isys.ca)
  1693. */
  1694. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
  1695. 0x10b5, 0x106a, 0, 0,
  1696. pbn_plx_romulus },
  1697. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
  1698. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1699. pbn_b1_4_115200 },
  1700. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
  1701. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1702. pbn_b1_2_115200 },
  1703. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
  1704. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1705. pbn_b1_8_115200 },
  1706. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
  1707. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1708. pbn_b1_8_115200 },
  1709. { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
  1710. PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
  1711. pbn_b0_4_921600 },
  1712. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
  1713. PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
  1714. pbn_b0_4_1152000 },
  1715. /*
  1716. * The below card is a little controversial since it is the
  1717. * subject of a PCI vendor/device ID clash. (See
  1718. * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
  1719. * For now just used the hex ID 0x950a.
  1720. */
  1721. { PCI_VENDOR_ID_OXSEMI, 0x950a,
  1722. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1723. pbn_b0_2_1130000 },
  1724. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
  1725. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1726. pbn_b0_4_115200 },
  1727. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
  1728. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1729. pbn_b0_bt_2_921600 },
  1730. /*
  1731. * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
  1732. * from skokodyn@yahoo.com
  1733. */
  1734. { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
  1735. PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
  1736. pbn_sbsxrsio },
  1737. { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
  1738. PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
  1739. pbn_sbsxrsio },
  1740. { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
  1741. PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
  1742. pbn_sbsxrsio },
  1743. { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
  1744. PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
  1745. pbn_sbsxrsio },
  1746. /*
  1747. * Digitan DS560-558, from jimd@esoft.com
  1748. */
  1749. { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
  1750. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1751. pbn_b1_1_115200 },
  1752. /*
  1753. * Titan Electronic cards
  1754. * The 400L and 800L have a custom setup quirk.
  1755. */
  1756. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
  1757. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1758. pbn_b0_1_921600 },
  1759. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
  1760. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1761. pbn_b0_2_921600 },
  1762. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
  1763. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1764. pbn_b0_4_921600 },
  1765. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
  1766. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1767. pbn_b0_4_921600 },
  1768. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
  1769. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1770. pbn_b1_1_921600 },
  1771. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
  1772. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1773. pbn_b1_bt_2_921600 },
  1774. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
  1775. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1776. pbn_b0_bt_4_921600 },
  1777. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
  1778. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1779. pbn_b0_bt_8_921600 },
  1780. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
  1781. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1782. pbn_b2_1_460800 },
  1783. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
  1784. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1785. pbn_b2_1_460800 },
  1786. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
  1787. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1788. pbn_b2_1_460800 },
  1789. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
  1790. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1791. pbn_b2_bt_2_921600 },
  1792. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
  1793. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1794. pbn_b2_bt_2_921600 },
  1795. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
  1796. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1797. pbn_b2_bt_2_921600 },
  1798. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
  1799. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1800. pbn_b2_bt_4_921600 },
  1801. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
  1802. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1803. pbn_b2_bt_4_921600 },
  1804. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
  1805. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1806. pbn_b2_bt_4_921600 },
  1807. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
  1808. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1809. pbn_b0_1_921600 },
  1810. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
  1811. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1812. pbn_b0_1_921600 },
  1813. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
  1814. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1815. pbn_b0_1_921600 },
  1816. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
  1817. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1818. pbn_b0_bt_2_921600 },
  1819. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
  1820. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1821. pbn_b0_bt_2_921600 },
  1822. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
  1823. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1824. pbn_b0_bt_2_921600 },
  1825. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
  1826. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1827. pbn_b0_bt_4_921600 },
  1828. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
  1829. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1830. pbn_b0_bt_4_921600 },
  1831. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
  1832. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1833. pbn_b0_bt_4_921600 },
  1834. /*
  1835. * Computone devices submitted by Doug McNash dmcnash@computone.com
  1836. */
  1837. { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
  1838. PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
  1839. 0, 0, pbn_computone_4 },
  1840. { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
  1841. PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
  1842. 0, 0, pbn_computone_8 },
  1843. { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
  1844. PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
  1845. 0, 0, pbn_computone_6 },
  1846. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
  1847. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1848. pbn_oxsemi },
  1849. { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
  1850. PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
  1851. pbn_b0_bt_1_921600 },
  1852. /*
  1853. * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
  1854. */
  1855. { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
  1856. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1857. pbn_b0_bt_8_115200 },
  1858. { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
  1859. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1860. pbn_b0_bt_8_115200 },
  1861. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
  1862. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1863. pbn_b0_bt_2_115200 },
  1864. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
  1865. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1866. pbn_b0_bt_2_115200 },
  1867. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
  1868. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1869. pbn_b0_bt_2_115200 },
  1870. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
  1871. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1872. pbn_b0_bt_4_460800 },
  1873. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
  1874. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1875. pbn_b0_bt_4_460800 },
  1876. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
  1877. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1878. pbn_b0_bt_2_460800 },
  1879. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
  1880. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1881. pbn_b0_bt_2_460800 },
  1882. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
  1883. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1884. pbn_b0_bt_2_460800 },
  1885. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
  1886. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1887. pbn_b0_bt_1_115200 },
  1888. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
  1889. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1890. pbn_b0_bt_1_460800 },
  1891. /*
  1892. * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
  1893. */
  1894. { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
  1895. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1896. pbn_b1_1_1382400 },
  1897. /*
  1898. * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
  1899. */
  1900. { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
  1901. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1902. pbn_b1_1_1382400 },
  1903. /*
  1904. * RAStel 2 port modem, gerg@moreton.com.au
  1905. */
  1906. { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
  1907. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1908. pbn_b2_bt_2_115200 },
  1909. /*
  1910. * EKF addition for i960 Boards form EKF with serial port
  1911. */
  1912. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
  1913. 0xE4BF, PCI_ANY_ID, 0, 0,
  1914. pbn_intel_i960 },
  1915. /*
  1916. * Xircom Cardbus/Ethernet combos
  1917. */
  1918. { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
  1919. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1920. pbn_b0_1_115200 },
  1921. /*
  1922. * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
  1923. */
  1924. { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
  1925. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1926. pbn_b0_1_115200 },
  1927. /*
  1928. * Untested PCI modems, sent in from various folks...
  1929. */
  1930. /*
  1931. * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
  1932. */
  1933. { PCI_VENDOR_ID_ROCKWELL, 0x1004,
  1934. 0x1048, 0x1500, 0, 0,
  1935. pbn_b1_1_115200 },
  1936. { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
  1937. 0xFF00, 0, 0, 0,
  1938. pbn_sgi_ioc3 },
  1939. /*
  1940. * HP Diva card
  1941. */
  1942. { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
  1943. PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
  1944. pbn_b1_1_115200 },
  1945. { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
  1946. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1947. pbn_b0_5_115200 },
  1948. { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
  1949. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1950. pbn_b2_1_115200 },
  1951. /*
  1952. * NEC Vrc-5074 (Nile 4) builtin UART.
  1953. */
  1954. { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
  1955. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1956. pbn_nec_nile4 },
  1957. { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
  1958. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1959. pbn_b3_4_115200 },
  1960. { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
  1961. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1962. pbn_b3_8_115200 },
  1963. /*
  1964. * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
  1965. */
  1966. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
  1967. PCI_ANY_ID, PCI_ANY_ID,
  1968. 0,
  1969. 0, pbn_exar_XR17C152 },
  1970. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
  1971. PCI_ANY_ID, PCI_ANY_ID,
  1972. 0,
  1973. 0, pbn_exar_XR17C154 },
  1974. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
  1975. PCI_ANY_ID, PCI_ANY_ID,
  1976. 0,
  1977. 0, pbn_exar_XR17C158 },
  1978. /*
  1979. * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
  1980. */
  1981. { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
  1982. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1983. pbn_b0_1_115200 },
  1984. /*
  1985. * These entries match devices with class COMMUNICATION_SERIAL,
  1986. * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
  1987. */
  1988. { PCI_ANY_ID, PCI_ANY_ID,
  1989. PCI_ANY_ID, PCI_ANY_ID,
  1990. PCI_CLASS_COMMUNICATION_SERIAL << 8,
  1991. 0xffff00, pbn_default },
  1992. { PCI_ANY_ID, PCI_ANY_ID,
  1993. PCI_ANY_ID, PCI_ANY_ID,
  1994. PCI_CLASS_COMMUNICATION_MODEM << 8,
  1995. 0xffff00, pbn_default },
  1996. { PCI_ANY_ID, PCI_ANY_ID,
  1997. PCI_ANY_ID, PCI_ANY_ID,
  1998. PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
  1999. 0xffff00, pbn_default },
  2000. { 0, }
  2001. };
  2002. static struct pci_driver serial_pci_driver = {
  2003. .name = "serial",
  2004. .probe = pciserial_init_one,
  2005. .remove = __devexit_p(pciserial_remove_one),
  2006. .suspend = pciserial_suspend_one,
  2007. .resume = pciserial_resume_one,
  2008. .id_table = serial_pci_tbl,
  2009. };
  2010. static int __init serial8250_pci_init(void)
  2011. {
  2012. return pci_register_driver(&serial_pci_driver);
  2013. }
  2014. static void __exit serial8250_pci_exit(void)
  2015. {
  2016. pci_unregister_driver(&serial_pci_driver);
  2017. }
  2018. module_init(serial8250_pci_init);
  2019. module_exit(serial8250_pci_exit);
  2020. MODULE_LICENSE("GPL");
  2021. MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
  2022. MODULE_DEVICE_TABLE(pci, serial_pci_tbl);