ep93xx-i2s.c 12 KB

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  1. /*
  2. * linux/sound/soc/ep93xx-i2s.c
  3. * EP93xx I2S driver
  4. *
  5. * Copyright (C) 2010 Ryan Mallon <ryan@bluewatersys.com>
  6. *
  7. * Based on the original driver by:
  8. * Copyright (C) 2007 Chase Douglas <chasedouglas@gmail>
  9. * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. *
  15. */
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/slab.h>
  19. #include <linux/clk.h>
  20. #include <linux/io.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/initval.h>
  25. #include <sound/soc.h>
  26. #include <mach/hardware.h>
  27. #include <mach/ep93xx-regs.h>
  28. #include <mach/dma.h>
  29. #include "ep93xx-pcm.h"
  30. #define EP93XX_I2S_TXCLKCFG 0x00
  31. #define EP93XX_I2S_RXCLKCFG 0x04
  32. #define EP93XX_I2S_GLCTRL 0x0C
  33. #define EP93XX_I2S_TXLINCTRLDATA 0x28
  34. #define EP93XX_I2S_TXCTRL 0x2C
  35. #define EP93XX_I2S_TXWRDLEN 0x30
  36. #define EP93XX_I2S_TX0EN 0x34
  37. #define EP93XX_I2S_RXLINCTRLDATA 0x58
  38. #define EP93XX_I2S_RXCTRL 0x5C
  39. #define EP93XX_I2S_RXWRDLEN 0x60
  40. #define EP93XX_I2S_RX0EN 0x64
  41. #define EP93XX_I2S_WRDLEN_16 (0 << 0)
  42. #define EP93XX_I2S_WRDLEN_24 (1 << 0)
  43. #define EP93XX_I2S_WRDLEN_32 (2 << 0)
  44. #define EP93XX_I2S_LINCTRLDATA_R_JUST (1 << 2) /* Right justify */
  45. #define EP93XX_I2S_CLKCFG_LRS (1 << 0) /* lrclk polarity */
  46. #define EP93XX_I2S_CLKCFG_CKP (1 << 1) /* Bit clock polarity */
  47. #define EP93XX_I2S_CLKCFG_REL (1 << 2) /* First bit transition */
  48. #define EP93XX_I2S_CLKCFG_MASTER (1 << 3) /* Master mode */
  49. #define EP93XX_I2S_CLKCFG_NBCG (1 << 4) /* Not bit clock gating */
  50. struct ep93xx_i2s_info {
  51. struct clk *mclk;
  52. struct clk *sclk;
  53. struct clk *lrclk;
  54. struct ep93xx_pcm_dma_params *dma_params;
  55. struct resource *mem;
  56. void __iomem *regs;
  57. };
  58. struct ep93xx_pcm_dma_params ep93xx_i2s_dma_params[] = {
  59. [SNDRV_PCM_STREAM_PLAYBACK] = {
  60. .name = "i2s-pcm-out",
  61. .dma_port = EP93XX_DMA_M2P_PORT_I2S1,
  62. },
  63. [SNDRV_PCM_STREAM_CAPTURE] = {
  64. .name = "i2s-pcm-in",
  65. .dma_port = EP93XX_DMA_M2P_PORT_I2S1,
  66. },
  67. };
  68. static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info *info,
  69. unsigned reg, unsigned val)
  70. {
  71. __raw_writel(val, info->regs + reg);
  72. }
  73. static inline unsigned ep93xx_i2s_read_reg(struct ep93xx_i2s_info *info,
  74. unsigned reg)
  75. {
  76. return __raw_readl(info->regs + reg);
  77. }
  78. static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream)
  79. {
  80. unsigned base_reg;
  81. int i;
  82. if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
  83. (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
  84. /* Enable clocks */
  85. clk_enable(info->mclk);
  86. clk_enable(info->sclk);
  87. clk_enable(info->lrclk);
  88. /* Enable i2s */
  89. ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 1);
  90. }
  91. /* Enable fifos */
  92. if (stream == SNDRV_PCM_STREAM_PLAYBACK)
  93. base_reg = EP93XX_I2S_TX0EN;
  94. else
  95. base_reg = EP93XX_I2S_RX0EN;
  96. for (i = 0; i < 3; i++)
  97. ep93xx_i2s_write_reg(info, base_reg + (i * 4), 1);
  98. }
  99. static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream)
  100. {
  101. unsigned base_reg;
  102. int i;
  103. /* Disable fifos */
  104. if (stream == SNDRV_PCM_STREAM_PLAYBACK)
  105. base_reg = EP93XX_I2S_TX0EN;
  106. else
  107. base_reg = EP93XX_I2S_RX0EN;
  108. for (i = 0; i < 3; i++)
  109. ep93xx_i2s_write_reg(info, base_reg + (i * 4), 0);
  110. if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
  111. (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
  112. /* Disable i2s */
  113. ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 0);
  114. /* Disable clocks */
  115. clk_disable(info->lrclk);
  116. clk_disable(info->sclk);
  117. clk_disable(info->mclk);
  118. }
  119. }
  120. static int ep93xx_i2s_startup(struct snd_pcm_substream *substream,
  121. struct snd_soc_dai *dai)
  122. {
  123. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  124. struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
  125. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  126. snd_soc_dai_set_dma_data(cpu_dai, substream,
  127. &info->dma_params[substream->stream]);
  128. return 0;
  129. }
  130. static void ep93xx_i2s_shutdown(struct snd_pcm_substream *substream,
  131. struct snd_soc_dai *dai)
  132. {
  133. struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
  134. ep93xx_i2s_disable(info, substream->stream);
  135. }
  136. static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
  137. unsigned int fmt)
  138. {
  139. struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
  140. unsigned int clk_cfg, lin_ctrl;
  141. clk_cfg = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG);
  142. lin_ctrl = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXLINCTRLDATA);
  143. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  144. case SND_SOC_DAIFMT_I2S:
  145. clk_cfg |= EP93XX_I2S_CLKCFG_REL;
  146. lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
  147. break;
  148. case SND_SOC_DAIFMT_LEFT_J:
  149. clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
  150. lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
  151. break;
  152. case SND_SOC_DAIFMT_RIGHT_J:
  153. clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
  154. lin_ctrl |= EP93XX_I2S_LINCTRLDATA_R_JUST;
  155. break;
  156. default:
  157. return -EINVAL;
  158. }
  159. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  160. case SND_SOC_DAIFMT_CBS_CFS:
  161. /* CPU is master */
  162. clk_cfg |= EP93XX_I2S_CLKCFG_MASTER;
  163. break;
  164. case SND_SOC_DAIFMT_CBM_CFM:
  165. /* Codec is master */
  166. clk_cfg &= ~EP93XX_I2S_CLKCFG_MASTER;
  167. break;
  168. default:
  169. return -EINVAL;
  170. }
  171. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  172. case SND_SOC_DAIFMT_NB_NF:
  173. /* Negative bit clock, lrclk low on left word */
  174. clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL);
  175. break;
  176. case SND_SOC_DAIFMT_NB_IF:
  177. /* Negative bit clock, lrclk low on right word */
  178. clk_cfg &= ~EP93XX_I2S_CLKCFG_CKP;
  179. clk_cfg |= EP93XX_I2S_CLKCFG_REL;
  180. break;
  181. case SND_SOC_DAIFMT_IB_NF:
  182. /* Positive bit clock, lrclk low on left word */
  183. clk_cfg |= EP93XX_I2S_CLKCFG_CKP;
  184. clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
  185. break;
  186. case SND_SOC_DAIFMT_IB_IF:
  187. /* Positive bit clock, lrclk low on right word */
  188. clk_cfg |= EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL;
  189. break;
  190. }
  191. /* Write new register values */
  192. ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg);
  193. ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg);
  194. ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, lin_ctrl);
  195. ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, lin_ctrl);
  196. return 0;
  197. }
  198. static int ep93xx_i2s_hw_params(struct snd_pcm_substream *substream,
  199. struct snd_pcm_hw_params *params,
  200. struct snd_soc_dai *dai)
  201. {
  202. struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
  203. unsigned word_len, div, sdiv, lrdiv;
  204. int found = 0, err;
  205. switch (params_format(params)) {
  206. case SNDRV_PCM_FORMAT_S16_LE:
  207. word_len = EP93XX_I2S_WRDLEN_16;
  208. break;
  209. case SNDRV_PCM_FORMAT_S24_LE:
  210. word_len = EP93XX_I2S_WRDLEN_24;
  211. break;
  212. case SNDRV_PCM_FORMAT_S32_LE:
  213. word_len = EP93XX_I2S_WRDLEN_32;
  214. break;
  215. default:
  216. return -EINVAL;
  217. }
  218. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  219. ep93xx_i2s_write_reg(info, EP93XX_I2S_TXWRDLEN, word_len);
  220. else
  221. ep93xx_i2s_write_reg(info, EP93XX_I2S_RXWRDLEN, word_len);
  222. /*
  223. * Calculate the sdiv (bit clock) and lrdiv (left/right clock) values.
  224. * If the lrclk is pulse length is larger than the word size, then the
  225. * bit clock will be gated for the unused bits.
  226. */
  227. div = (clk_get_rate(info->mclk) / params_rate(params)) *
  228. params_channels(params);
  229. for (sdiv = 2; sdiv <= 4; sdiv += 2)
  230. for (lrdiv = 32; lrdiv <= 128; lrdiv <<= 1)
  231. if (sdiv * lrdiv == div) {
  232. found = 1;
  233. goto out;
  234. }
  235. out:
  236. if (!found)
  237. return -EINVAL;
  238. err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv);
  239. if (err)
  240. return err;
  241. err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv);
  242. if (err)
  243. return err;
  244. ep93xx_i2s_enable(info, substream->stream);
  245. return 0;
  246. }
  247. static int ep93xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
  248. unsigned int freq, int dir)
  249. {
  250. struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
  251. if (dir == SND_SOC_CLOCK_IN || clk_id != 0)
  252. return -EINVAL;
  253. return clk_set_rate(info->mclk, freq);
  254. }
  255. #ifdef CONFIG_PM
  256. static int ep93xx_i2s_suspend(struct snd_soc_dai *dai)
  257. {
  258. struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
  259. if (!dai->active)
  260. return;
  261. ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_PLAYBACK);
  262. ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_CAPTURE);
  263. }
  264. static int ep93xx_i2s_resume(struct snd_soc_dai *dai)
  265. {
  266. struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
  267. if (!dai->active)
  268. return;
  269. ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_PLAYBACK);
  270. ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_CAPTURE);
  271. }
  272. #else
  273. #define ep93xx_i2s_suspend NULL
  274. #define ep93xx_i2s_resume NULL
  275. #endif
  276. static struct snd_soc_dai_ops ep93xx_i2s_dai_ops = {
  277. .startup = ep93xx_i2s_startup,
  278. .shutdown = ep93xx_i2s_shutdown,
  279. .hw_params = ep93xx_i2s_hw_params,
  280. .set_sysclk = ep93xx_i2s_set_sysclk,
  281. .set_fmt = ep93xx_i2s_set_dai_fmt,
  282. };
  283. #define EP93XX_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
  284. SNDRV_PCM_FMTBIT_S24_LE | \
  285. SNDRV_PCM_FMTBIT_S32_LE)
  286. static struct snd_soc_dai_driver ep93xx_i2s_dai = {
  287. .symmetric_rates= 1,
  288. .suspend = ep93xx_i2s_suspend,
  289. .resume = ep93xx_i2s_resume,
  290. .playback = {
  291. .channels_min = 2,
  292. .channels_max = 2,
  293. .rates = SNDRV_PCM_RATE_8000_48000,
  294. .formats = EP93XX_I2S_FORMATS,
  295. },
  296. .capture = {
  297. .channels_min = 2,
  298. .channels_max = 2,
  299. .rates = SNDRV_PCM_RATE_8000_48000,
  300. .formats = EP93XX_I2S_FORMATS,
  301. },
  302. .ops = &ep93xx_i2s_dai_ops,
  303. };
  304. static int ep93xx_i2s_probe(struct platform_device *pdev)
  305. {
  306. struct ep93xx_i2s_info *info;
  307. struct resource *res;
  308. int err;
  309. info = kzalloc(sizeof(struct ep93xx_i2s_info), GFP_KERNEL);
  310. if (!info) {
  311. err = -ENOMEM;
  312. goto fail;
  313. }
  314. dev_set_drvdata(&pdev->dev, info);
  315. info->dma_params = ep93xx_i2s_dma_params;
  316. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  317. if (!res) {
  318. err = -ENODEV;
  319. goto fail;
  320. }
  321. info->mem = request_mem_region(res->start, resource_size(res),
  322. pdev->name);
  323. if (!info->mem) {
  324. err = -EBUSY;
  325. goto fail;
  326. }
  327. info->regs = ioremap(info->mem->start, resource_size(info->mem));
  328. if (!info->regs) {
  329. err = -ENXIO;
  330. goto fail_release_mem;
  331. }
  332. info->mclk = clk_get(&pdev->dev, "mclk");
  333. if (IS_ERR(info->mclk)) {
  334. err = PTR_ERR(info->mclk);
  335. goto fail_unmap_mem;
  336. }
  337. info->sclk = clk_get(&pdev->dev, "sclk");
  338. if (IS_ERR(info->sclk)) {
  339. err = PTR_ERR(info->sclk);
  340. goto fail_put_mclk;
  341. }
  342. info->lrclk = clk_get(&pdev->dev, "lrclk");
  343. if (IS_ERR(info->lrclk)) {
  344. err = PTR_ERR(info->lrclk);
  345. goto fail_put_sclk;
  346. }
  347. err = snd_soc_register_dai(&pdev->dev, &ep93xx_i2s_dai);
  348. if (err)
  349. goto fail_put_lrclk;
  350. return 0;
  351. fail_put_lrclk:
  352. clk_put(info->lrclk);
  353. fail_put_sclk:
  354. clk_put(info->sclk);
  355. fail_put_mclk:
  356. clk_put(info->mclk);
  357. fail_unmap_mem:
  358. iounmap(info->regs);
  359. fail_release_mem:
  360. release_mem_region(info->mem->start, resource_size(info->mem));
  361. kfree(info);
  362. fail:
  363. return err;
  364. }
  365. static int __devexit ep93xx_i2s_remove(struct platform_device *pdev)
  366. {
  367. struct ep93xx_i2s_info *info = dev_get_drvdata(&pdev->dev);
  368. snd_soc_unregister_dai(&pdev->dev);
  369. clk_put(info->lrclk);
  370. clk_put(info->sclk);
  371. clk_put(info->mclk);
  372. iounmap(info->regs);
  373. release_mem_region(info->mem->start, resource_size(info->mem));
  374. kfree(info);
  375. return 0;
  376. }
  377. static struct platform_driver ep93xx_i2s_driver = {
  378. .probe = ep93xx_i2s_probe,
  379. .remove = __devexit_p(ep93xx_i2s_remove),
  380. .driver = {
  381. .name = "ep93xx-i2s",
  382. .owner = THIS_MODULE,
  383. },
  384. };
  385. static int __init ep93xx_i2s_init(void)
  386. {
  387. return platform_driver_register(&ep93xx_i2s_driver);
  388. }
  389. static void __exit ep93xx_i2s_exit(void)
  390. {
  391. platform_driver_unregister(&ep93xx_i2s_driver);
  392. }
  393. module_init(ep93xx_i2s_init);
  394. module_exit(ep93xx_i2s_exit);
  395. MODULE_ALIAS("platform:ep93xx-i2s");
  396. MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com>");
  397. MODULE_DESCRIPTION("EP93XX I2S driver");
  398. MODULE_LICENSE("GPL");