wm8804.c 19 KB

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  1. /*
  2. * wm8804.c -- WM8804 S/PDIF transceiver driver
  3. *
  4. * Copyright 2010 Wolfson Microelectronics plc
  5. *
  6. * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/init.h>
  15. #include <linux/delay.h>
  16. #include <linux/pm.h>
  17. #include <linux/i2c.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/regulator/consumer.h>
  20. #include <linux/slab.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/soc.h>
  25. #include <sound/soc-dapm.h>
  26. #include <sound/initval.h>
  27. #include <sound/tlv.h>
  28. #include "wm8804.h"
  29. #define WM8804_NUM_SUPPLIES 2
  30. static const char *wm8804_supply_names[WM8804_NUM_SUPPLIES] = {
  31. "PVDD",
  32. "DVDD"
  33. };
  34. static const u8 wm8804_reg_defs[] = {
  35. 0x05, /* R0 - RST/DEVID1 */
  36. 0x88, /* R1 - DEVID2 */
  37. 0x04, /* R2 - DEVREV */
  38. 0x21, /* R3 - PLL1 */
  39. 0xFD, /* R4 - PLL2 */
  40. 0x36, /* R5 - PLL3 */
  41. 0x07, /* R6 - PLL4 */
  42. 0x16, /* R7 - PLL5 */
  43. 0x18, /* R8 - PLL6 */
  44. 0xFF, /* R9 - SPDMODE */
  45. 0x00, /* R10 - INTMASK */
  46. 0x00, /* R11 - INTSTAT */
  47. 0x00, /* R12 - SPDSTAT */
  48. 0x00, /* R13 - RXCHAN1 */
  49. 0x00, /* R14 - RXCHAN2 */
  50. 0x00, /* R15 - RXCHAN3 */
  51. 0x00, /* R16 - RXCHAN4 */
  52. 0x00, /* R17 - RXCHAN5 */
  53. 0x00, /* R18 - SPDTX1 */
  54. 0x00, /* R19 - SPDTX2 */
  55. 0x00, /* R20 - SPDTX3 */
  56. 0x71, /* R21 - SPDTX4 */
  57. 0x0B, /* R22 - SPDTX5 */
  58. 0x70, /* R23 - GPO0 */
  59. 0x57, /* R24 - GPO1 */
  60. 0x00, /* R25 */
  61. 0x42, /* R26 - GPO2 */
  62. 0x06, /* R27 - AIFTX */
  63. 0x06, /* R28 - AIFRX */
  64. 0x80, /* R29 - SPDRX1 */
  65. 0x07, /* R30 - PWRDN */
  66. };
  67. struct wm8804_priv {
  68. enum snd_soc_control_type control_type;
  69. struct regulator_bulk_data supplies[WM8804_NUM_SUPPLIES];
  70. struct notifier_block disable_nb[WM8804_NUM_SUPPLIES];
  71. struct snd_soc_codec *codec;
  72. };
  73. static int txsrc_get(struct snd_kcontrol *kcontrol,
  74. struct snd_ctl_elem_value *ucontrol);
  75. static int txsrc_put(struct snd_kcontrol *kcontrol,
  76. struct snd_ctl_elem_value *ucontrol);
  77. /*
  78. * We can't use the same notifier block for more than one supply and
  79. * there's no way I can see to get from a callback to the caller
  80. * except container_of().
  81. */
  82. #define WM8804_REGULATOR_EVENT(n) \
  83. static int wm8804_regulator_event_##n(struct notifier_block *nb, \
  84. unsigned long event, void *data) \
  85. { \
  86. struct wm8804_priv *wm8804 = container_of(nb, struct wm8804_priv, \
  87. disable_nb[n]); \
  88. if (event & REGULATOR_EVENT_DISABLE) { \
  89. wm8804->codec->cache_sync = 1; \
  90. } \
  91. return 0; \
  92. }
  93. WM8804_REGULATOR_EVENT(0)
  94. WM8804_REGULATOR_EVENT(1)
  95. static const char *txsrc_text[] = { "S/PDIF RX", "AIF" };
  96. static const SOC_ENUM_SINGLE_EXT_DECL(txsrc, txsrc_text);
  97. static const struct snd_kcontrol_new wm8804_snd_controls[] = {
  98. SOC_ENUM_EXT("Input Source", txsrc, txsrc_get, txsrc_put),
  99. SOC_SINGLE("TX Playback Switch", WM8804_PWRDN, 2, 1, 1),
  100. SOC_SINGLE("AIF Playback Switch", WM8804_PWRDN, 4, 1, 1)
  101. };
  102. static int txsrc_get(struct snd_kcontrol *kcontrol,
  103. struct snd_ctl_elem_value *ucontrol)
  104. {
  105. struct snd_soc_codec *codec;
  106. unsigned int src;
  107. codec = snd_kcontrol_chip(kcontrol);
  108. src = snd_soc_read(codec, WM8804_SPDTX4);
  109. if (src & 0x40)
  110. ucontrol->value.integer.value[0] = 1;
  111. else
  112. ucontrol->value.integer.value[0] = 0;
  113. return 0;
  114. }
  115. static int txsrc_put(struct snd_kcontrol *kcontrol,
  116. struct snd_ctl_elem_value *ucontrol)
  117. {
  118. struct snd_soc_codec *codec;
  119. unsigned int src, txpwr;
  120. codec = snd_kcontrol_chip(kcontrol);
  121. if (ucontrol->value.integer.value[0] != 0
  122. && ucontrol->value.integer.value[0] != 1)
  123. return -EINVAL;
  124. src = snd_soc_read(codec, WM8804_SPDTX4);
  125. switch ((src & 0x40) >> 6) {
  126. case 0:
  127. if (!ucontrol->value.integer.value[0])
  128. return 0;
  129. break;
  130. case 1:
  131. if (ucontrol->value.integer.value[1])
  132. return 0;
  133. break;
  134. }
  135. /* save the current power state of the transmitter */
  136. txpwr = snd_soc_read(codec, WM8804_PWRDN) & 0x4;
  137. /* power down the transmitter */
  138. snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x4);
  139. /* set the tx source */
  140. snd_soc_update_bits(codec, WM8804_SPDTX4, 0x40,
  141. ucontrol->value.integer.value[0] << 6);
  142. if (ucontrol->value.integer.value[0]) {
  143. /* power down the receiver */
  144. snd_soc_update_bits(codec, WM8804_PWRDN, 0x2, 0x2);
  145. /* power up the AIF */
  146. snd_soc_update_bits(codec, WM8804_PWRDN, 0x10, 0);
  147. } else {
  148. /* don't power down the AIF -- may be used as an output */
  149. /* power up the receiver */
  150. snd_soc_update_bits(codec, WM8804_PWRDN, 0x2, 0);
  151. }
  152. /* restore the transmitter's configuration */
  153. snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, txpwr);
  154. return 0;
  155. }
  156. static int wm8804_volatile(unsigned int reg)
  157. {
  158. switch (reg) {
  159. case WM8804_RST_DEVID1:
  160. case WM8804_DEVID2:
  161. case WM8804_DEVREV:
  162. case WM8804_INTSTAT:
  163. case WM8804_SPDSTAT:
  164. case WM8804_RXCHAN1:
  165. case WM8804_RXCHAN2:
  166. case WM8804_RXCHAN3:
  167. case WM8804_RXCHAN4:
  168. case WM8804_RXCHAN5:
  169. return 1;
  170. default:
  171. break;
  172. }
  173. return 0;
  174. }
  175. static int wm8804_reset(struct snd_soc_codec *codec)
  176. {
  177. return snd_soc_write(codec, WM8804_RST_DEVID1, 0x0);
  178. }
  179. static int wm8804_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  180. {
  181. struct snd_soc_codec *codec;
  182. u16 format, master, bcp, lrp;
  183. codec = dai->codec;
  184. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  185. case SND_SOC_DAIFMT_I2S:
  186. format = 0x2;
  187. break;
  188. case SND_SOC_DAIFMT_RIGHT_J:
  189. format = 0x0;
  190. break;
  191. case SND_SOC_DAIFMT_LEFT_J:
  192. format = 0x1;
  193. break;
  194. case SND_SOC_DAIFMT_DSP_A:
  195. case SND_SOC_DAIFMT_DSP_B:
  196. format = 0x3;
  197. break;
  198. default:
  199. dev_err(dai->dev, "Unknown dai format\n");
  200. return -EINVAL;
  201. }
  202. /* set data format */
  203. snd_soc_update_bits(codec, WM8804_AIFTX, 0x3, format);
  204. snd_soc_update_bits(codec, WM8804_AIFRX, 0x3, format);
  205. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  206. case SND_SOC_DAIFMT_CBM_CFM:
  207. master = 1;
  208. break;
  209. case SND_SOC_DAIFMT_CBS_CFS:
  210. master = 0;
  211. break;
  212. default:
  213. dev_err(dai->dev, "Unknown master/slave configuration\n");
  214. return -EINVAL;
  215. }
  216. /* set master/slave mode */
  217. snd_soc_update_bits(codec, WM8804_AIFRX, 0x40, master << 6);
  218. bcp = lrp = 0;
  219. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  220. case SND_SOC_DAIFMT_NB_NF:
  221. break;
  222. case SND_SOC_DAIFMT_IB_IF:
  223. bcp = lrp = 1;
  224. break;
  225. case SND_SOC_DAIFMT_IB_NF:
  226. bcp = 1;
  227. break;
  228. case SND_SOC_DAIFMT_NB_IF:
  229. lrp = 1;
  230. break;
  231. default:
  232. dev_err(dai->dev, "Unknown polarity configuration\n");
  233. return -EINVAL;
  234. }
  235. /* set frame inversion */
  236. snd_soc_update_bits(codec, WM8804_AIFTX, 0x10 | 0x20,
  237. (bcp << 4) | (lrp << 5));
  238. snd_soc_update_bits(codec, WM8804_AIFRX, 0x10 | 0x20,
  239. (bcp << 4) | (lrp << 5));
  240. return 0;
  241. }
  242. static int wm8804_hw_params(struct snd_pcm_substream *substream,
  243. struct snd_pcm_hw_params *params,
  244. struct snd_soc_dai *dai)
  245. {
  246. struct snd_soc_codec *codec;
  247. u16 blen;
  248. codec = dai->codec;
  249. switch (params_format(params)) {
  250. case SNDRV_PCM_FORMAT_S16_LE:
  251. blen = 0x0;
  252. break;
  253. case SNDRV_PCM_FORMAT_S20_3LE:
  254. blen = 0x1;
  255. break;
  256. case SNDRV_PCM_FORMAT_S24_LE:
  257. blen = 0x2;
  258. break;
  259. default:
  260. dev_err(dai->dev, "Unsupported word length: %u\n",
  261. params_format(params));
  262. return -EINVAL;
  263. }
  264. /* set word length */
  265. snd_soc_update_bits(codec, WM8804_AIFTX, 0xc, blen << 2);
  266. snd_soc_update_bits(codec, WM8804_AIFRX, 0xc, blen << 2);
  267. return 0;
  268. }
  269. struct pll_div {
  270. u32 prescale:1;
  271. u32 mclkdiv:1;
  272. u32 freqmode:2;
  273. u32 n:4;
  274. u32 k:22;
  275. };
  276. /* PLL rate to output rate divisions */
  277. static struct {
  278. unsigned int div;
  279. unsigned int freqmode;
  280. unsigned int mclkdiv;
  281. } post_table[] = {
  282. { 2, 0, 0 },
  283. { 4, 0, 1 },
  284. { 4, 1, 0 },
  285. { 8, 1, 1 },
  286. { 8, 2, 0 },
  287. { 16, 2, 1 },
  288. { 12, 3, 0 },
  289. { 24, 3, 1 }
  290. };
  291. #define FIXED_PLL_SIZE ((1ULL << 22) * 10)
  292. static int pll_factors(struct pll_div *pll_div, unsigned int target,
  293. unsigned int source)
  294. {
  295. u64 Kpart;
  296. unsigned long int K, Ndiv, Nmod, tmp;
  297. int i;
  298. /*
  299. * Scale the output frequency up; the PLL should run in the
  300. * region of 90-100MHz.
  301. */
  302. for (i = 0; i < ARRAY_SIZE(post_table); i++) {
  303. tmp = target * post_table[i].div;
  304. if (tmp >= 90000000 && tmp <= 100000000) {
  305. pll_div->freqmode = post_table[i].freqmode;
  306. pll_div->mclkdiv = post_table[i].mclkdiv;
  307. target *= post_table[i].div;
  308. break;
  309. }
  310. }
  311. if (i == ARRAY_SIZE(post_table)) {
  312. pr_err("%s: Unable to scale output frequency: %uHz\n",
  313. __func__, target);
  314. return -EINVAL;
  315. }
  316. pll_div->prescale = 0;
  317. Ndiv = target / source;
  318. if (Ndiv < 5) {
  319. source >>= 1;
  320. pll_div->prescale = 1;
  321. Ndiv = target / source;
  322. }
  323. if (Ndiv < 5 || Ndiv > 13) {
  324. pr_err("%s: WM8804 N value is not within the recommended range: %lu\n",
  325. __func__, Ndiv);
  326. return -EINVAL;
  327. }
  328. pll_div->n = Ndiv;
  329. Nmod = target % source;
  330. Kpart = FIXED_PLL_SIZE * (u64)Nmod;
  331. do_div(Kpart, source);
  332. K = Kpart & 0xffffffff;
  333. if ((K % 10) >= 5)
  334. K += 5;
  335. K /= 10;
  336. pll_div->k = K;
  337. return 0;
  338. }
  339. static int wm8804_set_pll(struct snd_soc_dai *dai, int pll_id,
  340. int source, unsigned int freq_in,
  341. unsigned int freq_out)
  342. {
  343. struct snd_soc_codec *codec;
  344. codec = dai->codec;
  345. if (!freq_in || !freq_out) {
  346. /* disable the PLL */
  347. snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0x1);
  348. return 0;
  349. } else {
  350. int ret;
  351. struct pll_div pll_div;
  352. ret = pll_factors(&pll_div, freq_out, freq_in);
  353. if (ret)
  354. return ret;
  355. /* power down the PLL before reprogramming it */
  356. snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0x1);
  357. if (!freq_in || !freq_out)
  358. return 0;
  359. /* set PLLN and PRESCALE */
  360. snd_soc_update_bits(codec, WM8804_PLL4, 0xf | 0x10,
  361. pll_div.n | (pll_div.prescale << 4));
  362. /* set mclkdiv and freqmode */
  363. snd_soc_update_bits(codec, WM8804_PLL5, 0x3 | 0x8,
  364. pll_div.freqmode | (pll_div.mclkdiv << 3));
  365. /* set PLLK */
  366. snd_soc_write(codec, WM8804_PLL1, pll_div.k & 0xff);
  367. snd_soc_write(codec, WM8804_PLL2, (pll_div.k >> 8) & 0xff);
  368. snd_soc_write(codec, WM8804_PLL3, pll_div.k >> 16);
  369. /* power up the PLL */
  370. snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0);
  371. }
  372. return 0;
  373. }
  374. static int wm8804_set_sysclk(struct snd_soc_dai *dai,
  375. int clk_id, unsigned int freq, int dir)
  376. {
  377. struct snd_soc_codec *codec;
  378. codec = dai->codec;
  379. switch (clk_id) {
  380. case WM8804_TX_CLKSRC_MCLK:
  381. if ((freq >= 10000000 && freq <= 14400000)
  382. || (freq >= 16280000 && freq <= 27000000))
  383. snd_soc_update_bits(codec, WM8804_PLL6, 0x80, 0x80);
  384. else {
  385. dev_err(dai->dev, "OSCCLOCK is not within the "
  386. "recommended range: %uHz\n", freq);
  387. return -EINVAL;
  388. }
  389. break;
  390. case WM8804_TX_CLKSRC_PLL:
  391. snd_soc_update_bits(codec, WM8804_PLL6, 0x80, 0);
  392. break;
  393. case WM8804_CLKOUT_SRC_CLK1:
  394. snd_soc_update_bits(codec, WM8804_PLL6, 0x8, 0);
  395. break;
  396. case WM8804_CLKOUT_SRC_OSCCLK:
  397. snd_soc_update_bits(codec, WM8804_PLL6, 0x8, 0x8);
  398. break;
  399. default:
  400. dev_err(dai->dev, "Unknown clock source: %d\n", clk_id);
  401. return -EINVAL;
  402. }
  403. return 0;
  404. }
  405. static int wm8804_set_clkdiv(struct snd_soc_dai *dai,
  406. int div_id, int div)
  407. {
  408. struct snd_soc_codec *codec;
  409. codec = dai->codec;
  410. switch (div_id) {
  411. case WM8804_CLKOUT_DIV:
  412. snd_soc_update_bits(codec, WM8804_PLL5, 0x30,
  413. (div & 0x3) << 4);
  414. break;
  415. default:
  416. dev_err(dai->dev, "Unknown clock divider: %d\n", div_id);
  417. return -EINVAL;
  418. }
  419. return 0;
  420. }
  421. static void wm8804_sync_cache(struct snd_soc_codec *codec)
  422. {
  423. short i;
  424. u8 *cache;
  425. if (!codec->cache_sync)
  426. return;
  427. codec->cache_only = 0;
  428. cache = codec->reg_cache;
  429. for (i = 0; i < codec->driver->reg_cache_size; i++) {
  430. if (i == WM8804_RST_DEVID1 || cache[i] == wm8804_reg_defs[i])
  431. continue;
  432. snd_soc_write(codec, i, cache[i]);
  433. }
  434. codec->cache_sync = 0;
  435. }
  436. static int wm8804_set_bias_level(struct snd_soc_codec *codec,
  437. enum snd_soc_bias_level level)
  438. {
  439. int ret;
  440. struct wm8804_priv *wm8804;
  441. wm8804 = snd_soc_codec_get_drvdata(codec);
  442. switch (level) {
  443. case SND_SOC_BIAS_ON:
  444. break;
  445. case SND_SOC_BIAS_PREPARE:
  446. /* power up the OSC and the PLL */
  447. snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0);
  448. break;
  449. case SND_SOC_BIAS_STANDBY:
  450. if (codec->bias_level == SND_SOC_BIAS_OFF) {
  451. ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies),
  452. wm8804->supplies);
  453. if (ret) {
  454. dev_err(codec->dev,
  455. "Failed to enable supplies: %d\n",
  456. ret);
  457. return ret;
  458. }
  459. wm8804_sync_cache(codec);
  460. }
  461. /* power down the OSC and the PLL */
  462. snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0x9);
  463. break;
  464. case SND_SOC_BIAS_OFF:
  465. /* power down the OSC and the PLL */
  466. snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0x9);
  467. regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies),
  468. wm8804->supplies);
  469. break;
  470. }
  471. codec->bias_level = level;
  472. return 0;
  473. }
  474. #ifdef CONFIG_PM
  475. static int wm8804_suspend(struct snd_soc_codec *codec, pm_message_t state)
  476. {
  477. wm8804_set_bias_level(codec, SND_SOC_BIAS_OFF);
  478. return 0;
  479. }
  480. static int wm8804_resume(struct snd_soc_codec *codec)
  481. {
  482. wm8804_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  483. return 0;
  484. }
  485. #else
  486. #define wm8804_suspend NULL
  487. #define wm8804_resume NULL
  488. #endif
  489. static int wm8804_remove(struct snd_soc_codec *codec)
  490. {
  491. struct wm8804_priv *wm8804;
  492. int i;
  493. wm8804 = snd_soc_codec_get_drvdata(codec);
  494. wm8804_set_bias_level(codec, SND_SOC_BIAS_OFF);
  495. for (i = 0; i < ARRAY_SIZE(wm8804->supplies); ++i)
  496. regulator_unregister_notifier(wm8804->supplies[i].consumer,
  497. &wm8804->disable_nb[i]);
  498. regulator_bulk_free(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
  499. return 0;
  500. }
  501. static int wm8804_probe(struct snd_soc_codec *codec)
  502. {
  503. struct wm8804_priv *wm8804;
  504. int i, id1, id2, ret;
  505. wm8804 = snd_soc_codec_get_drvdata(codec);
  506. wm8804->codec = codec;
  507. codec->idle_bias_off = 1;
  508. ret = snd_soc_codec_set_cache_io(codec, 8, 8, wm8804->control_type);
  509. if (ret < 0) {
  510. dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret);
  511. return ret;
  512. }
  513. for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++)
  514. wm8804->supplies[i].supply = wm8804_supply_names[i];
  515. ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8804->supplies),
  516. wm8804->supplies);
  517. if (ret) {
  518. dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
  519. return ret;
  520. }
  521. wm8804->disable_nb[0].notifier_call = wm8804_regulator_event_0;
  522. wm8804->disable_nb[1].notifier_call = wm8804_regulator_event_1;
  523. /* This should really be moved into the regulator core */
  524. for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++) {
  525. ret = regulator_register_notifier(wm8804->supplies[i].consumer,
  526. &wm8804->disable_nb[i]);
  527. if (ret != 0) {
  528. dev_err(codec->dev,
  529. "Failed to register regulator notifier: %d\n",
  530. ret);
  531. }
  532. }
  533. ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies),
  534. wm8804->supplies);
  535. if (ret) {
  536. dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
  537. goto err_reg_get;
  538. }
  539. id1 = snd_soc_read(codec, WM8804_RST_DEVID1);
  540. if (id1 < 0) {
  541. dev_err(codec->dev, "Failed to read device ID: %d\n", id1);
  542. ret = id1;
  543. goto err_reg_enable;
  544. }
  545. id2 = snd_soc_read(codec, WM8804_DEVID2);
  546. if (id2 < 0) {
  547. dev_err(codec->dev, "Failed to read device ID: %d\n", id2);
  548. ret = id2;
  549. goto err_reg_enable;
  550. }
  551. id2 = (id2 << 8) | id1;
  552. if (id2 != ((wm8804_reg_defs[WM8804_DEVID2] << 8)
  553. | wm8804_reg_defs[WM8804_RST_DEVID1])) {
  554. dev_err(codec->dev, "Invalid device ID: %#x\n", id2);
  555. ret = -EINVAL;
  556. goto err_reg_enable;
  557. }
  558. ret = snd_soc_read(codec, WM8804_DEVREV);
  559. if (ret < 0) {
  560. dev_err(codec->dev, "Failed to read device revision: %d\n",
  561. ret);
  562. goto err_reg_enable;
  563. }
  564. dev_info(codec->dev, "revision %c\n", ret + 'A');
  565. ret = wm8804_reset(codec);
  566. if (ret < 0) {
  567. dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
  568. goto err_reg_enable;
  569. }
  570. wm8804_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  571. snd_soc_add_controls(codec, wm8804_snd_controls,
  572. ARRAY_SIZE(wm8804_snd_controls));
  573. return 0;
  574. err_reg_enable:
  575. regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
  576. err_reg_get:
  577. regulator_bulk_free(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
  578. return ret;
  579. }
  580. static struct snd_soc_dai_ops wm8804_dai_ops = {
  581. .hw_params = wm8804_hw_params,
  582. .set_fmt = wm8804_set_fmt,
  583. .set_sysclk = wm8804_set_sysclk,
  584. .set_clkdiv = wm8804_set_clkdiv,
  585. .set_pll = wm8804_set_pll
  586. };
  587. #define WM8804_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  588. SNDRV_PCM_FMTBIT_S24_LE)
  589. static struct snd_soc_dai_driver wm8804_dai = {
  590. .name = "wm8804-spdif",
  591. .playback = {
  592. .stream_name = "Playback",
  593. .channels_min = 2,
  594. .channels_max = 2,
  595. .rates = SNDRV_PCM_RATE_8000_192000,
  596. .formats = WM8804_FORMATS,
  597. },
  598. .capture = {
  599. .stream_name = "Capture",
  600. .channels_min = 2,
  601. .channels_max = 2,
  602. .rates = SNDRV_PCM_RATE_8000_192000,
  603. .formats = WM8804_FORMATS,
  604. },
  605. .ops = &wm8804_dai_ops,
  606. .symmetric_rates = 1
  607. };
  608. static struct snd_soc_codec_driver soc_codec_dev_wm8804 = {
  609. .probe = wm8804_probe,
  610. .remove = wm8804_remove,
  611. .suspend = wm8804_suspend,
  612. .resume = wm8804_resume,
  613. .set_bias_level = wm8804_set_bias_level,
  614. .reg_cache_size = ARRAY_SIZE(wm8804_reg_defs),
  615. .reg_word_size = sizeof(u8),
  616. .reg_cache_default = wm8804_reg_defs,
  617. .volatile_register = wm8804_volatile
  618. };
  619. #if defined(CONFIG_SPI_MASTER)
  620. static int __devinit wm8804_spi_probe(struct spi_device *spi)
  621. {
  622. struct wm8804_priv *wm8804;
  623. int ret;
  624. wm8804 = kzalloc(sizeof *wm8804, GFP_KERNEL);
  625. if (!wm8804)
  626. return -ENOMEM;
  627. wm8804->control_type = SND_SOC_SPI;
  628. spi_set_drvdata(spi, wm8804);
  629. ret = snd_soc_register_codec(&spi->dev,
  630. &soc_codec_dev_wm8804, &wm8804_dai, 1);
  631. if (ret < 0)
  632. kfree(wm8804);
  633. return ret;
  634. }
  635. static int __devexit wm8804_spi_remove(struct spi_device *spi)
  636. {
  637. snd_soc_unregister_codec(&spi->dev);
  638. kfree(spi_get_drvdata(spi));
  639. return 0;
  640. }
  641. static struct spi_driver wm8804_spi_driver = {
  642. .driver = {
  643. .name = "wm8804",
  644. .owner = THIS_MODULE,
  645. },
  646. .probe = wm8804_spi_probe,
  647. .remove = __devexit_p(wm8804_spi_remove)
  648. };
  649. #endif
  650. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  651. static __devinit int wm8804_i2c_probe(struct i2c_client *i2c,
  652. const struct i2c_device_id *id)
  653. {
  654. struct wm8804_priv *wm8804;
  655. int ret;
  656. wm8804 = kzalloc(sizeof *wm8804, GFP_KERNEL);
  657. if (!wm8804)
  658. return -ENOMEM;
  659. wm8804->control_type = SND_SOC_I2C;
  660. i2c_set_clientdata(i2c, wm8804);
  661. ret = snd_soc_register_codec(&i2c->dev,
  662. &soc_codec_dev_wm8804, &wm8804_dai, 1);
  663. if (ret < 0)
  664. kfree(wm8804);
  665. return ret;
  666. }
  667. static __devexit int wm8804_i2c_remove(struct i2c_client *client)
  668. {
  669. snd_soc_unregister_codec(&client->dev);
  670. kfree(i2c_get_clientdata(client));
  671. return 0;
  672. }
  673. static const struct i2c_device_id wm8804_i2c_id[] = {
  674. { "wm8804", 0 },
  675. { }
  676. };
  677. MODULE_DEVICE_TABLE(i2c, wm8804_i2c_id);
  678. static struct i2c_driver wm8804_i2c_driver = {
  679. .driver = {
  680. .name = "wm8804",
  681. .owner = THIS_MODULE,
  682. },
  683. .probe = wm8804_i2c_probe,
  684. .remove = __devexit_p(wm8804_i2c_remove),
  685. .id_table = wm8804_i2c_id
  686. };
  687. #endif
  688. static int __init wm8804_modinit(void)
  689. {
  690. int ret = 0;
  691. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  692. ret = i2c_add_driver(&wm8804_i2c_driver);
  693. if (ret) {
  694. printk(KERN_ERR "Failed to register wm8804 I2C driver: %d\n",
  695. ret);
  696. }
  697. #endif
  698. #if defined(CONFIG_SPI_MASTER)
  699. ret = spi_register_driver(&wm8804_spi_driver);
  700. if (ret != 0) {
  701. printk(KERN_ERR "Failed to register wm8804 SPI driver: %d\n",
  702. ret);
  703. }
  704. #endif
  705. return ret;
  706. }
  707. module_init(wm8804_modinit);
  708. static void __exit wm8804_exit(void)
  709. {
  710. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  711. i2c_del_driver(&wm8804_i2c_driver);
  712. #endif
  713. #if defined(CONFIG_SPI_MASTER)
  714. spi_unregister_driver(&wm8804_spi_driver);
  715. #endif
  716. }
  717. module_exit(wm8804_exit);
  718. MODULE_DESCRIPTION("ASoC WM8804 driver");
  719. MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
  720. MODULE_LICENSE("GPL");