twl4030.c 71 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl.h>
  29. #include <linux/slab.h>
  30. #include <sound/core.h>
  31. #include <sound/pcm.h>
  32. #include <sound/pcm_params.h>
  33. #include <sound/soc.h>
  34. #include <sound/soc-dapm.h>
  35. #include <sound/initval.h>
  36. #include <sound/tlv.h>
  37. /* Register descriptions are here */
  38. #include <linux/mfd/twl4030-codec.h>
  39. /* Shadow register used by the audio driver */
  40. #define TWL4030_REG_SW_SHADOW 0x4A
  41. #define TWL4030_CACHEREGNUM (TWL4030_REG_SW_SHADOW + 1)
  42. /* TWL4030_REG_SW_SHADOW (0x4A) Fields */
  43. #define TWL4030_HFL_EN 0x01
  44. #define TWL4030_HFR_EN 0x02
  45. /*
  46. * twl4030 register cache & default register settings
  47. */
  48. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  49. 0x00, /* this register not used */
  50. 0x00, /* REG_CODEC_MODE (0x1) */
  51. 0x00, /* REG_OPTION (0x2) */
  52. 0x00, /* REG_UNKNOWN (0x3) */
  53. 0x00, /* REG_MICBIAS_CTL (0x4) */
  54. 0x00, /* REG_ANAMICL (0x5) */
  55. 0x00, /* REG_ANAMICR (0x6) */
  56. 0x00, /* REG_AVADC_CTL (0x7) */
  57. 0x00, /* REG_ADCMICSEL (0x8) */
  58. 0x00, /* REG_DIGMIXING (0x9) */
  59. 0x0f, /* REG_ATXL1PGA (0xA) */
  60. 0x0f, /* REG_ATXR1PGA (0xB) */
  61. 0x0f, /* REG_AVTXL2PGA (0xC) */
  62. 0x0f, /* REG_AVTXR2PGA (0xD) */
  63. 0x00, /* REG_AUDIO_IF (0xE) */
  64. 0x00, /* REG_VOICE_IF (0xF) */
  65. 0x3f, /* REG_ARXR1PGA (0x10) */
  66. 0x3f, /* REG_ARXL1PGA (0x11) */
  67. 0x3f, /* REG_ARXR2PGA (0x12) */
  68. 0x3f, /* REG_ARXL2PGA (0x13) */
  69. 0x25, /* REG_VRXPGA (0x14) */
  70. 0x00, /* REG_VSTPGA (0x15) */
  71. 0x00, /* REG_VRX2ARXPGA (0x16) */
  72. 0x00, /* REG_AVDAC_CTL (0x17) */
  73. 0x00, /* REG_ARX2VTXPGA (0x18) */
  74. 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
  75. 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
  76. 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
  77. 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
  78. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  79. 0x00, /* REG_BT_IF (0x1E) */
  80. 0x55, /* REG_BTPGA (0x1F) */
  81. 0x00, /* REG_BTSTPGA (0x20) */
  82. 0x00, /* REG_EAR_CTL (0x21) */
  83. 0x00, /* REG_HS_SEL (0x22) */
  84. 0x00, /* REG_HS_GAIN_SET (0x23) */
  85. 0x00, /* REG_HS_POPN_SET (0x24) */
  86. 0x00, /* REG_PREDL_CTL (0x25) */
  87. 0x00, /* REG_PREDR_CTL (0x26) */
  88. 0x00, /* REG_PRECKL_CTL (0x27) */
  89. 0x00, /* REG_PRECKR_CTL (0x28) */
  90. 0x00, /* REG_HFL_CTL (0x29) */
  91. 0x00, /* REG_HFR_CTL (0x2A) */
  92. 0x05, /* REG_ALC_CTL (0x2B) */
  93. 0x00, /* REG_ALC_SET1 (0x2C) */
  94. 0x00, /* REG_ALC_SET2 (0x2D) */
  95. 0x00, /* REG_BOOST_CTL (0x2E) */
  96. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  97. 0x13, /* REG_DTMF_FREQSEL (0x30) */
  98. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  99. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  100. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  101. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  102. 0x79, /* REG_DTMF_TONOFF (0x35) */
  103. 0x11, /* REG_DTMF_WANONOFF (0x36) */
  104. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  105. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  106. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  107. 0x06, /* REG_APLL_CTL (0x3A) */
  108. 0x00, /* REG_DTMF_CTL (0x3B) */
  109. 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
  110. 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
  111. 0x00, /* REG_MISC_SET_1 (0x3E) */
  112. 0x00, /* REG_PCMBTMUX (0x3F) */
  113. 0x00, /* not used (0x40) */
  114. 0x00, /* not used (0x41) */
  115. 0x00, /* not used (0x42) */
  116. 0x00, /* REG_RX_PATH_SEL (0x43) */
  117. 0x32, /* REG_VDL_APGA_CTL (0x44) */
  118. 0x00, /* REG_VIBRA_CTL (0x45) */
  119. 0x00, /* REG_VIBRA_SET (0x46) */
  120. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  121. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  122. 0x00, /* REG_MISC_SET_2 (0x49) */
  123. 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
  124. };
  125. /* codec private data */
  126. struct twl4030_priv {
  127. struct snd_soc_codec codec;
  128. unsigned int codec_powered;
  129. /* reference counts of AIF/APLL users */
  130. unsigned int apll_enabled;
  131. struct snd_pcm_substream *master_substream;
  132. struct snd_pcm_substream *slave_substream;
  133. unsigned int configured;
  134. unsigned int rate;
  135. unsigned int sample_bits;
  136. unsigned int channels;
  137. unsigned int sysclk;
  138. /* Output (with associated amp) states */
  139. u8 hsl_enabled, hsr_enabled;
  140. u8 earpiece_enabled;
  141. u8 predrivel_enabled, predriver_enabled;
  142. u8 carkitl_enabled, carkitr_enabled;
  143. /* Delay needed after enabling the digimic interface */
  144. unsigned int digimic_delay;
  145. };
  146. /*
  147. * read twl4030 register cache
  148. */
  149. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  150. unsigned int reg)
  151. {
  152. u8 *cache = codec->reg_cache;
  153. if (reg >= TWL4030_CACHEREGNUM)
  154. return -EIO;
  155. return cache[reg];
  156. }
  157. /*
  158. * write twl4030 register cache
  159. */
  160. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  161. u8 reg, u8 value)
  162. {
  163. u8 *cache = codec->reg_cache;
  164. if (reg >= TWL4030_CACHEREGNUM)
  165. return;
  166. cache[reg] = value;
  167. }
  168. /*
  169. * write to the twl4030 register space
  170. */
  171. static int twl4030_write(struct snd_soc_codec *codec,
  172. unsigned int reg, unsigned int value)
  173. {
  174. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  175. int write_to_reg = 0;
  176. twl4030_write_reg_cache(codec, reg, value);
  177. if (likely(reg < TWL4030_REG_SW_SHADOW)) {
  178. /* Decide if the given register can be written */
  179. switch (reg) {
  180. case TWL4030_REG_EAR_CTL:
  181. if (twl4030->earpiece_enabled)
  182. write_to_reg = 1;
  183. break;
  184. case TWL4030_REG_PREDL_CTL:
  185. if (twl4030->predrivel_enabled)
  186. write_to_reg = 1;
  187. break;
  188. case TWL4030_REG_PREDR_CTL:
  189. if (twl4030->predriver_enabled)
  190. write_to_reg = 1;
  191. break;
  192. case TWL4030_REG_PRECKL_CTL:
  193. if (twl4030->carkitl_enabled)
  194. write_to_reg = 1;
  195. break;
  196. case TWL4030_REG_PRECKR_CTL:
  197. if (twl4030->carkitr_enabled)
  198. write_to_reg = 1;
  199. break;
  200. case TWL4030_REG_HS_GAIN_SET:
  201. if (twl4030->hsl_enabled || twl4030->hsr_enabled)
  202. write_to_reg = 1;
  203. break;
  204. default:
  205. /* All other register can be written */
  206. write_to_reg = 1;
  207. break;
  208. }
  209. if (write_to_reg)
  210. return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  211. value, reg);
  212. }
  213. return 0;
  214. }
  215. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  216. {
  217. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  218. int mode;
  219. if (enable == twl4030->codec_powered)
  220. return;
  221. if (enable)
  222. mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
  223. else
  224. mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
  225. if (mode >= 0) {
  226. twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
  227. twl4030->codec_powered = enable;
  228. }
  229. /* REVISIT: this delay is present in TI sample drivers */
  230. /* but there seems to be no TRM requirement for it */
  231. udelay(10);
  232. }
  233. static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
  234. {
  235. int i, difference = 0;
  236. u8 val;
  237. dev_dbg(codec->dev, "Checking TWL audio default configuration\n");
  238. for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) {
  239. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i);
  240. if (val != twl4030_reg[i]) {
  241. difference++;
  242. dev_dbg(codec->dev,
  243. "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n",
  244. i, val, twl4030_reg[i]);
  245. }
  246. }
  247. dev_dbg(codec->dev, "Found %d non maching registers. %s\n",
  248. difference, difference ? "Not OK" : "OK");
  249. }
  250. static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
  251. {
  252. int i;
  253. /* set all audio section registers to reasonable defaults */
  254. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  255. if (i != TWL4030_REG_APLL_CTL)
  256. twl4030_write(codec, i, twl4030_reg[i]);
  257. }
  258. static void twl4030_init_chip(struct snd_soc_codec *codec)
  259. {
  260. struct twl4030_codec_audio_data *pdata = dev_get_platdata(codec->dev);
  261. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  262. u8 reg, byte;
  263. int i = 0;
  264. /* Check defaults, if instructed before anything else */
  265. if (pdata && pdata->check_defaults)
  266. twl4030_check_defaults(codec);
  267. /* Reset registers, if no setup data or if instructed to do so */
  268. if (!pdata || (pdata && pdata->reset_registers))
  269. twl4030_reset_registers(codec);
  270. /* Refresh APLL_CTL register from HW */
  271. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  272. TWL4030_REG_APLL_CTL);
  273. twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
  274. /* anti-pop when changing analog gain */
  275. reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  276. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  277. reg | TWL4030_SMOOTH_ANAVOL_EN);
  278. twl4030_write(codec, TWL4030_REG_OPTION,
  279. TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
  280. TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
  281. /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
  282. twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
  283. /* Machine dependent setup */
  284. if (!pdata)
  285. return;
  286. twl4030->digimic_delay = pdata->digimic_delay;
  287. reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  288. reg &= ~TWL4030_RAMP_DELAY;
  289. reg |= (pdata->ramp_delay_value << 2);
  290. twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
  291. /* initiate offset cancellation */
  292. twl4030_codec_enable(codec, 1);
  293. reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  294. reg &= ~TWL4030_OFFSET_CNCL_SEL;
  295. reg |= pdata->offset_cncl_path;
  296. twl4030_write(codec, TWL4030_REG_ANAMICL,
  297. reg | TWL4030_CNCL_OFFSET_START);
  298. /* wait for offset cancellation to complete */
  299. do {
  300. /* this takes a little while, so don't slam i2c */
  301. udelay(2000);
  302. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  303. TWL4030_REG_ANAMICL);
  304. } while ((i++ < 100) &&
  305. ((byte & TWL4030_CNCL_OFFSET_START) ==
  306. TWL4030_CNCL_OFFSET_START));
  307. /* Make sure that the reg_cache has the same value as the HW */
  308. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  309. twl4030_codec_enable(codec, 0);
  310. }
  311. static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
  312. {
  313. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  314. int status = -1;
  315. if (enable) {
  316. twl4030->apll_enabled++;
  317. if (twl4030->apll_enabled == 1)
  318. status = twl4030_codec_enable_resource(
  319. TWL4030_CODEC_RES_APLL);
  320. } else {
  321. twl4030->apll_enabled--;
  322. if (!twl4030->apll_enabled)
  323. status = twl4030_codec_disable_resource(
  324. TWL4030_CODEC_RES_APLL);
  325. }
  326. if (status >= 0)
  327. twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
  328. }
  329. /* Earpiece */
  330. static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
  331. SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
  332. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
  333. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
  334. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
  335. };
  336. /* PreDrive Left */
  337. static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
  338. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
  339. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
  340. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
  341. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
  342. };
  343. /* PreDrive Right */
  344. static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
  345. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
  346. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
  347. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
  348. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
  349. };
  350. /* Headset Left */
  351. static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
  352. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
  353. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
  354. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
  355. };
  356. /* Headset Right */
  357. static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
  358. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
  359. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
  360. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
  361. };
  362. /* Carkit Left */
  363. static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
  364. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
  365. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
  366. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
  367. };
  368. /* Carkit Right */
  369. static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
  370. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
  371. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
  372. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
  373. };
  374. /* Handsfree Left */
  375. static const char *twl4030_handsfreel_texts[] =
  376. {"Voice", "AudioL1", "AudioL2", "AudioR2"};
  377. static const struct soc_enum twl4030_handsfreel_enum =
  378. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  379. ARRAY_SIZE(twl4030_handsfreel_texts),
  380. twl4030_handsfreel_texts);
  381. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  382. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  383. /* Handsfree Left virtual mute */
  384. static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
  385. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
  386. /* Handsfree Right */
  387. static const char *twl4030_handsfreer_texts[] =
  388. {"Voice", "AudioR1", "AudioR2", "AudioL2"};
  389. static const struct soc_enum twl4030_handsfreer_enum =
  390. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  391. ARRAY_SIZE(twl4030_handsfreer_texts),
  392. twl4030_handsfreer_texts);
  393. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  394. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  395. /* Handsfree Right virtual mute */
  396. static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
  397. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
  398. /* Vibra */
  399. /* Vibra audio path selection */
  400. static const char *twl4030_vibra_texts[] =
  401. {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
  402. static const struct soc_enum twl4030_vibra_enum =
  403. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
  404. ARRAY_SIZE(twl4030_vibra_texts),
  405. twl4030_vibra_texts);
  406. static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
  407. SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
  408. /* Vibra path selection: local vibrator (PWM) or audio driven */
  409. static const char *twl4030_vibrapath_texts[] =
  410. {"Local vibrator", "Audio"};
  411. static const struct soc_enum twl4030_vibrapath_enum =
  412. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
  413. ARRAY_SIZE(twl4030_vibrapath_texts),
  414. twl4030_vibrapath_texts);
  415. static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
  416. SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
  417. /* Left analog microphone selection */
  418. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
  419. SOC_DAPM_SINGLE("Main Mic Capture Switch",
  420. TWL4030_REG_ANAMICL, 0, 1, 0),
  421. SOC_DAPM_SINGLE("Headset Mic Capture Switch",
  422. TWL4030_REG_ANAMICL, 1, 1, 0),
  423. SOC_DAPM_SINGLE("AUXL Capture Switch",
  424. TWL4030_REG_ANAMICL, 2, 1, 0),
  425. SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
  426. TWL4030_REG_ANAMICL, 3, 1, 0),
  427. };
  428. /* Right analog microphone selection */
  429. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
  430. SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
  431. SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
  432. };
  433. /* TX1 L/R Analog/Digital microphone selection */
  434. static const char *twl4030_micpathtx1_texts[] =
  435. {"Analog", "Digimic0"};
  436. static const struct soc_enum twl4030_micpathtx1_enum =
  437. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  438. ARRAY_SIZE(twl4030_micpathtx1_texts),
  439. twl4030_micpathtx1_texts);
  440. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  441. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  442. /* TX2 L/R Analog/Digital microphone selection */
  443. static const char *twl4030_micpathtx2_texts[] =
  444. {"Analog", "Digimic1"};
  445. static const struct soc_enum twl4030_micpathtx2_enum =
  446. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  447. ARRAY_SIZE(twl4030_micpathtx2_texts),
  448. twl4030_micpathtx2_texts);
  449. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  450. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  451. /* Analog bypass for AudioR1 */
  452. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  453. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  454. /* Analog bypass for AudioL1 */
  455. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  456. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  457. /* Analog bypass for AudioR2 */
  458. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  459. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  460. /* Analog bypass for AudioL2 */
  461. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  462. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  463. /* Analog bypass for Voice */
  464. static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
  465. SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
  466. /* Digital bypass gain, mute instead of -30dB */
  467. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  468. TLV_DB_RANGE_HEAD(3),
  469. 0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
  470. 2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
  471. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  472. };
  473. /* Digital bypass left (TX1L -> RX2L) */
  474. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  475. SOC_DAPM_SINGLE_TLV("Volume",
  476. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  477. twl4030_dapm_dbypass_tlv);
  478. /* Digital bypass right (TX1R -> RX2R) */
  479. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  480. SOC_DAPM_SINGLE_TLV("Volume",
  481. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  482. twl4030_dapm_dbypass_tlv);
  483. /*
  484. * Voice Sidetone GAIN volume control:
  485. * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
  486. */
  487. static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
  488. /* Digital bypass voice: sidetone (VUL -> VDL)*/
  489. static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
  490. SOC_DAPM_SINGLE_TLV("Volume",
  491. TWL4030_REG_VSTPGA, 0, 0x29, 0,
  492. twl4030_dapm_dbypassv_tlv);
  493. /*
  494. * Output PGA builder:
  495. * Handle the muting and unmuting of the given output (turning off the
  496. * amplifier associated with the output pin)
  497. * On mute bypass the reg_cache and write 0 to the register
  498. * On unmute: restore the register content from the reg_cache
  499. * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
  500. */
  501. #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
  502. static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
  503. struct snd_kcontrol *kcontrol, int event) \
  504. { \
  505. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
  506. \
  507. switch (event) { \
  508. case SND_SOC_DAPM_POST_PMU: \
  509. twl4030->pin_name##_enabled = 1; \
  510. twl4030_write(w->codec, reg, \
  511. twl4030_read_reg_cache(w->codec, reg)); \
  512. break; \
  513. case SND_SOC_DAPM_POST_PMD: \
  514. twl4030->pin_name##_enabled = 0; \
  515. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
  516. 0, reg); \
  517. break; \
  518. } \
  519. return 0; \
  520. }
  521. TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
  522. TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
  523. TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
  524. TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
  525. TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
  526. static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
  527. {
  528. unsigned char hs_ctl;
  529. hs_ctl = twl4030_read_reg_cache(codec, reg);
  530. if (ramp) {
  531. /* HF ramp-up */
  532. hs_ctl |= TWL4030_HF_CTL_REF_EN;
  533. twl4030_write(codec, reg, hs_ctl);
  534. udelay(10);
  535. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  536. twl4030_write(codec, reg, hs_ctl);
  537. udelay(40);
  538. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  539. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  540. twl4030_write(codec, reg, hs_ctl);
  541. } else {
  542. /* HF ramp-down */
  543. hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
  544. hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
  545. twl4030_write(codec, reg, hs_ctl);
  546. hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
  547. twl4030_write(codec, reg, hs_ctl);
  548. udelay(40);
  549. hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
  550. twl4030_write(codec, reg, hs_ctl);
  551. }
  552. }
  553. static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
  554. struct snd_kcontrol *kcontrol, int event)
  555. {
  556. switch (event) {
  557. case SND_SOC_DAPM_POST_PMU:
  558. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
  559. break;
  560. case SND_SOC_DAPM_POST_PMD:
  561. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
  562. break;
  563. }
  564. return 0;
  565. }
  566. static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
  567. struct snd_kcontrol *kcontrol, int event)
  568. {
  569. switch (event) {
  570. case SND_SOC_DAPM_POST_PMU:
  571. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
  572. break;
  573. case SND_SOC_DAPM_POST_PMD:
  574. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
  575. break;
  576. }
  577. return 0;
  578. }
  579. static int vibramux_event(struct snd_soc_dapm_widget *w,
  580. struct snd_kcontrol *kcontrol, int event)
  581. {
  582. twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
  583. return 0;
  584. }
  585. static int apll_event(struct snd_soc_dapm_widget *w,
  586. struct snd_kcontrol *kcontrol, int event)
  587. {
  588. switch (event) {
  589. case SND_SOC_DAPM_PRE_PMU:
  590. twl4030_apll_enable(w->codec, 1);
  591. break;
  592. case SND_SOC_DAPM_POST_PMD:
  593. twl4030_apll_enable(w->codec, 0);
  594. break;
  595. }
  596. return 0;
  597. }
  598. static int aif_event(struct snd_soc_dapm_widget *w,
  599. struct snd_kcontrol *kcontrol, int event)
  600. {
  601. u8 audio_if;
  602. audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
  603. switch (event) {
  604. case SND_SOC_DAPM_PRE_PMU:
  605. /* Enable AIF */
  606. /* enable the PLL before we use it to clock the DAI */
  607. twl4030_apll_enable(w->codec, 1);
  608. twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
  609. audio_if | TWL4030_AIF_EN);
  610. break;
  611. case SND_SOC_DAPM_POST_PMD:
  612. /* disable the DAI before we stop it's source PLL */
  613. twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
  614. audio_if & ~TWL4030_AIF_EN);
  615. twl4030_apll_enable(w->codec, 0);
  616. break;
  617. }
  618. return 0;
  619. }
  620. static void headset_ramp(struct snd_soc_codec *codec, int ramp)
  621. {
  622. struct twl4030_codec_audio_data *pdata = codec->dev->platform_data;
  623. unsigned char hs_gain, hs_pop;
  624. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  625. /* Base values for ramp delay calculation: 2^19 - 2^26 */
  626. unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
  627. 8388608, 16777216, 33554432, 67108864};
  628. hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
  629. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  630. /* Enable external mute control, this dramatically reduces
  631. * the pop-noise */
  632. if (pdata && pdata->hs_extmute) {
  633. if (pdata->set_hs_extmute) {
  634. pdata->set_hs_extmute(1);
  635. } else {
  636. hs_pop |= TWL4030_EXTMUTE;
  637. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  638. }
  639. }
  640. if (ramp) {
  641. /* Headset ramp-up according to the TRM */
  642. hs_pop |= TWL4030_VMID_EN;
  643. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  644. /* Actually write to the register */
  645. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  646. hs_gain,
  647. TWL4030_REG_HS_GAIN_SET);
  648. hs_pop |= TWL4030_RAMP_EN;
  649. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  650. /* Wait ramp delay time + 1, so the VMID can settle */
  651. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  652. twl4030->sysclk) + 1);
  653. } else {
  654. /* Headset ramp-down _not_ according to
  655. * the TRM, but in a way that it is working */
  656. hs_pop &= ~TWL4030_RAMP_EN;
  657. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  658. /* Wait ramp delay time + 1, so the VMID can settle */
  659. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  660. twl4030->sysclk) + 1);
  661. /* Bypass the reg_cache to mute the headset */
  662. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  663. hs_gain & (~0x0f),
  664. TWL4030_REG_HS_GAIN_SET);
  665. hs_pop &= ~TWL4030_VMID_EN;
  666. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  667. }
  668. /* Disable external mute */
  669. if (pdata && pdata->hs_extmute) {
  670. if (pdata->set_hs_extmute) {
  671. pdata->set_hs_extmute(0);
  672. } else {
  673. hs_pop &= ~TWL4030_EXTMUTE;
  674. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  675. }
  676. }
  677. }
  678. static int headsetlpga_event(struct snd_soc_dapm_widget *w,
  679. struct snd_kcontrol *kcontrol, int event)
  680. {
  681. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
  682. switch (event) {
  683. case SND_SOC_DAPM_POST_PMU:
  684. /* Do the ramp-up only once */
  685. if (!twl4030->hsr_enabled)
  686. headset_ramp(w->codec, 1);
  687. twl4030->hsl_enabled = 1;
  688. break;
  689. case SND_SOC_DAPM_POST_PMD:
  690. /* Do the ramp-down only if both headsetL/R is disabled */
  691. if (!twl4030->hsr_enabled)
  692. headset_ramp(w->codec, 0);
  693. twl4030->hsl_enabled = 0;
  694. break;
  695. }
  696. return 0;
  697. }
  698. static int headsetrpga_event(struct snd_soc_dapm_widget *w,
  699. struct snd_kcontrol *kcontrol, int event)
  700. {
  701. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
  702. switch (event) {
  703. case SND_SOC_DAPM_POST_PMU:
  704. /* Do the ramp-up only once */
  705. if (!twl4030->hsl_enabled)
  706. headset_ramp(w->codec, 1);
  707. twl4030->hsr_enabled = 1;
  708. break;
  709. case SND_SOC_DAPM_POST_PMD:
  710. /* Do the ramp-down only if both headsetL/R is disabled */
  711. if (!twl4030->hsl_enabled)
  712. headset_ramp(w->codec, 0);
  713. twl4030->hsr_enabled = 0;
  714. break;
  715. }
  716. return 0;
  717. }
  718. static int digimic_event(struct snd_soc_dapm_widget *w,
  719. struct snd_kcontrol *kcontrol, int event)
  720. {
  721. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
  722. if (twl4030->digimic_delay)
  723. mdelay(twl4030->digimic_delay);
  724. return 0;
  725. }
  726. /*
  727. * Some of the gain controls in TWL (mostly those which are associated with
  728. * the outputs) are implemented in an interesting way:
  729. * 0x0 : Power down (mute)
  730. * 0x1 : 6dB
  731. * 0x2 : 0 dB
  732. * 0x3 : -6 dB
  733. * Inverting not going to help with these.
  734. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  735. */
  736. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  737. xinvert, tlv_array) \
  738. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  739. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  740. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  741. .tlv.p = (tlv_array), \
  742. .info = snd_soc_info_volsw, \
  743. .get = snd_soc_get_volsw_twl4030, \
  744. .put = snd_soc_put_volsw_twl4030, \
  745. .private_value = (unsigned long)&(struct soc_mixer_control) \
  746. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  747. .max = xmax, .invert = xinvert} }
  748. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  749. xinvert, tlv_array) \
  750. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  751. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  752. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  753. .tlv.p = (tlv_array), \
  754. .info = snd_soc_info_volsw_2r, \
  755. .get = snd_soc_get_volsw_r2_twl4030,\
  756. .put = snd_soc_put_volsw_r2_twl4030, \
  757. .private_value = (unsigned long)&(struct soc_mixer_control) \
  758. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  759. .rshift = xshift, .max = xmax, .invert = xinvert} }
  760. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  761. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  762. xinvert, tlv_array)
  763. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  764. struct snd_ctl_elem_value *ucontrol)
  765. {
  766. struct soc_mixer_control *mc =
  767. (struct soc_mixer_control *)kcontrol->private_value;
  768. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  769. unsigned int reg = mc->reg;
  770. unsigned int shift = mc->shift;
  771. unsigned int rshift = mc->rshift;
  772. int max = mc->max;
  773. int mask = (1 << fls(max)) - 1;
  774. ucontrol->value.integer.value[0] =
  775. (snd_soc_read(codec, reg) >> shift) & mask;
  776. if (ucontrol->value.integer.value[0])
  777. ucontrol->value.integer.value[0] =
  778. max + 1 - ucontrol->value.integer.value[0];
  779. if (shift != rshift) {
  780. ucontrol->value.integer.value[1] =
  781. (snd_soc_read(codec, reg) >> rshift) & mask;
  782. if (ucontrol->value.integer.value[1])
  783. ucontrol->value.integer.value[1] =
  784. max + 1 - ucontrol->value.integer.value[1];
  785. }
  786. return 0;
  787. }
  788. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  789. struct snd_ctl_elem_value *ucontrol)
  790. {
  791. struct soc_mixer_control *mc =
  792. (struct soc_mixer_control *)kcontrol->private_value;
  793. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  794. unsigned int reg = mc->reg;
  795. unsigned int shift = mc->shift;
  796. unsigned int rshift = mc->rshift;
  797. int max = mc->max;
  798. int mask = (1 << fls(max)) - 1;
  799. unsigned short val, val2, val_mask;
  800. val = (ucontrol->value.integer.value[0] & mask);
  801. val_mask = mask << shift;
  802. if (val)
  803. val = max + 1 - val;
  804. val = val << shift;
  805. if (shift != rshift) {
  806. val2 = (ucontrol->value.integer.value[1] & mask);
  807. val_mask |= mask << rshift;
  808. if (val2)
  809. val2 = max + 1 - val2;
  810. val |= val2 << rshift;
  811. }
  812. return snd_soc_update_bits(codec, reg, val_mask, val);
  813. }
  814. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  815. struct snd_ctl_elem_value *ucontrol)
  816. {
  817. struct soc_mixer_control *mc =
  818. (struct soc_mixer_control *)kcontrol->private_value;
  819. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  820. unsigned int reg = mc->reg;
  821. unsigned int reg2 = mc->rreg;
  822. unsigned int shift = mc->shift;
  823. int max = mc->max;
  824. int mask = (1<<fls(max))-1;
  825. ucontrol->value.integer.value[0] =
  826. (snd_soc_read(codec, reg) >> shift) & mask;
  827. ucontrol->value.integer.value[1] =
  828. (snd_soc_read(codec, reg2) >> shift) & mask;
  829. if (ucontrol->value.integer.value[0])
  830. ucontrol->value.integer.value[0] =
  831. max + 1 - ucontrol->value.integer.value[0];
  832. if (ucontrol->value.integer.value[1])
  833. ucontrol->value.integer.value[1] =
  834. max + 1 - ucontrol->value.integer.value[1];
  835. return 0;
  836. }
  837. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  838. struct snd_ctl_elem_value *ucontrol)
  839. {
  840. struct soc_mixer_control *mc =
  841. (struct soc_mixer_control *)kcontrol->private_value;
  842. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  843. unsigned int reg = mc->reg;
  844. unsigned int reg2 = mc->rreg;
  845. unsigned int shift = mc->shift;
  846. int max = mc->max;
  847. int mask = (1 << fls(max)) - 1;
  848. int err;
  849. unsigned short val, val2, val_mask;
  850. val_mask = mask << shift;
  851. val = (ucontrol->value.integer.value[0] & mask);
  852. val2 = (ucontrol->value.integer.value[1] & mask);
  853. if (val)
  854. val = max + 1 - val;
  855. if (val2)
  856. val2 = max + 1 - val2;
  857. val = val << shift;
  858. val2 = val2 << shift;
  859. err = snd_soc_update_bits(codec, reg, val_mask, val);
  860. if (err < 0)
  861. return err;
  862. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  863. return err;
  864. }
  865. /* Codec operation modes */
  866. static const char *twl4030_op_modes_texts[] = {
  867. "Option 2 (voice/audio)", "Option 1 (audio)"
  868. };
  869. static const struct soc_enum twl4030_op_modes_enum =
  870. SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
  871. ARRAY_SIZE(twl4030_op_modes_texts),
  872. twl4030_op_modes_texts);
  873. static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
  874. struct snd_ctl_elem_value *ucontrol)
  875. {
  876. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  877. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  878. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  879. unsigned short val;
  880. unsigned short mask, bitmask;
  881. if (twl4030->configured) {
  882. printk(KERN_ERR "twl4030 operation mode cannot be "
  883. "changed on-the-fly\n");
  884. return -EBUSY;
  885. }
  886. for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
  887. ;
  888. if (ucontrol->value.enumerated.item[0] > e->max - 1)
  889. return -EINVAL;
  890. val = ucontrol->value.enumerated.item[0] << e->shift_l;
  891. mask = (bitmask - 1) << e->shift_l;
  892. if (e->shift_l != e->shift_r) {
  893. if (ucontrol->value.enumerated.item[1] > e->max - 1)
  894. return -EINVAL;
  895. val |= ucontrol->value.enumerated.item[1] << e->shift_r;
  896. mask |= (bitmask - 1) << e->shift_r;
  897. }
  898. return snd_soc_update_bits(codec, e->reg, mask, val);
  899. }
  900. /*
  901. * FGAIN volume control:
  902. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  903. */
  904. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  905. /*
  906. * CGAIN volume control:
  907. * 0 dB to 12 dB in 6 dB steps
  908. * value 2 and 3 means 12 dB
  909. */
  910. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  911. /*
  912. * Voice Downlink GAIN volume control:
  913. * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
  914. */
  915. static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
  916. /*
  917. * Analog playback gain
  918. * -24 dB to 12 dB in 2 dB steps
  919. */
  920. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  921. /*
  922. * Gain controls tied to outputs
  923. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  924. */
  925. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  926. /*
  927. * Gain control for earpiece amplifier
  928. * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
  929. */
  930. static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
  931. /*
  932. * Capture gain after the ADCs
  933. * from 0 dB to 31 dB in 1 dB steps
  934. */
  935. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  936. /*
  937. * Gain control for input amplifiers
  938. * 0 dB to 30 dB in 6 dB steps
  939. */
  940. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  941. /* AVADC clock priority */
  942. static const char *twl4030_avadc_clk_priority_texts[] = {
  943. "Voice high priority", "HiFi high priority"
  944. };
  945. static const struct soc_enum twl4030_avadc_clk_priority_enum =
  946. SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
  947. ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
  948. twl4030_avadc_clk_priority_texts);
  949. static const char *twl4030_rampdelay_texts[] = {
  950. "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
  951. "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
  952. "3495/2581/1748 ms"
  953. };
  954. static const struct soc_enum twl4030_rampdelay_enum =
  955. SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
  956. ARRAY_SIZE(twl4030_rampdelay_texts),
  957. twl4030_rampdelay_texts);
  958. /* Vibra H-bridge direction mode */
  959. static const char *twl4030_vibradirmode_texts[] = {
  960. "Vibra H-bridge direction", "Audio data MSB",
  961. };
  962. static const struct soc_enum twl4030_vibradirmode_enum =
  963. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
  964. ARRAY_SIZE(twl4030_vibradirmode_texts),
  965. twl4030_vibradirmode_texts);
  966. /* Vibra H-bridge direction */
  967. static const char *twl4030_vibradir_texts[] = {
  968. "Positive polarity", "Negative polarity",
  969. };
  970. static const struct soc_enum twl4030_vibradir_enum =
  971. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
  972. ARRAY_SIZE(twl4030_vibradir_texts),
  973. twl4030_vibradir_texts);
  974. /* Digimic Left and right swapping */
  975. static const char *twl4030_digimicswap_texts[] = {
  976. "Not swapped", "Swapped",
  977. };
  978. static const struct soc_enum twl4030_digimicswap_enum =
  979. SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
  980. ARRAY_SIZE(twl4030_digimicswap_texts),
  981. twl4030_digimicswap_texts);
  982. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  983. /* Codec operation mode control */
  984. SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
  985. snd_soc_get_enum_double,
  986. snd_soc_put_twl4030_opmode_enum_double),
  987. /* Common playback gain controls */
  988. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  989. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  990. 0, 0x3f, 0, digital_fine_tlv),
  991. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  992. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  993. 0, 0x3f, 0, digital_fine_tlv),
  994. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  995. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  996. 6, 0x2, 0, digital_coarse_tlv),
  997. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  998. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  999. 6, 0x2, 0, digital_coarse_tlv),
  1000. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  1001. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  1002. 3, 0x12, 1, analog_tlv),
  1003. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  1004. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  1005. 3, 0x12, 1, analog_tlv),
  1006. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  1007. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  1008. 1, 1, 0),
  1009. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  1010. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  1011. 1, 1, 0),
  1012. /* Common voice downlink gain controls */
  1013. SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
  1014. TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
  1015. SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
  1016. TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
  1017. SOC_SINGLE("DAC Voice Analog Downlink Switch",
  1018. TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
  1019. /* Separate output gain controls */
  1020. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  1021. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  1022. 4, 3, 0, output_tvl),
  1023. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  1024. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  1025. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  1026. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  1027. 4, 3, 0, output_tvl),
  1028. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  1029. TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
  1030. /* Common capture gain controls */
  1031. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  1032. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  1033. 0, 0x1f, 0, digital_capture_tlv),
  1034. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  1035. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  1036. 0, 0x1f, 0, digital_capture_tlv),
  1037. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  1038. 0, 3, 5, 0, input_gain_tlv),
  1039. SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
  1040. SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
  1041. SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
  1042. SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
  1043. SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
  1044. };
  1045. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  1046. /* Left channel inputs */
  1047. SND_SOC_DAPM_INPUT("MAINMIC"),
  1048. SND_SOC_DAPM_INPUT("HSMIC"),
  1049. SND_SOC_DAPM_INPUT("AUXL"),
  1050. SND_SOC_DAPM_INPUT("CARKITMIC"),
  1051. /* Right channel inputs */
  1052. SND_SOC_DAPM_INPUT("SUBMIC"),
  1053. SND_SOC_DAPM_INPUT("AUXR"),
  1054. /* Digital microphones (Stereo) */
  1055. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  1056. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  1057. /* Outputs */
  1058. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  1059. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  1060. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  1061. SND_SOC_DAPM_OUTPUT("HSOL"),
  1062. SND_SOC_DAPM_OUTPUT("HSOR"),
  1063. SND_SOC_DAPM_OUTPUT("CARKITL"),
  1064. SND_SOC_DAPM_OUTPUT("CARKITR"),
  1065. SND_SOC_DAPM_OUTPUT("HFL"),
  1066. SND_SOC_DAPM_OUTPUT("HFR"),
  1067. SND_SOC_DAPM_OUTPUT("VIBRA"),
  1068. /* AIF and APLL clocks for running DAIs (including loopback) */
  1069. SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
  1070. SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
  1071. SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
  1072. /* DACs */
  1073. SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
  1074. SND_SOC_NOPM, 0, 0),
  1075. SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
  1076. SND_SOC_NOPM, 0, 0),
  1077. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
  1078. SND_SOC_NOPM, 0, 0),
  1079. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
  1080. SND_SOC_NOPM, 0, 0),
  1081. SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
  1082. SND_SOC_NOPM, 0, 0),
  1083. /* Analog bypasses */
  1084. SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1085. &twl4030_dapm_abypassr1_control),
  1086. SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1087. &twl4030_dapm_abypassl1_control),
  1088. SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1089. &twl4030_dapm_abypassr2_control),
  1090. SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1091. &twl4030_dapm_abypassl2_control),
  1092. SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
  1093. &twl4030_dapm_abypassv_control),
  1094. /* Master analog loopback switch */
  1095. SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
  1096. NULL, 0),
  1097. /* Digital bypasses */
  1098. SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  1099. &twl4030_dapm_dbypassl_control),
  1100. SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  1101. &twl4030_dapm_dbypassr_control),
  1102. SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
  1103. &twl4030_dapm_dbypassv_control),
  1104. /* Digital mixers, power control for the physical DACs */
  1105. SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
  1106. TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
  1107. SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
  1108. TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
  1109. SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
  1110. TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
  1111. SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
  1112. TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
  1113. SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
  1114. TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
  1115. /* Analog mixers, power control for the physical PGAs */
  1116. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
  1117. TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
  1118. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
  1119. TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
  1120. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
  1121. TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
  1122. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
  1123. TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
  1124. SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
  1125. TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
  1126. SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
  1127. SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
  1128. SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
  1129. SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
  1130. /* Output MIXER controls */
  1131. /* Earpiece */
  1132. SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
  1133. &twl4030_dapm_earpiece_controls[0],
  1134. ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
  1135. SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
  1136. 0, 0, NULL, 0, earpiecepga_event,
  1137. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1138. /* PreDrivL/R */
  1139. SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
  1140. &twl4030_dapm_predrivel_controls[0],
  1141. ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
  1142. SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
  1143. 0, 0, NULL, 0, predrivelpga_event,
  1144. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1145. SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
  1146. &twl4030_dapm_predriver_controls[0],
  1147. ARRAY_SIZE(twl4030_dapm_predriver_controls)),
  1148. SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
  1149. 0, 0, NULL, 0, predriverpga_event,
  1150. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1151. /* HeadsetL/R */
  1152. SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
  1153. &twl4030_dapm_hsol_controls[0],
  1154. ARRAY_SIZE(twl4030_dapm_hsol_controls)),
  1155. SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
  1156. 0, 0, NULL, 0, headsetlpga_event,
  1157. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1158. SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
  1159. &twl4030_dapm_hsor_controls[0],
  1160. ARRAY_SIZE(twl4030_dapm_hsor_controls)),
  1161. SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
  1162. 0, 0, NULL, 0, headsetrpga_event,
  1163. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1164. /* CarkitL/R */
  1165. SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
  1166. &twl4030_dapm_carkitl_controls[0],
  1167. ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
  1168. SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
  1169. 0, 0, NULL, 0, carkitlpga_event,
  1170. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1171. SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
  1172. &twl4030_dapm_carkitr_controls[0],
  1173. ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
  1174. SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
  1175. 0, 0, NULL, 0, carkitrpga_event,
  1176. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1177. /* Output MUX controls */
  1178. /* HandsfreeL/R */
  1179. SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
  1180. &twl4030_dapm_handsfreel_control),
  1181. SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
  1182. &twl4030_dapm_handsfreelmute_control),
  1183. SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
  1184. 0, 0, NULL, 0, handsfreelpga_event,
  1185. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1186. SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
  1187. &twl4030_dapm_handsfreer_control),
  1188. SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
  1189. &twl4030_dapm_handsfreermute_control),
  1190. SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
  1191. 0, 0, NULL, 0, handsfreerpga_event,
  1192. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1193. /* Vibra */
  1194. SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
  1195. &twl4030_dapm_vibra_control, vibramux_event,
  1196. SND_SOC_DAPM_PRE_PMU),
  1197. SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
  1198. &twl4030_dapm_vibrapath_control),
  1199. /* Introducing four virtual ADC, since TWL4030 have four channel for
  1200. capture */
  1201. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  1202. SND_SOC_NOPM, 0, 0),
  1203. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  1204. SND_SOC_NOPM, 0, 0),
  1205. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  1206. SND_SOC_NOPM, 0, 0),
  1207. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  1208. SND_SOC_NOPM, 0, 0),
  1209. /* Analog/Digital mic path selection.
  1210. TX1 Left/Right: either analog Left/Right or Digimic0
  1211. TX2 Left/Right: either analog Left/Right or Digimic1 */
  1212. SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  1213. &twl4030_dapm_micpathtx1_control),
  1214. SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  1215. &twl4030_dapm_micpathtx2_control),
  1216. /* Analog input mixers for the capture amplifiers */
  1217. SND_SOC_DAPM_MIXER("Analog Left",
  1218. TWL4030_REG_ANAMICL, 4, 0,
  1219. &twl4030_dapm_analoglmic_controls[0],
  1220. ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
  1221. SND_SOC_DAPM_MIXER("Analog Right",
  1222. TWL4030_REG_ANAMICR, 4, 0,
  1223. &twl4030_dapm_analogrmic_controls[0],
  1224. ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
  1225. SND_SOC_DAPM_PGA("ADC Physical Left",
  1226. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  1227. SND_SOC_DAPM_PGA("ADC Physical Right",
  1228. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  1229. SND_SOC_DAPM_PGA_E("Digimic0 Enable",
  1230. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0,
  1231. digimic_event, SND_SOC_DAPM_POST_PMU),
  1232. SND_SOC_DAPM_PGA_E("Digimic1 Enable",
  1233. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0,
  1234. digimic_event, SND_SOC_DAPM_POST_PMU),
  1235. SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0,
  1236. NULL, 0),
  1237. SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0,
  1238. NULL, 0),
  1239. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  1240. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  1241. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  1242. };
  1243. static const struct snd_soc_dapm_route intercon[] = {
  1244. {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
  1245. {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
  1246. {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
  1247. {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
  1248. {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
  1249. /* Supply for the digital part (APLL) */
  1250. {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
  1251. {"DAC Left1", NULL, "AIF Enable"},
  1252. {"DAC Right1", NULL, "AIF Enable"},
  1253. {"DAC Left2", NULL, "AIF Enable"},
  1254. {"DAC Right1", NULL, "AIF Enable"},
  1255. {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
  1256. {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
  1257. {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
  1258. {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
  1259. {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
  1260. {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
  1261. {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
  1262. /* Internal playback routings */
  1263. /* Earpiece */
  1264. {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
  1265. {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1266. {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1267. {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1268. {"Earpiece PGA", NULL, "Earpiece Mixer"},
  1269. /* PreDrivL */
  1270. {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1271. {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1272. {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1273. {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1274. {"PredriveL PGA", NULL, "PredriveL Mixer"},
  1275. /* PreDrivR */
  1276. {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1277. {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1278. {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1279. {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1280. {"PredriveR PGA", NULL, "PredriveR Mixer"},
  1281. /* HeadsetL */
  1282. {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1283. {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1284. {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1285. {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
  1286. /* HeadsetR */
  1287. {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1288. {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1289. {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1290. {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
  1291. /* CarkitL */
  1292. {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1293. {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1294. {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1295. {"CarkitL PGA", NULL, "CarkitL Mixer"},
  1296. /* CarkitR */
  1297. {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1298. {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1299. {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1300. {"CarkitR PGA", NULL, "CarkitR Mixer"},
  1301. /* HandsfreeL */
  1302. {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
  1303. {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
  1304. {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1305. {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1306. {"HandsfreeL", "Switch", "HandsfreeL Mux"},
  1307. {"HandsfreeL PGA", NULL, "HandsfreeL"},
  1308. /* HandsfreeR */
  1309. {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
  1310. {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
  1311. {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1312. {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1313. {"HandsfreeR", "Switch", "HandsfreeR Mux"},
  1314. {"HandsfreeR PGA", NULL, "HandsfreeR"},
  1315. /* Vibra */
  1316. {"Vibra Mux", "AudioL1", "DAC Left1"},
  1317. {"Vibra Mux", "AudioR1", "DAC Right1"},
  1318. {"Vibra Mux", "AudioL2", "DAC Left2"},
  1319. {"Vibra Mux", "AudioR2", "DAC Right2"},
  1320. /* outputs */
  1321. /* Must be always connected (for AIF and APLL) */
  1322. {"Virtual HiFi OUT", NULL, "DAC Left1"},
  1323. {"Virtual HiFi OUT", NULL, "DAC Right1"},
  1324. {"Virtual HiFi OUT", NULL, "DAC Left2"},
  1325. {"Virtual HiFi OUT", NULL, "DAC Right2"},
  1326. /* Must be always connected (for APLL) */
  1327. {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
  1328. /* Physical outputs */
  1329. {"EARPIECE", NULL, "Earpiece PGA"},
  1330. {"PREDRIVEL", NULL, "PredriveL PGA"},
  1331. {"PREDRIVER", NULL, "PredriveR PGA"},
  1332. {"HSOL", NULL, "HeadsetL PGA"},
  1333. {"HSOR", NULL, "HeadsetR PGA"},
  1334. {"CARKITL", NULL, "CarkitL PGA"},
  1335. {"CARKITR", NULL, "CarkitR PGA"},
  1336. {"HFL", NULL, "HandsfreeL PGA"},
  1337. {"HFR", NULL, "HandsfreeR PGA"},
  1338. {"Vibra Route", "Audio", "Vibra Mux"},
  1339. {"VIBRA", NULL, "Vibra Route"},
  1340. /* Capture path */
  1341. /* Must be always connected (for AIF and APLL) */
  1342. {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
  1343. {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
  1344. {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
  1345. {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
  1346. /* Physical inputs */
  1347. {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
  1348. {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
  1349. {"Analog Left", "AUXL Capture Switch", "AUXL"},
  1350. {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
  1351. {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
  1352. {"Analog Right", "AUXR Capture Switch", "AUXR"},
  1353. {"ADC Physical Left", NULL, "Analog Left"},
  1354. {"ADC Physical Right", NULL, "Analog Right"},
  1355. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  1356. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  1357. {"DIGIMIC0", NULL, "micbias1 select"},
  1358. {"DIGIMIC1", NULL, "micbias2 select"},
  1359. /* TX1 Left capture path */
  1360. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  1361. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1362. /* TX1 Right capture path */
  1363. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  1364. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1365. /* TX2 Left capture path */
  1366. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  1367. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1368. /* TX2 Right capture path */
  1369. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  1370. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1371. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  1372. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  1373. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  1374. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  1375. {"ADC Virtual Left1", NULL, "AIF Enable"},
  1376. {"ADC Virtual Right1", NULL, "AIF Enable"},
  1377. {"ADC Virtual Left2", NULL, "AIF Enable"},
  1378. {"ADC Virtual Right2", NULL, "AIF Enable"},
  1379. /* Analog bypass routes */
  1380. {"Right1 Analog Loopback", "Switch", "Analog Right"},
  1381. {"Left1 Analog Loopback", "Switch", "Analog Left"},
  1382. {"Right2 Analog Loopback", "Switch", "Analog Right"},
  1383. {"Left2 Analog Loopback", "Switch", "Analog Left"},
  1384. {"Voice Analog Loopback", "Switch", "Analog Left"},
  1385. /* Supply for the Analog loopbacks */
  1386. {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
  1387. {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
  1388. {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
  1389. {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
  1390. {"Voice Analog Loopback", NULL, "FM Loop Enable"},
  1391. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  1392. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  1393. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  1394. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  1395. {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
  1396. /* Digital bypass routes */
  1397. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  1398. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  1399. {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
  1400. {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
  1401. {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
  1402. {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
  1403. };
  1404. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  1405. {
  1406. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1407. ARRAY_SIZE(twl4030_dapm_widgets));
  1408. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1409. return 0;
  1410. }
  1411. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1412. enum snd_soc_bias_level level)
  1413. {
  1414. switch (level) {
  1415. case SND_SOC_BIAS_ON:
  1416. break;
  1417. case SND_SOC_BIAS_PREPARE:
  1418. break;
  1419. case SND_SOC_BIAS_STANDBY:
  1420. if (codec->bias_level == SND_SOC_BIAS_OFF)
  1421. twl4030_codec_enable(codec, 1);
  1422. break;
  1423. case SND_SOC_BIAS_OFF:
  1424. twl4030_codec_enable(codec, 0);
  1425. break;
  1426. }
  1427. codec->bias_level = level;
  1428. return 0;
  1429. }
  1430. static void twl4030_constraints(struct twl4030_priv *twl4030,
  1431. struct snd_pcm_substream *mst_substream)
  1432. {
  1433. struct snd_pcm_substream *slv_substream;
  1434. /* Pick the stream, which need to be constrained */
  1435. if (mst_substream == twl4030->master_substream)
  1436. slv_substream = twl4030->slave_substream;
  1437. else if (mst_substream == twl4030->slave_substream)
  1438. slv_substream = twl4030->master_substream;
  1439. else /* This should not happen.. */
  1440. return;
  1441. /* Set the constraints according to the already configured stream */
  1442. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1443. SNDRV_PCM_HW_PARAM_RATE,
  1444. twl4030->rate,
  1445. twl4030->rate);
  1446. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1447. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1448. twl4030->sample_bits,
  1449. twl4030->sample_bits);
  1450. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1451. SNDRV_PCM_HW_PARAM_CHANNELS,
  1452. twl4030->channels,
  1453. twl4030->channels);
  1454. }
  1455. /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
  1456. * capture has to be enabled/disabled. */
  1457. static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
  1458. int enable)
  1459. {
  1460. u8 reg, mask;
  1461. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1462. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1463. mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
  1464. else
  1465. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1466. if (enable)
  1467. reg |= mask;
  1468. else
  1469. reg &= ~mask;
  1470. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1471. }
  1472. static int twl4030_startup(struct snd_pcm_substream *substream,
  1473. struct snd_soc_dai *dai)
  1474. {
  1475. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1476. struct snd_soc_codec *codec = rtd->codec;
  1477. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1478. if (twl4030->master_substream) {
  1479. twl4030->slave_substream = substream;
  1480. /* The DAI has one configuration for playback and capture, so
  1481. * if the DAI has been already configured then constrain this
  1482. * substream to match it. */
  1483. if (twl4030->configured)
  1484. twl4030_constraints(twl4030, twl4030->master_substream);
  1485. } else {
  1486. if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1487. TWL4030_OPTION_1)) {
  1488. /* In option2 4 channel is not supported, set the
  1489. * constraint for the first stream for channels, the
  1490. * second stream will 'inherit' this cosntraint */
  1491. snd_pcm_hw_constraint_minmax(substream->runtime,
  1492. SNDRV_PCM_HW_PARAM_CHANNELS,
  1493. 2, 2);
  1494. }
  1495. twl4030->master_substream = substream;
  1496. }
  1497. return 0;
  1498. }
  1499. static void twl4030_shutdown(struct snd_pcm_substream *substream,
  1500. struct snd_soc_dai *dai)
  1501. {
  1502. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1503. struct snd_soc_codec *codec = rtd->codec;
  1504. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1505. if (twl4030->master_substream == substream)
  1506. twl4030->master_substream = twl4030->slave_substream;
  1507. twl4030->slave_substream = NULL;
  1508. /* If all streams are closed, or the remaining stream has not yet
  1509. * been configured than set the DAI as not configured. */
  1510. if (!twl4030->master_substream)
  1511. twl4030->configured = 0;
  1512. else if (!twl4030->master_substream->runtime->channels)
  1513. twl4030->configured = 0;
  1514. /* If the closing substream had 4 channel, do the necessary cleanup */
  1515. if (substream->runtime->channels == 4)
  1516. twl4030_tdm_enable(codec, substream->stream, 0);
  1517. }
  1518. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1519. struct snd_pcm_hw_params *params,
  1520. struct snd_soc_dai *dai)
  1521. {
  1522. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1523. struct snd_soc_codec *codec = rtd->codec;
  1524. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1525. u8 mode, old_mode, format, old_format;
  1526. /* If the substream has 4 channel, do the necessary setup */
  1527. if (params_channels(params) == 4) {
  1528. format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1529. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  1530. /* Safety check: are we in the correct operating mode and
  1531. * the interface is in TDM mode? */
  1532. if ((mode & TWL4030_OPTION_1) &&
  1533. ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
  1534. twl4030_tdm_enable(codec, substream->stream, 1);
  1535. else
  1536. return -EINVAL;
  1537. }
  1538. if (twl4030->configured)
  1539. /* Ignoring hw_params for already configured DAI */
  1540. return 0;
  1541. /* bit rate */
  1542. old_mode = twl4030_read_reg_cache(codec,
  1543. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1544. mode = old_mode & ~TWL4030_APLL_RATE;
  1545. switch (params_rate(params)) {
  1546. case 8000:
  1547. mode |= TWL4030_APLL_RATE_8000;
  1548. break;
  1549. case 11025:
  1550. mode |= TWL4030_APLL_RATE_11025;
  1551. break;
  1552. case 12000:
  1553. mode |= TWL4030_APLL_RATE_12000;
  1554. break;
  1555. case 16000:
  1556. mode |= TWL4030_APLL_RATE_16000;
  1557. break;
  1558. case 22050:
  1559. mode |= TWL4030_APLL_RATE_22050;
  1560. break;
  1561. case 24000:
  1562. mode |= TWL4030_APLL_RATE_24000;
  1563. break;
  1564. case 32000:
  1565. mode |= TWL4030_APLL_RATE_32000;
  1566. break;
  1567. case 44100:
  1568. mode |= TWL4030_APLL_RATE_44100;
  1569. break;
  1570. case 48000:
  1571. mode |= TWL4030_APLL_RATE_48000;
  1572. break;
  1573. case 96000:
  1574. mode |= TWL4030_APLL_RATE_96000;
  1575. break;
  1576. default:
  1577. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1578. params_rate(params));
  1579. return -EINVAL;
  1580. }
  1581. /* sample size */
  1582. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1583. format = old_format;
  1584. format &= ~TWL4030_DATA_WIDTH;
  1585. switch (params_format(params)) {
  1586. case SNDRV_PCM_FORMAT_S16_LE:
  1587. format |= TWL4030_DATA_WIDTH_16S_16W;
  1588. break;
  1589. case SNDRV_PCM_FORMAT_S24_LE:
  1590. format |= TWL4030_DATA_WIDTH_32S_24W;
  1591. break;
  1592. default:
  1593. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1594. params_format(params));
  1595. return -EINVAL;
  1596. }
  1597. if (format != old_format || mode != old_mode) {
  1598. if (twl4030->codec_powered) {
  1599. /*
  1600. * If the codec is powered, than we need to toggle the
  1601. * codec power.
  1602. */
  1603. twl4030_codec_enable(codec, 0);
  1604. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1605. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1606. twl4030_codec_enable(codec, 1);
  1607. } else {
  1608. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1609. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1610. }
  1611. }
  1612. /* Store the important parameters for the DAI configuration and set
  1613. * the DAI as configured */
  1614. twl4030->configured = 1;
  1615. twl4030->rate = params_rate(params);
  1616. twl4030->sample_bits = hw_param_interval(params,
  1617. SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
  1618. twl4030->channels = params_channels(params);
  1619. /* If both playback and capture streams are open, and one of them
  1620. * is setting the hw parameters right now (since we are here), set
  1621. * constraints to the other stream to match the current one. */
  1622. if (twl4030->slave_substream)
  1623. twl4030_constraints(twl4030, substream);
  1624. return 0;
  1625. }
  1626. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1627. int clk_id, unsigned int freq, int dir)
  1628. {
  1629. struct snd_soc_codec *codec = codec_dai->codec;
  1630. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1631. switch (freq) {
  1632. case 19200000:
  1633. case 26000000:
  1634. case 38400000:
  1635. break;
  1636. default:
  1637. dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq);
  1638. return -EINVAL;
  1639. }
  1640. if ((freq / 1000) != twl4030->sysclk) {
  1641. dev_err(codec->dev,
  1642. "Mismatch in APLL mclk: %u (configured: %u)\n",
  1643. freq, twl4030->sysclk * 1000);
  1644. return -EINVAL;
  1645. }
  1646. return 0;
  1647. }
  1648. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1649. unsigned int fmt)
  1650. {
  1651. struct snd_soc_codec *codec = codec_dai->codec;
  1652. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1653. u8 old_format, format;
  1654. /* get format */
  1655. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1656. format = old_format;
  1657. /* set master/slave audio interface */
  1658. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1659. case SND_SOC_DAIFMT_CBM_CFM:
  1660. format &= ~(TWL4030_AIF_SLAVE_EN);
  1661. format &= ~(TWL4030_CLK256FS_EN);
  1662. break;
  1663. case SND_SOC_DAIFMT_CBS_CFS:
  1664. format |= TWL4030_AIF_SLAVE_EN;
  1665. format |= TWL4030_CLK256FS_EN;
  1666. break;
  1667. default:
  1668. return -EINVAL;
  1669. }
  1670. /* interface format */
  1671. format &= ~TWL4030_AIF_FORMAT;
  1672. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1673. case SND_SOC_DAIFMT_I2S:
  1674. format |= TWL4030_AIF_FORMAT_CODEC;
  1675. break;
  1676. case SND_SOC_DAIFMT_DSP_A:
  1677. format |= TWL4030_AIF_FORMAT_TDM;
  1678. break;
  1679. default:
  1680. return -EINVAL;
  1681. }
  1682. if (format != old_format) {
  1683. if (twl4030->codec_powered) {
  1684. /*
  1685. * If the codec is powered, than we need to toggle the
  1686. * codec power.
  1687. */
  1688. twl4030_codec_enable(codec, 0);
  1689. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1690. twl4030_codec_enable(codec, 1);
  1691. } else {
  1692. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1693. }
  1694. }
  1695. return 0;
  1696. }
  1697. static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
  1698. {
  1699. struct snd_soc_codec *codec = dai->codec;
  1700. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1701. if (tristate)
  1702. reg |= TWL4030_AIF_TRI_EN;
  1703. else
  1704. reg &= ~TWL4030_AIF_TRI_EN;
  1705. return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
  1706. }
  1707. /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
  1708. * (VTXL, VTXR) for uplink has to be enabled/disabled. */
  1709. static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
  1710. int enable)
  1711. {
  1712. u8 reg, mask;
  1713. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1714. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1715. mask = TWL4030_ARXL1_VRX_EN;
  1716. else
  1717. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1718. if (enable)
  1719. reg |= mask;
  1720. else
  1721. reg &= ~mask;
  1722. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1723. }
  1724. static int twl4030_voice_startup(struct snd_pcm_substream *substream,
  1725. struct snd_soc_dai *dai)
  1726. {
  1727. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1728. struct snd_soc_codec *codec = rtd->codec;
  1729. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1730. u8 mode;
  1731. /* If the system master clock is not 26MHz, the voice PCM interface is
  1732. * not avilable.
  1733. */
  1734. if (twl4030->sysclk != 26000) {
  1735. dev_err(codec->dev, "The board is configured for %u Hz, while"
  1736. "the Voice interface needs 26MHz APLL mclk\n",
  1737. twl4030->sysclk * 1000);
  1738. return -EINVAL;
  1739. }
  1740. /* If the codec mode is not option2, the voice PCM interface is not
  1741. * avilable.
  1742. */
  1743. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1744. & TWL4030_OPT_MODE;
  1745. if (mode != TWL4030_OPTION_2) {
  1746. printk(KERN_ERR "TWL4030 voice startup: "
  1747. "the codec mode is not option2\n");
  1748. return -EINVAL;
  1749. }
  1750. return 0;
  1751. }
  1752. static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
  1753. struct snd_soc_dai *dai)
  1754. {
  1755. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1756. struct snd_soc_codec *codec = rtd->codec;
  1757. /* Enable voice digital filters */
  1758. twl4030_voice_enable(codec, substream->stream, 0);
  1759. }
  1760. static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
  1761. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1762. {
  1763. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1764. struct snd_soc_codec *codec = rtd->codec;
  1765. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1766. u8 old_mode, mode;
  1767. /* Enable voice digital filters */
  1768. twl4030_voice_enable(codec, substream->stream, 1);
  1769. /* bit rate */
  1770. old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1771. & ~(TWL4030_CODECPDZ);
  1772. mode = old_mode;
  1773. switch (params_rate(params)) {
  1774. case 8000:
  1775. mode &= ~(TWL4030_SEL_16K);
  1776. break;
  1777. case 16000:
  1778. mode |= TWL4030_SEL_16K;
  1779. break;
  1780. default:
  1781. printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
  1782. params_rate(params));
  1783. return -EINVAL;
  1784. }
  1785. if (mode != old_mode) {
  1786. if (twl4030->codec_powered) {
  1787. /*
  1788. * If the codec is powered, than we need to toggle the
  1789. * codec power.
  1790. */
  1791. twl4030_codec_enable(codec, 0);
  1792. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1793. twl4030_codec_enable(codec, 1);
  1794. } else {
  1795. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1796. }
  1797. }
  1798. return 0;
  1799. }
  1800. static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1801. int clk_id, unsigned int freq, int dir)
  1802. {
  1803. struct snd_soc_codec *codec = codec_dai->codec;
  1804. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1805. if (freq != 26000000) {
  1806. dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice"
  1807. "interface needs 26MHz APLL mclk\n", freq);
  1808. return -EINVAL;
  1809. }
  1810. if ((freq / 1000) != twl4030->sysclk) {
  1811. dev_err(codec->dev,
  1812. "Mismatch in APLL mclk: %u (configured: %u)\n",
  1813. freq, twl4030->sysclk * 1000);
  1814. return -EINVAL;
  1815. }
  1816. return 0;
  1817. }
  1818. static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1819. unsigned int fmt)
  1820. {
  1821. struct snd_soc_codec *codec = codec_dai->codec;
  1822. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1823. u8 old_format, format;
  1824. /* get format */
  1825. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1826. format = old_format;
  1827. /* set master/slave audio interface */
  1828. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1829. case SND_SOC_DAIFMT_CBM_CFM:
  1830. format &= ~(TWL4030_VIF_SLAVE_EN);
  1831. break;
  1832. case SND_SOC_DAIFMT_CBS_CFS:
  1833. format |= TWL4030_VIF_SLAVE_EN;
  1834. break;
  1835. default:
  1836. return -EINVAL;
  1837. }
  1838. /* clock inversion */
  1839. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1840. case SND_SOC_DAIFMT_IB_NF:
  1841. format &= ~(TWL4030_VIF_FORMAT);
  1842. break;
  1843. case SND_SOC_DAIFMT_NB_IF:
  1844. format |= TWL4030_VIF_FORMAT;
  1845. break;
  1846. default:
  1847. return -EINVAL;
  1848. }
  1849. if (format != old_format) {
  1850. if (twl4030->codec_powered) {
  1851. /*
  1852. * If the codec is powered, than we need to toggle the
  1853. * codec power.
  1854. */
  1855. twl4030_codec_enable(codec, 0);
  1856. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1857. twl4030_codec_enable(codec, 1);
  1858. } else {
  1859. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1860. }
  1861. }
  1862. return 0;
  1863. }
  1864. static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
  1865. {
  1866. struct snd_soc_codec *codec = dai->codec;
  1867. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1868. if (tristate)
  1869. reg |= TWL4030_VIF_TRI_EN;
  1870. else
  1871. reg &= ~TWL4030_VIF_TRI_EN;
  1872. return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
  1873. }
  1874. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1875. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1876. static struct snd_soc_dai_ops twl4030_dai_hifi_ops = {
  1877. .startup = twl4030_startup,
  1878. .shutdown = twl4030_shutdown,
  1879. .hw_params = twl4030_hw_params,
  1880. .set_sysclk = twl4030_set_dai_sysclk,
  1881. .set_fmt = twl4030_set_dai_fmt,
  1882. .set_tristate = twl4030_set_tristate,
  1883. };
  1884. static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
  1885. .startup = twl4030_voice_startup,
  1886. .shutdown = twl4030_voice_shutdown,
  1887. .hw_params = twl4030_voice_hw_params,
  1888. .set_sysclk = twl4030_voice_set_dai_sysclk,
  1889. .set_fmt = twl4030_voice_set_dai_fmt,
  1890. .set_tristate = twl4030_voice_set_tristate,
  1891. };
  1892. static struct snd_soc_dai_driver twl4030_dai[] = {
  1893. {
  1894. .name = "twl4030-hifi",
  1895. .playback = {
  1896. .stream_name = "HiFi Playback",
  1897. .channels_min = 2,
  1898. .channels_max = 4,
  1899. .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
  1900. .formats = TWL4030_FORMATS,},
  1901. .capture = {
  1902. .stream_name = "Capture",
  1903. .channels_min = 2,
  1904. .channels_max = 4,
  1905. .rates = TWL4030_RATES,
  1906. .formats = TWL4030_FORMATS,},
  1907. .ops = &twl4030_dai_hifi_ops,
  1908. },
  1909. {
  1910. .name = "twl4030-voice",
  1911. .playback = {
  1912. .stream_name = "Voice Playback",
  1913. .channels_min = 1,
  1914. .channels_max = 1,
  1915. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1916. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1917. .capture = {
  1918. .stream_name = "Capture",
  1919. .channels_min = 1,
  1920. .channels_max = 2,
  1921. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1922. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1923. .ops = &twl4030_dai_voice_ops,
  1924. },
  1925. };
  1926. static int twl4030_soc_suspend(struct snd_soc_codec *codec, pm_message_t state)
  1927. {
  1928. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1929. return 0;
  1930. }
  1931. static int twl4030_soc_resume(struct snd_soc_codec *codec)
  1932. {
  1933. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1934. return 0;
  1935. }
  1936. static int twl4030_soc_probe(struct snd_soc_codec *codec)
  1937. {
  1938. struct twl4030_priv *twl4030;
  1939. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  1940. if (twl4030 == NULL) {
  1941. printk("Can not allocate memroy\n");
  1942. return -ENOMEM;
  1943. }
  1944. snd_soc_codec_set_drvdata(codec, twl4030);
  1945. /* Set the defaults, and power up the codec */
  1946. twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
  1947. codec->idle_bias_off = 1;
  1948. twl4030_init_chip(codec);
  1949. snd_soc_add_controls(codec, twl4030_snd_controls,
  1950. ARRAY_SIZE(twl4030_snd_controls));
  1951. twl4030_add_widgets(codec);
  1952. return 0;
  1953. }
  1954. static int twl4030_soc_remove(struct snd_soc_codec *codec)
  1955. {
  1956. /* Reset registers to their chip default before leaving */
  1957. twl4030_reset_registers(codec);
  1958. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1959. return 0;
  1960. }
  1961. static struct snd_soc_codec_driver soc_codec_dev_twl4030 = {
  1962. .probe = twl4030_soc_probe,
  1963. .remove = twl4030_soc_remove,
  1964. .suspend = twl4030_soc_suspend,
  1965. .resume = twl4030_soc_resume,
  1966. .read = twl4030_read_reg_cache,
  1967. .write = twl4030_write,
  1968. .set_bias_level = twl4030_set_bias_level,
  1969. .reg_cache_size = sizeof(twl4030_reg),
  1970. .reg_word_size = sizeof(u8),
  1971. .reg_cache_default = twl4030_reg,
  1972. };
  1973. static int __devinit twl4030_codec_probe(struct platform_device *pdev)
  1974. {
  1975. struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
  1976. if (!pdata) {
  1977. dev_err(&pdev->dev, "platform_data is missing\n");
  1978. return -EINVAL;
  1979. }
  1980. return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl4030,
  1981. twl4030_dai, ARRAY_SIZE(twl4030_dai));
  1982. }
  1983. static int __devexit twl4030_codec_remove(struct platform_device *pdev)
  1984. {
  1985. struct twl4030_priv *twl4030 = dev_get_drvdata(&pdev->dev);
  1986. snd_soc_unregister_codec(&pdev->dev);
  1987. kfree(twl4030);
  1988. return 0;
  1989. }
  1990. MODULE_ALIAS("platform:twl4030-codec");
  1991. static struct platform_driver twl4030_codec_driver = {
  1992. .probe = twl4030_codec_probe,
  1993. .remove = __devexit_p(twl4030_codec_remove),
  1994. .driver = {
  1995. .name = "twl4030-codec",
  1996. .owner = THIS_MODULE,
  1997. },
  1998. };
  1999. static int __init twl4030_modinit(void)
  2000. {
  2001. return platform_driver_register(&twl4030_codec_driver);
  2002. }
  2003. module_init(twl4030_modinit);
  2004. static void __exit twl4030_exit(void)
  2005. {
  2006. platform_driver_unregister(&twl4030_codec_driver);
  2007. }
  2008. module_exit(twl4030_exit);
  2009. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  2010. MODULE_AUTHOR("Steve Sakoman");
  2011. MODULE_LICENSE("GPL");