ak4642.c 12 KB

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  1. /*
  2. * ak4642.c -- AK4642/AK4643 ALSA Soc Audio driver
  3. *
  4. * Copyright (C) 2009 Renesas Solutions Corp.
  5. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  6. *
  7. * Based on wm8731.c by Richard Purdie
  8. * Based on ak4535.c by Richard Purdie
  9. * Based on wm8753.c by Liam Girdwood
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. /* ** CAUTION **
  16. *
  17. * This is very simple driver.
  18. * It can use headphone output / stereo input only
  19. *
  20. * AK4642 is not tested.
  21. * AK4643 is tested.
  22. */
  23. #include <linux/delay.h>
  24. #include <linux/i2c.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/slab.h>
  27. #include <sound/soc-dapm.h>
  28. #include <sound/initval.h>
  29. #include <sound/tlv.h>
  30. #define AK4642_VERSION "0.0.1"
  31. #define PW_MGMT1 0x00
  32. #define PW_MGMT2 0x01
  33. #define SG_SL1 0x02
  34. #define SG_SL2 0x03
  35. #define MD_CTL1 0x04
  36. #define MD_CTL2 0x05
  37. #define TIMER 0x06
  38. #define ALC_CTL1 0x07
  39. #define ALC_CTL2 0x08
  40. #define L_IVC 0x09
  41. #define L_DVC 0x0a
  42. #define ALC_CTL3 0x0b
  43. #define R_IVC 0x0c
  44. #define R_DVC 0x0d
  45. #define MD_CTL3 0x0e
  46. #define MD_CTL4 0x0f
  47. #define PW_MGMT3 0x10
  48. #define DF_S 0x11
  49. #define FIL3_0 0x12
  50. #define FIL3_1 0x13
  51. #define FIL3_2 0x14
  52. #define FIL3_3 0x15
  53. #define EQ_0 0x16
  54. #define EQ_1 0x17
  55. #define EQ_2 0x18
  56. #define EQ_3 0x19
  57. #define EQ_4 0x1a
  58. #define EQ_5 0x1b
  59. #define FIL1_0 0x1c
  60. #define FIL1_1 0x1d
  61. #define FIL1_2 0x1e
  62. #define FIL1_3 0x1f
  63. #define PW_MGMT4 0x20
  64. #define MD_CTL5 0x21
  65. #define LO_MS 0x22
  66. #define HP_MS 0x23
  67. #define SPK_MS 0x24
  68. #define AK4642_CACHEREGNUM 0x25
  69. /* PW_MGMT1*/
  70. #define PMVCM (1 << 6) /* VCOM Power Management */
  71. #define PMMIN (1 << 5) /* MIN Input Power Management */
  72. #define PMDAC (1 << 2) /* DAC Power Management */
  73. #define PMADL (1 << 0) /* MIC Amp Lch and ADC Lch Power Management */
  74. /* PW_MGMT2 */
  75. #define HPMTN (1 << 6)
  76. #define PMHPL (1 << 5)
  77. #define PMHPR (1 << 4)
  78. #define MS (1 << 3) /* master/slave select */
  79. #define MCKO (1 << 1)
  80. #define PMPLL (1 << 0)
  81. #define PMHP_MASK (PMHPL | PMHPR)
  82. #define PMHP PMHP_MASK
  83. /* PW_MGMT3 */
  84. #define PMADR (1 << 0) /* MIC L / ADC R Power Management */
  85. /* SG_SL1 */
  86. #define MINS (1 << 6) /* Switch from MIN to Speaker */
  87. #define DACL (1 << 4) /* Switch from DAC to Stereo or Receiver */
  88. #define PMMP (1 << 2) /* MPWR pin Power Management */
  89. #define MGAIN0 (1 << 0) /* MIC amp gain*/
  90. /* TIMER */
  91. #define ZTM(param) ((param & 0x3) << 4) /* ALC Zoro Crossing TimeOut */
  92. #define WTM(param) (((param & 0x4) << 4) | ((param & 0x3) << 2))
  93. /* ALC_CTL1 */
  94. #define ALC (1 << 5) /* ALC Enable */
  95. #define LMTH0 (1 << 0) /* ALC Limiter / Recovery Level */
  96. /* MD_CTL1 */
  97. #define PLL3 (1 << 7)
  98. #define PLL2 (1 << 6)
  99. #define PLL1 (1 << 5)
  100. #define PLL0 (1 << 4)
  101. #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
  102. #define BCKO_MASK (1 << 3)
  103. #define BCKO_64 BCKO_MASK
  104. /* MD_CTL2 */
  105. #define FS0 (1 << 0)
  106. #define FS1 (1 << 1)
  107. #define FS2 (1 << 2)
  108. #define FS3 (1 << 5)
  109. #define FS_MASK (FS0 | FS1 | FS2 | FS3)
  110. /* MD_CTL3 */
  111. #define BST1 (1 << 3)
  112. /* MD_CTL4 */
  113. #define DACH (1 << 0)
  114. /*
  115. * Playback Volume (table 39)
  116. *
  117. * max : 0x00 : +12.0 dB
  118. * ( 0.5 dB step )
  119. * min : 0xFE : -115.0 dB
  120. * mute: 0xFF
  121. */
  122. static const DECLARE_TLV_DB_SCALE(out_tlv, -11500, 50, 1);
  123. static const struct snd_kcontrol_new ak4642_snd_controls[] = {
  124. SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
  125. 0, 0xFF, 1, out_tlv),
  126. };
  127. /* codec private data */
  128. struct ak4642_priv {
  129. unsigned int sysclk;
  130. enum snd_soc_control_type control_type;
  131. void *control_data;
  132. };
  133. /*
  134. * ak4642 register cache
  135. */
  136. static const u16 ak4642_reg[AK4642_CACHEREGNUM] = {
  137. 0x0000, 0x0000, 0x0001, 0x0000,
  138. 0x0002, 0x0000, 0x0000, 0x0000,
  139. 0x00e1, 0x00e1, 0x0018, 0x0000,
  140. 0x00e1, 0x0018, 0x0011, 0x0008,
  141. 0x0000, 0x0000, 0x0000, 0x0000,
  142. 0x0000, 0x0000, 0x0000, 0x0000,
  143. 0x0000, 0x0000, 0x0000, 0x0000,
  144. 0x0000, 0x0000, 0x0000, 0x0000,
  145. 0x0000, 0x0000, 0x0000, 0x0000,
  146. 0x0000,
  147. };
  148. /*
  149. * read ak4642 register cache
  150. */
  151. static inline unsigned int ak4642_read_reg_cache(struct snd_soc_codec *codec,
  152. unsigned int reg)
  153. {
  154. u16 *cache = codec->reg_cache;
  155. if (reg >= AK4642_CACHEREGNUM)
  156. return -1;
  157. return cache[reg];
  158. }
  159. /*
  160. * write ak4642 register cache
  161. */
  162. static inline void ak4642_write_reg_cache(struct snd_soc_codec *codec,
  163. u16 reg, unsigned int value)
  164. {
  165. u16 *cache = codec->reg_cache;
  166. if (reg >= AK4642_CACHEREGNUM)
  167. return;
  168. cache[reg] = value;
  169. }
  170. /*
  171. * write to the AK4642 register space
  172. */
  173. static int ak4642_write(struct snd_soc_codec *codec, unsigned int reg,
  174. unsigned int value)
  175. {
  176. u8 data[2];
  177. /* data is
  178. * D15..D8 AK4642 register offset
  179. * D7...D0 register data
  180. */
  181. data[0] = reg & 0xff;
  182. data[1] = value & 0xff;
  183. if (codec->hw_write(codec->control_data, data, 2) == 2) {
  184. ak4642_write_reg_cache(codec, reg, value);
  185. return 0;
  186. } else
  187. return -EIO;
  188. }
  189. static int ak4642_sync(struct snd_soc_codec *codec)
  190. {
  191. u16 *cache = codec->reg_cache;
  192. int i, r = 0;
  193. for (i = 0; i < AK4642_CACHEREGNUM; i++)
  194. r |= ak4642_write(codec, i, cache[i]);
  195. return r;
  196. };
  197. static int ak4642_dai_startup(struct snd_pcm_substream *substream,
  198. struct snd_soc_dai *dai)
  199. {
  200. int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  201. struct snd_soc_codec *codec = dai->codec;
  202. if (is_play) {
  203. /*
  204. * start headphone output
  205. *
  206. * PLL, Master Mode
  207. * Audio I/F Format :MSB justified (ADC & DAC)
  208. * Bass Boost Level : Middle
  209. *
  210. * This operation came from example code of
  211. * "ASAHI KASEI AK4642" (japanese) manual p97.
  212. */
  213. snd_soc_update_bits(codec, MD_CTL4, DACH, DACH);
  214. snd_soc_update_bits(codec, MD_CTL3, BST1, BST1);
  215. ak4642_write(codec, L_IVC, 0x91); /* volume */
  216. ak4642_write(codec, R_IVC, 0x91); /* volume */
  217. snd_soc_update_bits(codec, PW_MGMT1, PMVCM | PMMIN | PMDAC,
  218. PMVCM | PMMIN | PMDAC);
  219. snd_soc_update_bits(codec, PW_MGMT2, PMHP_MASK, PMHP);
  220. snd_soc_update_bits(codec, PW_MGMT2, HPMTN, HPMTN);
  221. } else {
  222. /*
  223. * start stereo input
  224. *
  225. * PLL Master Mode
  226. * Audio I/F Format:MSB justified (ADC & DAC)
  227. * Pre MIC AMP:+20dB
  228. * MIC Power On
  229. * ALC setting:Refer to Table 35
  230. * ALC bit=“1”
  231. *
  232. * This operation came from example code of
  233. * "ASAHI KASEI AK4642" (japanese) manual p94.
  234. */
  235. ak4642_write(codec, SG_SL1, PMMP | MGAIN0);
  236. ak4642_write(codec, TIMER, ZTM(0x3) | WTM(0x3));
  237. ak4642_write(codec, ALC_CTL1, ALC | LMTH0);
  238. snd_soc_update_bits(codec, PW_MGMT1, PMVCM | PMADL,
  239. PMVCM | PMADL);
  240. snd_soc_update_bits(codec, PW_MGMT3, PMADR, PMADR);
  241. }
  242. return 0;
  243. }
  244. static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
  245. struct snd_soc_dai *dai)
  246. {
  247. int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  248. struct snd_soc_codec *codec = dai->codec;
  249. if (is_play) {
  250. /* stop headphone output */
  251. snd_soc_update_bits(codec, PW_MGMT2, HPMTN, 0);
  252. snd_soc_update_bits(codec, PW_MGMT2, PMHP_MASK, 0);
  253. snd_soc_update_bits(codec, PW_MGMT1, PMMIN | PMDAC, 0);
  254. snd_soc_update_bits(codec, MD_CTL3, BST1, 0);
  255. snd_soc_update_bits(codec, MD_CTL4, DACH, 0);
  256. } else {
  257. /* stop stereo input */
  258. snd_soc_update_bits(codec, PW_MGMT1, PMADL, 0);
  259. snd_soc_update_bits(codec, PW_MGMT3, PMADR, 0);
  260. snd_soc_update_bits(codec, ALC_CTL1, ALC, 0);
  261. }
  262. }
  263. static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
  264. int clk_id, unsigned int freq, int dir)
  265. {
  266. struct snd_soc_codec *codec = codec_dai->codec;
  267. u8 pll;
  268. switch (freq) {
  269. case 11289600:
  270. pll = PLL2;
  271. break;
  272. case 12288000:
  273. pll = PLL2 | PLL0;
  274. break;
  275. case 12000000:
  276. pll = PLL2 | PLL1;
  277. break;
  278. case 24000000:
  279. pll = PLL2 | PLL1 | PLL0;
  280. break;
  281. case 13500000:
  282. pll = PLL3 | PLL2;
  283. break;
  284. case 27000000:
  285. pll = PLL3 | PLL2 | PLL0;
  286. break;
  287. default:
  288. return -EINVAL;
  289. }
  290. snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll);
  291. return 0;
  292. }
  293. static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  294. {
  295. struct snd_soc_codec *codec = dai->codec;
  296. u8 data;
  297. u8 bcko;
  298. data = MCKO | PMPLL; /* use MCKO */
  299. bcko = 0;
  300. /* set master/slave audio interface */
  301. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  302. case SND_SOC_DAIFMT_CBM_CFM:
  303. data |= MS;
  304. bcko = BCKO_64;
  305. break;
  306. case SND_SOC_DAIFMT_CBS_CFS:
  307. break;
  308. default:
  309. return -EINVAL;
  310. }
  311. snd_soc_update_bits(codec, PW_MGMT2, MS, data);
  312. snd_soc_update_bits(codec, MD_CTL1, BCKO_MASK, bcko);
  313. return 0;
  314. }
  315. static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
  316. struct snd_pcm_hw_params *params,
  317. struct snd_soc_dai *dai)
  318. {
  319. struct snd_soc_codec *codec = dai->codec;
  320. u8 rate;
  321. switch (params_rate(params)) {
  322. case 7350:
  323. rate = FS2;
  324. break;
  325. case 8000:
  326. rate = 0;
  327. break;
  328. case 11025:
  329. rate = FS2 | FS0;
  330. break;
  331. case 12000:
  332. rate = FS0;
  333. break;
  334. case 14700:
  335. rate = FS2 | FS1;
  336. break;
  337. case 16000:
  338. rate = FS1;
  339. break;
  340. case 22050:
  341. rate = FS2 | FS1 | FS0;
  342. break;
  343. case 24000:
  344. rate = FS1 | FS0;
  345. break;
  346. case 29400:
  347. rate = FS3 | FS2 | FS1;
  348. break;
  349. case 32000:
  350. rate = FS3 | FS1;
  351. break;
  352. case 44100:
  353. rate = FS3 | FS2 | FS1 | FS0;
  354. break;
  355. case 48000:
  356. rate = FS3 | FS1 | FS0;
  357. break;
  358. default:
  359. return -EINVAL;
  360. break;
  361. }
  362. snd_soc_update_bits(codec, MD_CTL2, FS_MASK, rate);
  363. return 0;
  364. }
  365. static struct snd_soc_dai_ops ak4642_dai_ops = {
  366. .startup = ak4642_dai_startup,
  367. .shutdown = ak4642_dai_shutdown,
  368. .set_sysclk = ak4642_dai_set_sysclk,
  369. .set_fmt = ak4642_dai_set_fmt,
  370. .hw_params = ak4642_dai_hw_params,
  371. };
  372. static struct snd_soc_dai_driver ak4642_dai = {
  373. .name = "ak4642-hifi",
  374. .playback = {
  375. .stream_name = "Playback",
  376. .channels_min = 1,
  377. .channels_max = 2,
  378. .rates = SNDRV_PCM_RATE_8000_48000,
  379. .formats = SNDRV_PCM_FMTBIT_S16_LE },
  380. .capture = {
  381. .stream_name = "Capture",
  382. .channels_min = 1,
  383. .channels_max = 2,
  384. .rates = SNDRV_PCM_RATE_8000_48000,
  385. .formats = SNDRV_PCM_FMTBIT_S16_LE },
  386. .ops = &ak4642_dai_ops,
  387. .symmetric_rates = 1,
  388. };
  389. static int ak4642_resume(struct snd_soc_codec *codec)
  390. {
  391. ak4642_sync(codec);
  392. return 0;
  393. }
  394. static int ak4642_probe(struct snd_soc_codec *codec)
  395. {
  396. struct ak4642_priv *ak4642 = snd_soc_codec_get_drvdata(codec);
  397. dev_info(codec->dev, "AK4642 Audio Codec %s", AK4642_VERSION);
  398. codec->hw_write = (hw_write_t)i2c_master_send;
  399. codec->control_data = ak4642->control_data;
  400. snd_soc_add_controls(codec, ak4642_snd_controls,
  401. ARRAY_SIZE(ak4642_snd_controls));
  402. return 0;
  403. }
  404. static struct snd_soc_codec_driver soc_codec_dev_ak4642 = {
  405. .probe = ak4642_probe,
  406. .resume = ak4642_resume,
  407. .read = ak4642_read_reg_cache,
  408. .write = ak4642_write,
  409. .reg_cache_size = ARRAY_SIZE(ak4642_reg),
  410. .reg_word_size = sizeof(u8),
  411. .reg_cache_default = ak4642_reg,
  412. };
  413. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  414. static __devinit int ak4642_i2c_probe(struct i2c_client *i2c,
  415. const struct i2c_device_id *id)
  416. {
  417. struct ak4642_priv *ak4642;
  418. int ret;
  419. ak4642 = kzalloc(sizeof(struct ak4642_priv), GFP_KERNEL);
  420. if (!ak4642)
  421. return -ENOMEM;
  422. i2c_set_clientdata(i2c, ak4642);
  423. ak4642->control_data = i2c;
  424. ak4642->control_type = SND_SOC_I2C;
  425. ret = snd_soc_register_codec(&i2c->dev,
  426. &soc_codec_dev_ak4642, &ak4642_dai, 1);
  427. if (ret < 0)
  428. kfree(ak4642);
  429. return ret;
  430. }
  431. static __devexit int ak4642_i2c_remove(struct i2c_client *client)
  432. {
  433. snd_soc_unregister_codec(&client->dev);
  434. kfree(i2c_get_clientdata(client));
  435. return 0;
  436. }
  437. static const struct i2c_device_id ak4642_i2c_id[] = {
  438. { "ak4642", 0 },
  439. { "ak4643", 0 },
  440. { }
  441. };
  442. MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);
  443. static struct i2c_driver ak4642_i2c_driver = {
  444. .driver = {
  445. .name = "ak4642-codec",
  446. .owner = THIS_MODULE,
  447. },
  448. .probe = ak4642_i2c_probe,
  449. .remove = __devexit_p(ak4642_i2c_remove),
  450. .id_table = ak4642_i2c_id,
  451. };
  452. #endif
  453. static int __init ak4642_modinit(void)
  454. {
  455. int ret = 0;
  456. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  457. ret = i2c_add_driver(&ak4642_i2c_driver);
  458. #endif
  459. return ret;
  460. }
  461. module_init(ak4642_modinit);
  462. static void __exit ak4642_exit(void)
  463. {
  464. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  465. i2c_del_driver(&ak4642_i2c_driver);
  466. #endif
  467. }
  468. module_exit(ak4642_exit);
  469. MODULE_DESCRIPTION("Soc AK4642 driver");
  470. MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
  471. MODULE_LICENSE("GPL");