omap_wdt.c 10 KB

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  1. /*
  2. * omap_wdt.c
  3. *
  4. * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
  5. *
  6. * Author: MontaVista Software, Inc.
  7. * <gdavis@mvista.com> or <source@mvista.com>
  8. *
  9. * 2003 (c) MontaVista Software, Inc. This file is licensed under the
  10. * terms of the GNU General Public License version 2. This program is
  11. * licensed "as is" without any warranty of any kind, whether express
  12. * or implied.
  13. *
  14. * History:
  15. *
  16. * 20030527: George G. Davis <gdavis@mvista.com>
  17. * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
  18. * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
  19. * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
  20. *
  21. * Copyright (c) 2004 Texas Instruments.
  22. * 1. Modified to support OMAP1610 32-KHz watchdog timer
  23. * 2. Ported to 2.6 kernel
  24. *
  25. * Copyright (c) 2005 David Brownell
  26. * Use the driver model and standard identifiers; handle bigger timeouts.
  27. */
  28. #include <linux/module.h>
  29. #include <linux/types.h>
  30. #include <linux/kernel.h>
  31. #include <linux/fs.h>
  32. #include <linux/mm.h>
  33. #include <linux/miscdevice.h>
  34. #include <linux/watchdog.h>
  35. #include <linux/reboot.h>
  36. #include <linux/init.h>
  37. #include <linux/err.h>
  38. #include <linux/platform_device.h>
  39. #include <linux/moduleparam.h>
  40. #include <linux/bitops.h>
  41. #include <linux/io.h>
  42. #include <linux/uaccess.h>
  43. #include <linux/slab.h>
  44. #include <linux/pm_runtime.h>
  45. #include <mach/hardware.h>
  46. #include <plat/prcm.h>
  47. #include "omap_wdt.h"
  48. static struct platform_device *omap_wdt_dev;
  49. static unsigned timer_margin;
  50. module_param(timer_margin, uint, 0);
  51. MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
  52. static unsigned int wdt_trgr_pattern = 0x1234;
  53. static spinlock_t wdt_lock;
  54. struct omap_wdt_dev {
  55. void __iomem *base; /* physical */
  56. struct device *dev;
  57. int omap_wdt_users;
  58. struct resource *mem;
  59. struct miscdevice omap_wdt_miscdev;
  60. };
  61. static void omap_wdt_ping(struct omap_wdt_dev *wdev)
  62. {
  63. void __iomem *base = wdev->base;
  64. /* wait for posted write to complete */
  65. while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
  66. cpu_relax();
  67. wdt_trgr_pattern = ~wdt_trgr_pattern;
  68. __raw_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
  69. /* wait for posted write to complete */
  70. while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
  71. cpu_relax();
  72. /* reloaded WCRR from WLDR */
  73. }
  74. static void omap_wdt_enable(struct omap_wdt_dev *wdev)
  75. {
  76. void __iomem *base = wdev->base;
  77. /* Sequence to enable the watchdog */
  78. __raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR);
  79. while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
  80. cpu_relax();
  81. __raw_writel(0x4444, base + OMAP_WATCHDOG_SPR);
  82. while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
  83. cpu_relax();
  84. }
  85. static void omap_wdt_disable(struct omap_wdt_dev *wdev)
  86. {
  87. void __iomem *base = wdev->base;
  88. /* sequence required to disable watchdog */
  89. __raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
  90. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
  91. cpu_relax();
  92. __raw_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
  93. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
  94. cpu_relax();
  95. }
  96. static void omap_wdt_adjust_timeout(unsigned new_timeout)
  97. {
  98. if (new_timeout < TIMER_MARGIN_MIN)
  99. new_timeout = TIMER_MARGIN_DEFAULT;
  100. if (new_timeout > TIMER_MARGIN_MAX)
  101. new_timeout = TIMER_MARGIN_MAX;
  102. timer_margin = new_timeout;
  103. }
  104. static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev)
  105. {
  106. u32 pre_margin = GET_WLDR_VAL(timer_margin);
  107. void __iomem *base = wdev->base;
  108. /* just count up at 32 KHz */
  109. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
  110. cpu_relax();
  111. __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
  112. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
  113. cpu_relax();
  114. }
  115. /*
  116. * Allow only one task to hold it open
  117. */
  118. static int omap_wdt_open(struct inode *inode, struct file *file)
  119. {
  120. struct omap_wdt_dev *wdev = platform_get_drvdata(omap_wdt_dev);
  121. void __iomem *base = wdev->base;
  122. if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users)))
  123. return -EBUSY;
  124. pm_runtime_get_sync(wdev->dev);
  125. /* initialize prescaler */
  126. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
  127. cpu_relax();
  128. __raw_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
  129. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
  130. cpu_relax();
  131. file->private_data = (void *) wdev;
  132. omap_wdt_set_timeout(wdev);
  133. omap_wdt_ping(wdev); /* trigger loading of new timeout value */
  134. omap_wdt_enable(wdev);
  135. return nonseekable_open(inode, file);
  136. }
  137. static int omap_wdt_release(struct inode *inode, struct file *file)
  138. {
  139. struct omap_wdt_dev *wdev = file->private_data;
  140. /*
  141. * Shut off the timer unless NOWAYOUT is defined.
  142. */
  143. #ifndef CONFIG_WATCHDOG_NOWAYOUT
  144. omap_wdt_disable(wdev);
  145. pm_runtime_put_sync(wdev->dev);
  146. #else
  147. printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n");
  148. #endif
  149. wdev->omap_wdt_users = 0;
  150. return 0;
  151. }
  152. static ssize_t omap_wdt_write(struct file *file, const char __user *data,
  153. size_t len, loff_t *ppos)
  154. {
  155. struct omap_wdt_dev *wdev = file->private_data;
  156. /* Refresh LOAD_TIME. */
  157. if (len) {
  158. spin_lock(&wdt_lock);
  159. omap_wdt_ping(wdev);
  160. spin_unlock(&wdt_lock);
  161. }
  162. return len;
  163. }
  164. static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
  165. unsigned long arg)
  166. {
  167. struct omap_wdt_dev *wdev;
  168. int new_margin;
  169. static const struct watchdog_info ident = {
  170. .identity = "OMAP Watchdog",
  171. .options = WDIOF_SETTIMEOUT,
  172. .firmware_version = 0,
  173. };
  174. wdev = file->private_data;
  175. switch (cmd) {
  176. case WDIOC_GETSUPPORT:
  177. return copy_to_user((struct watchdog_info __user *)arg, &ident,
  178. sizeof(ident));
  179. case WDIOC_GETSTATUS:
  180. return put_user(0, (int __user *)arg);
  181. case WDIOC_GETBOOTSTATUS:
  182. if (cpu_is_omap16xx())
  183. return put_user(__raw_readw(ARM_SYSST),
  184. (int __user *)arg);
  185. if (cpu_is_omap24xx())
  186. return put_user(omap_prcm_get_reset_sources(),
  187. (int __user *)arg);
  188. case WDIOC_KEEPALIVE:
  189. spin_lock(&wdt_lock);
  190. omap_wdt_ping(wdev);
  191. spin_unlock(&wdt_lock);
  192. return 0;
  193. case WDIOC_SETTIMEOUT:
  194. if (get_user(new_margin, (int __user *)arg))
  195. return -EFAULT;
  196. omap_wdt_adjust_timeout(new_margin);
  197. spin_lock(&wdt_lock);
  198. omap_wdt_disable(wdev);
  199. omap_wdt_set_timeout(wdev);
  200. omap_wdt_enable(wdev);
  201. omap_wdt_ping(wdev);
  202. spin_unlock(&wdt_lock);
  203. /* Fall */
  204. case WDIOC_GETTIMEOUT:
  205. return put_user(timer_margin, (int __user *)arg);
  206. default:
  207. return -ENOTTY;
  208. }
  209. }
  210. static const struct file_operations omap_wdt_fops = {
  211. .owner = THIS_MODULE,
  212. .write = omap_wdt_write,
  213. .unlocked_ioctl = omap_wdt_ioctl,
  214. .open = omap_wdt_open,
  215. .release = omap_wdt_release,
  216. .llseek = no_llseek,
  217. };
  218. static int __devinit omap_wdt_probe(struct platform_device *pdev)
  219. {
  220. struct resource *res, *mem;
  221. struct omap_wdt_dev *wdev;
  222. int ret;
  223. /* reserve static register mappings */
  224. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  225. if (!res) {
  226. ret = -ENOENT;
  227. goto err_get_resource;
  228. }
  229. if (omap_wdt_dev) {
  230. ret = -EBUSY;
  231. goto err_busy;
  232. }
  233. mem = request_mem_region(res->start, resource_size(res), pdev->name);
  234. if (!mem) {
  235. ret = -EBUSY;
  236. goto err_busy;
  237. }
  238. wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL);
  239. if (!wdev) {
  240. ret = -ENOMEM;
  241. goto err_kzalloc;
  242. }
  243. wdev->omap_wdt_users = 0;
  244. wdev->mem = mem;
  245. wdev->dev = &pdev->dev;
  246. wdev->base = ioremap(res->start, resource_size(res));
  247. if (!wdev->base) {
  248. ret = -ENOMEM;
  249. goto err_ioremap;
  250. }
  251. platform_set_drvdata(pdev, wdev);
  252. pm_runtime_enable(wdev->dev);
  253. pm_runtime_get_sync(wdev->dev);
  254. omap_wdt_disable(wdev);
  255. omap_wdt_adjust_timeout(timer_margin);
  256. wdev->omap_wdt_miscdev.parent = &pdev->dev;
  257. wdev->omap_wdt_miscdev.minor = WATCHDOG_MINOR;
  258. wdev->omap_wdt_miscdev.name = "watchdog";
  259. wdev->omap_wdt_miscdev.fops = &omap_wdt_fops;
  260. ret = misc_register(&(wdev->omap_wdt_miscdev));
  261. if (ret)
  262. goto err_misc;
  263. pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
  264. __raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
  265. timer_margin);
  266. pm_runtime_put_sync(wdev->dev);
  267. omap_wdt_dev = pdev;
  268. return 0;
  269. err_misc:
  270. platform_set_drvdata(pdev, NULL);
  271. iounmap(wdev->base);
  272. err_ioremap:
  273. wdev->base = NULL;
  274. kfree(wdev);
  275. err_kzalloc:
  276. release_mem_region(res->start, resource_size(res));
  277. err_busy:
  278. err_get_resource:
  279. return ret;
  280. }
  281. static void omap_wdt_shutdown(struct platform_device *pdev)
  282. {
  283. struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
  284. if (wdev->omap_wdt_users)
  285. omap_wdt_disable(wdev);
  286. }
  287. static int __devexit omap_wdt_remove(struct platform_device *pdev)
  288. {
  289. struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
  290. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  291. if (!res)
  292. return -ENOENT;
  293. misc_deregister(&(wdev->omap_wdt_miscdev));
  294. release_mem_region(res->start, resource_size(res));
  295. platform_set_drvdata(pdev, NULL);
  296. iounmap(wdev->base);
  297. kfree(wdev);
  298. omap_wdt_dev = NULL;
  299. return 0;
  300. }
  301. #ifdef CONFIG_PM
  302. /* REVISIT ... not clear this is the best way to handle system suspend; and
  303. * it's very inappropriate for selective device suspend (e.g. suspending this
  304. * through sysfs rather than by stopping the watchdog daemon). Also, this
  305. * may not play well enough with NOWAYOUT...
  306. */
  307. static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
  308. {
  309. struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
  310. if (wdev->omap_wdt_users)
  311. omap_wdt_disable(wdev);
  312. return 0;
  313. }
  314. static int omap_wdt_resume(struct platform_device *pdev)
  315. {
  316. struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
  317. if (wdev->omap_wdt_users) {
  318. omap_wdt_enable(wdev);
  319. omap_wdt_ping(wdev);
  320. }
  321. return 0;
  322. }
  323. #else
  324. #define omap_wdt_suspend NULL
  325. #define omap_wdt_resume NULL
  326. #endif
  327. static struct platform_driver omap_wdt_driver = {
  328. .probe = omap_wdt_probe,
  329. .remove = __devexit_p(omap_wdt_remove),
  330. .shutdown = omap_wdt_shutdown,
  331. .suspend = omap_wdt_suspend,
  332. .resume = omap_wdt_resume,
  333. .driver = {
  334. .owner = THIS_MODULE,
  335. .name = "omap_wdt",
  336. },
  337. };
  338. static int __init omap_wdt_init(void)
  339. {
  340. spin_lock_init(&wdt_lock);
  341. return platform_driver_register(&omap_wdt_driver);
  342. }
  343. static void __exit omap_wdt_exit(void)
  344. {
  345. platform_driver_unregister(&omap_wdt_driver);
  346. }
  347. module_init(omap_wdt_init);
  348. module_exit(omap_wdt_exit);
  349. MODULE_AUTHOR("George G. Davis");
  350. MODULE_LICENSE("GPL");
  351. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
  352. MODULE_ALIAS("platform:omap_wdt");