atmel_usba_udc.c 50 KB

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  1. /*
  2. * Driver for the Atmel USBA high speed USB device controller
  3. *
  4. * Copyright (C) 2005-2007 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/slab.h>
  16. #include <linux/device.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/list.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/usb/ch9.h>
  21. #include <linux/usb/gadget.h>
  22. #include <linux/usb/atmel_usba_udc.h>
  23. #include <linux/delay.h>
  24. #include <asm/gpio.h>
  25. #include <mach/board.h>
  26. #include "atmel_usba_udc.h"
  27. static struct usba_udc the_udc;
  28. static struct usba_ep *usba_ep;
  29. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  30. #include <linux/debugfs.h>
  31. #include <linux/uaccess.h>
  32. static int queue_dbg_open(struct inode *inode, struct file *file)
  33. {
  34. struct usba_ep *ep = inode->i_private;
  35. struct usba_request *req, *req_copy;
  36. struct list_head *queue_data;
  37. queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
  38. if (!queue_data)
  39. return -ENOMEM;
  40. INIT_LIST_HEAD(queue_data);
  41. spin_lock_irq(&ep->udc->lock);
  42. list_for_each_entry(req, &ep->queue, queue) {
  43. req_copy = kmemdup(req, sizeof(*req_copy), GFP_ATOMIC);
  44. if (!req_copy)
  45. goto fail;
  46. list_add_tail(&req_copy->queue, queue_data);
  47. }
  48. spin_unlock_irq(&ep->udc->lock);
  49. file->private_data = queue_data;
  50. return 0;
  51. fail:
  52. spin_unlock_irq(&ep->udc->lock);
  53. list_for_each_entry_safe(req, req_copy, queue_data, queue) {
  54. list_del(&req->queue);
  55. kfree(req);
  56. }
  57. kfree(queue_data);
  58. return -ENOMEM;
  59. }
  60. /*
  61. * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
  62. *
  63. * b: buffer address
  64. * l: buffer length
  65. * I/i: interrupt/no interrupt
  66. * Z/z: zero/no zero
  67. * S/s: short ok/short not ok
  68. * s: status
  69. * n: nr_packets
  70. * F/f: submitted/not submitted to FIFO
  71. * D/d: using/not using DMA
  72. * L/l: last transaction/not last transaction
  73. */
  74. static ssize_t queue_dbg_read(struct file *file, char __user *buf,
  75. size_t nbytes, loff_t *ppos)
  76. {
  77. struct list_head *queue = file->private_data;
  78. struct usba_request *req, *tmp_req;
  79. size_t len, remaining, actual = 0;
  80. char tmpbuf[38];
  81. if (!access_ok(VERIFY_WRITE, buf, nbytes))
  82. return -EFAULT;
  83. mutex_lock(&file->f_dentry->d_inode->i_mutex);
  84. list_for_each_entry_safe(req, tmp_req, queue, queue) {
  85. len = snprintf(tmpbuf, sizeof(tmpbuf),
  86. "%8p %08x %c%c%c %5d %c%c%c\n",
  87. req->req.buf, req->req.length,
  88. req->req.no_interrupt ? 'i' : 'I',
  89. req->req.zero ? 'Z' : 'z',
  90. req->req.short_not_ok ? 's' : 'S',
  91. req->req.status,
  92. req->submitted ? 'F' : 'f',
  93. req->using_dma ? 'D' : 'd',
  94. req->last_transaction ? 'L' : 'l');
  95. len = min(len, sizeof(tmpbuf));
  96. if (len > nbytes)
  97. break;
  98. list_del(&req->queue);
  99. kfree(req);
  100. remaining = __copy_to_user(buf, tmpbuf, len);
  101. actual += len - remaining;
  102. if (remaining)
  103. break;
  104. nbytes -= len;
  105. buf += len;
  106. }
  107. mutex_unlock(&file->f_dentry->d_inode->i_mutex);
  108. return actual;
  109. }
  110. static int queue_dbg_release(struct inode *inode, struct file *file)
  111. {
  112. struct list_head *queue_data = file->private_data;
  113. struct usba_request *req, *tmp_req;
  114. list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
  115. list_del(&req->queue);
  116. kfree(req);
  117. }
  118. kfree(queue_data);
  119. return 0;
  120. }
  121. static int regs_dbg_open(struct inode *inode, struct file *file)
  122. {
  123. struct usba_udc *udc;
  124. unsigned int i;
  125. u32 *data;
  126. int ret = -ENOMEM;
  127. mutex_lock(&inode->i_mutex);
  128. udc = inode->i_private;
  129. data = kmalloc(inode->i_size, GFP_KERNEL);
  130. if (!data)
  131. goto out;
  132. spin_lock_irq(&udc->lock);
  133. for (i = 0; i < inode->i_size / 4; i++)
  134. data[i] = __raw_readl(udc->regs + i * 4);
  135. spin_unlock_irq(&udc->lock);
  136. file->private_data = data;
  137. ret = 0;
  138. out:
  139. mutex_unlock(&inode->i_mutex);
  140. return ret;
  141. }
  142. static ssize_t regs_dbg_read(struct file *file, char __user *buf,
  143. size_t nbytes, loff_t *ppos)
  144. {
  145. struct inode *inode = file->f_dentry->d_inode;
  146. int ret;
  147. mutex_lock(&inode->i_mutex);
  148. ret = simple_read_from_buffer(buf, nbytes, ppos,
  149. file->private_data,
  150. file->f_dentry->d_inode->i_size);
  151. mutex_unlock(&inode->i_mutex);
  152. return ret;
  153. }
  154. static int regs_dbg_release(struct inode *inode, struct file *file)
  155. {
  156. kfree(file->private_data);
  157. return 0;
  158. }
  159. const struct file_operations queue_dbg_fops = {
  160. .owner = THIS_MODULE,
  161. .open = queue_dbg_open,
  162. .llseek = no_llseek,
  163. .read = queue_dbg_read,
  164. .release = queue_dbg_release,
  165. };
  166. const struct file_operations regs_dbg_fops = {
  167. .owner = THIS_MODULE,
  168. .open = regs_dbg_open,
  169. .llseek = generic_file_llseek,
  170. .read = regs_dbg_read,
  171. .release = regs_dbg_release,
  172. };
  173. static void usba_ep_init_debugfs(struct usba_udc *udc,
  174. struct usba_ep *ep)
  175. {
  176. struct dentry *ep_root;
  177. ep_root = debugfs_create_dir(ep->ep.name, udc->debugfs_root);
  178. if (!ep_root)
  179. goto err_root;
  180. ep->debugfs_dir = ep_root;
  181. ep->debugfs_queue = debugfs_create_file("queue", 0400, ep_root,
  182. ep, &queue_dbg_fops);
  183. if (!ep->debugfs_queue)
  184. goto err_queue;
  185. if (ep->can_dma) {
  186. ep->debugfs_dma_status
  187. = debugfs_create_u32("dma_status", 0400, ep_root,
  188. &ep->last_dma_status);
  189. if (!ep->debugfs_dma_status)
  190. goto err_dma_status;
  191. }
  192. if (ep_is_control(ep)) {
  193. ep->debugfs_state
  194. = debugfs_create_u32("state", 0400, ep_root,
  195. &ep->state);
  196. if (!ep->debugfs_state)
  197. goto err_state;
  198. }
  199. return;
  200. err_state:
  201. if (ep->can_dma)
  202. debugfs_remove(ep->debugfs_dma_status);
  203. err_dma_status:
  204. debugfs_remove(ep->debugfs_queue);
  205. err_queue:
  206. debugfs_remove(ep_root);
  207. err_root:
  208. dev_err(&ep->udc->pdev->dev,
  209. "failed to create debugfs directory for %s\n", ep->ep.name);
  210. }
  211. static void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  212. {
  213. debugfs_remove(ep->debugfs_queue);
  214. debugfs_remove(ep->debugfs_dma_status);
  215. debugfs_remove(ep->debugfs_state);
  216. debugfs_remove(ep->debugfs_dir);
  217. ep->debugfs_dma_status = NULL;
  218. ep->debugfs_dir = NULL;
  219. }
  220. static void usba_init_debugfs(struct usba_udc *udc)
  221. {
  222. struct dentry *root, *regs;
  223. struct resource *regs_resource;
  224. root = debugfs_create_dir(udc->gadget.name, NULL);
  225. if (IS_ERR(root) || !root)
  226. goto err_root;
  227. udc->debugfs_root = root;
  228. regs = debugfs_create_file("regs", 0400, root, udc, &regs_dbg_fops);
  229. if (!regs)
  230. goto err_regs;
  231. regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
  232. CTRL_IOMEM_ID);
  233. regs->d_inode->i_size = regs_resource->end - regs_resource->start + 1;
  234. udc->debugfs_regs = regs;
  235. usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0));
  236. return;
  237. err_regs:
  238. debugfs_remove(root);
  239. err_root:
  240. udc->debugfs_root = NULL;
  241. dev_err(&udc->pdev->dev, "debugfs is not available\n");
  242. }
  243. static void usba_cleanup_debugfs(struct usba_udc *udc)
  244. {
  245. usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0));
  246. debugfs_remove(udc->debugfs_regs);
  247. debugfs_remove(udc->debugfs_root);
  248. udc->debugfs_regs = NULL;
  249. udc->debugfs_root = NULL;
  250. }
  251. #else
  252. static inline void usba_ep_init_debugfs(struct usba_udc *udc,
  253. struct usba_ep *ep)
  254. {
  255. }
  256. static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  257. {
  258. }
  259. static inline void usba_init_debugfs(struct usba_udc *udc)
  260. {
  261. }
  262. static inline void usba_cleanup_debugfs(struct usba_udc *udc)
  263. {
  264. }
  265. #endif
  266. static int vbus_is_present(struct usba_udc *udc)
  267. {
  268. if (gpio_is_valid(udc->vbus_pin))
  269. return gpio_get_value(udc->vbus_pin) ^ udc->vbus_pin_inverted;
  270. /* No Vbus detection: Assume always present */
  271. return 1;
  272. }
  273. #if defined(CONFIG_ARCH_AT91SAM9RL)
  274. #include <mach/at91_pmc.h>
  275. static void toggle_bias(int is_on)
  276. {
  277. unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
  278. if (is_on)
  279. at91_sys_write(AT91_CKGR_UCKR, uckr | AT91_PMC_BIASEN);
  280. else
  281. at91_sys_write(AT91_CKGR_UCKR, uckr & ~(AT91_PMC_BIASEN));
  282. }
  283. #else
  284. static void toggle_bias(int is_on)
  285. {
  286. }
  287. #endif /* CONFIG_ARCH_AT91SAM9RL */
  288. static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
  289. {
  290. unsigned int transaction_len;
  291. transaction_len = req->req.length - req->req.actual;
  292. req->last_transaction = 1;
  293. if (transaction_len > ep->ep.maxpacket) {
  294. transaction_len = ep->ep.maxpacket;
  295. req->last_transaction = 0;
  296. } else if (transaction_len == ep->ep.maxpacket && req->req.zero)
  297. req->last_transaction = 0;
  298. DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
  299. ep->ep.name, req, transaction_len,
  300. req->last_transaction ? ", done" : "");
  301. memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
  302. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  303. req->req.actual += transaction_len;
  304. }
  305. static void submit_request(struct usba_ep *ep, struct usba_request *req)
  306. {
  307. DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
  308. ep->ep.name, req, req->req.length);
  309. req->req.actual = 0;
  310. req->submitted = 1;
  311. if (req->using_dma) {
  312. if (req->req.length == 0) {
  313. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  314. return;
  315. }
  316. if (req->req.zero)
  317. usba_ep_writel(ep, CTL_ENB, USBA_SHORT_PACKET);
  318. else
  319. usba_ep_writel(ep, CTL_DIS, USBA_SHORT_PACKET);
  320. usba_dma_writel(ep, ADDRESS, req->req.dma);
  321. usba_dma_writel(ep, CONTROL, req->ctrl);
  322. } else {
  323. next_fifo_transaction(ep, req);
  324. if (req->last_transaction) {
  325. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  326. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  327. } else {
  328. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  329. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  330. }
  331. }
  332. }
  333. static void submit_next_request(struct usba_ep *ep)
  334. {
  335. struct usba_request *req;
  336. if (list_empty(&ep->queue)) {
  337. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY | USBA_RX_BK_RDY);
  338. return;
  339. }
  340. req = list_entry(ep->queue.next, struct usba_request, queue);
  341. if (!req->submitted)
  342. submit_request(ep, req);
  343. }
  344. static void send_status(struct usba_udc *udc, struct usba_ep *ep)
  345. {
  346. ep->state = STATUS_STAGE_IN;
  347. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  348. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  349. }
  350. static void receive_data(struct usba_ep *ep)
  351. {
  352. struct usba_udc *udc = ep->udc;
  353. struct usba_request *req;
  354. unsigned long status;
  355. unsigned int bytecount, nr_busy;
  356. int is_complete = 0;
  357. status = usba_ep_readl(ep, STA);
  358. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  359. DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
  360. while (nr_busy > 0) {
  361. if (list_empty(&ep->queue)) {
  362. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  363. break;
  364. }
  365. req = list_entry(ep->queue.next,
  366. struct usba_request, queue);
  367. bytecount = USBA_BFEXT(BYTE_COUNT, status);
  368. if (status & (1 << 31))
  369. is_complete = 1;
  370. if (req->req.actual + bytecount >= req->req.length) {
  371. is_complete = 1;
  372. bytecount = req->req.length - req->req.actual;
  373. }
  374. memcpy_fromio(req->req.buf + req->req.actual,
  375. ep->fifo, bytecount);
  376. req->req.actual += bytecount;
  377. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  378. if (is_complete) {
  379. DBG(DBG_QUEUE, "%s: request done\n", ep->ep.name);
  380. req->req.status = 0;
  381. list_del_init(&req->queue);
  382. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  383. spin_unlock(&udc->lock);
  384. req->req.complete(&ep->ep, &req->req);
  385. spin_lock(&udc->lock);
  386. }
  387. status = usba_ep_readl(ep, STA);
  388. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  389. if (is_complete && ep_is_control(ep)) {
  390. send_status(udc, ep);
  391. break;
  392. }
  393. }
  394. }
  395. static void
  396. request_complete(struct usba_ep *ep, struct usba_request *req, int status)
  397. {
  398. struct usba_udc *udc = ep->udc;
  399. WARN_ON(!list_empty(&req->queue));
  400. if (req->req.status == -EINPROGRESS)
  401. req->req.status = status;
  402. if (req->mapped) {
  403. dma_unmap_single(
  404. &udc->pdev->dev, req->req.dma, req->req.length,
  405. ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  406. req->req.dma = DMA_ADDR_INVALID;
  407. req->mapped = 0;
  408. }
  409. DBG(DBG_GADGET | DBG_REQ,
  410. "%s: req %p complete: status %d, actual %u\n",
  411. ep->ep.name, req, req->req.status, req->req.actual);
  412. spin_unlock(&udc->lock);
  413. req->req.complete(&ep->ep, &req->req);
  414. spin_lock(&udc->lock);
  415. }
  416. static void
  417. request_complete_list(struct usba_ep *ep, struct list_head *list, int status)
  418. {
  419. struct usba_request *req, *tmp_req;
  420. list_for_each_entry_safe(req, tmp_req, list, queue) {
  421. list_del_init(&req->queue);
  422. request_complete(ep, req, status);
  423. }
  424. }
  425. static int
  426. usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
  427. {
  428. struct usba_ep *ep = to_usba_ep(_ep);
  429. struct usba_udc *udc = ep->udc;
  430. unsigned long flags, ept_cfg, maxpacket;
  431. unsigned int nr_trans;
  432. DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep->ep.name, desc);
  433. maxpacket = le16_to_cpu(desc->wMaxPacketSize) & 0x7ff;
  434. if (((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != ep->index)
  435. || ep->index == 0
  436. || desc->bDescriptorType != USB_DT_ENDPOINT
  437. || maxpacket == 0
  438. || maxpacket > ep->fifo_size) {
  439. DBG(DBG_ERR, "ep_enable: Invalid argument");
  440. return -EINVAL;
  441. }
  442. ep->is_isoc = 0;
  443. ep->is_in = 0;
  444. if (maxpacket <= 8)
  445. ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
  446. else
  447. /* LSB is bit 1, not 0 */
  448. ept_cfg = USBA_BF(EPT_SIZE, fls(maxpacket - 1) - 3);
  449. DBG(DBG_HW, "%s: EPT_SIZE = %lu (maxpacket = %lu)\n",
  450. ep->ep.name, ept_cfg, maxpacket);
  451. if (usb_endpoint_dir_in(desc)) {
  452. ep->is_in = 1;
  453. ept_cfg |= USBA_EPT_DIR_IN;
  454. }
  455. switch (usb_endpoint_type(desc)) {
  456. case USB_ENDPOINT_XFER_CONTROL:
  457. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
  458. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE);
  459. break;
  460. case USB_ENDPOINT_XFER_ISOC:
  461. if (!ep->can_isoc) {
  462. DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
  463. ep->ep.name);
  464. return -EINVAL;
  465. }
  466. /*
  467. * Bits 11:12 specify number of _additional_
  468. * transactions per microframe.
  469. */
  470. nr_trans = ((le16_to_cpu(desc->wMaxPacketSize) >> 11) & 3) + 1;
  471. if (nr_trans > 3)
  472. return -EINVAL;
  473. ep->is_isoc = 1;
  474. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO);
  475. /*
  476. * Do triple-buffering on high-bandwidth iso endpoints.
  477. */
  478. if (nr_trans > 1 && ep->nr_banks == 3)
  479. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_TRIPLE);
  480. else
  481. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  482. ept_cfg |= USBA_BF(NB_TRANS, nr_trans);
  483. break;
  484. case USB_ENDPOINT_XFER_BULK:
  485. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK);
  486. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  487. break;
  488. case USB_ENDPOINT_XFER_INT:
  489. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT);
  490. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  491. break;
  492. }
  493. spin_lock_irqsave(&ep->udc->lock, flags);
  494. if (ep->desc) {
  495. spin_unlock_irqrestore(&ep->udc->lock, flags);
  496. DBG(DBG_ERR, "ep%d already enabled\n", ep->index);
  497. return -EBUSY;
  498. }
  499. ep->desc = desc;
  500. ep->ep.maxpacket = maxpacket;
  501. usba_ep_writel(ep, CFG, ept_cfg);
  502. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  503. if (ep->can_dma) {
  504. u32 ctrl;
  505. usba_writel(udc, INT_ENB,
  506. (usba_readl(udc, INT_ENB)
  507. | USBA_BF(EPT_INT, 1 << ep->index)
  508. | USBA_BF(DMA_INT, 1 << ep->index)));
  509. ctrl = USBA_AUTO_VALID | USBA_INTDIS_DMA;
  510. usba_ep_writel(ep, CTL_ENB, ctrl);
  511. } else {
  512. usba_writel(udc, INT_ENB,
  513. (usba_readl(udc, INT_ENB)
  514. | USBA_BF(EPT_INT, 1 << ep->index)));
  515. }
  516. spin_unlock_irqrestore(&udc->lock, flags);
  517. DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
  518. (unsigned long)usba_ep_readl(ep, CFG));
  519. DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
  520. (unsigned long)usba_readl(udc, INT_ENB));
  521. return 0;
  522. }
  523. static int usba_ep_disable(struct usb_ep *_ep)
  524. {
  525. struct usba_ep *ep = to_usba_ep(_ep);
  526. struct usba_udc *udc = ep->udc;
  527. LIST_HEAD(req_list);
  528. unsigned long flags;
  529. DBG(DBG_GADGET, "ep_disable: %s\n", ep->ep.name);
  530. spin_lock_irqsave(&udc->lock, flags);
  531. if (!ep->desc) {
  532. spin_unlock_irqrestore(&udc->lock, flags);
  533. /* REVISIT because this driver disables endpoints in
  534. * reset_all_endpoints() before calling disconnect(),
  535. * most gadget drivers would trigger this non-error ...
  536. */
  537. if (udc->gadget.speed != USB_SPEED_UNKNOWN)
  538. DBG(DBG_ERR, "ep_disable: %s not enabled\n",
  539. ep->ep.name);
  540. return -EINVAL;
  541. }
  542. ep->desc = NULL;
  543. list_splice_init(&ep->queue, &req_list);
  544. if (ep->can_dma) {
  545. usba_dma_writel(ep, CONTROL, 0);
  546. usba_dma_writel(ep, ADDRESS, 0);
  547. usba_dma_readl(ep, STATUS);
  548. }
  549. usba_ep_writel(ep, CTL_DIS, USBA_EPT_ENABLE);
  550. usba_writel(udc, INT_ENB,
  551. usba_readl(udc, INT_ENB)
  552. & ~USBA_BF(EPT_INT, 1 << ep->index));
  553. request_complete_list(ep, &req_list, -ESHUTDOWN);
  554. spin_unlock_irqrestore(&udc->lock, flags);
  555. return 0;
  556. }
  557. static struct usb_request *
  558. usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
  559. {
  560. struct usba_request *req;
  561. DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
  562. req = kzalloc(sizeof(*req), gfp_flags);
  563. if (!req)
  564. return NULL;
  565. INIT_LIST_HEAD(&req->queue);
  566. req->req.dma = DMA_ADDR_INVALID;
  567. return &req->req;
  568. }
  569. static void
  570. usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
  571. {
  572. struct usba_request *req = to_usba_req(_req);
  573. DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
  574. kfree(req);
  575. }
  576. static int queue_dma(struct usba_udc *udc, struct usba_ep *ep,
  577. struct usba_request *req, gfp_t gfp_flags)
  578. {
  579. unsigned long flags;
  580. int ret;
  581. DBG(DBG_DMA, "%s: req l/%u d/%08x %c%c%c\n",
  582. ep->ep.name, req->req.length, req->req.dma,
  583. req->req.zero ? 'Z' : 'z',
  584. req->req.short_not_ok ? 'S' : 's',
  585. req->req.no_interrupt ? 'I' : 'i');
  586. if (req->req.length > 0x10000) {
  587. /* Lengths from 0 to 65536 (inclusive) are supported */
  588. DBG(DBG_ERR, "invalid request length %u\n", req->req.length);
  589. return -EINVAL;
  590. }
  591. req->using_dma = 1;
  592. if (req->req.dma == DMA_ADDR_INVALID) {
  593. req->req.dma = dma_map_single(
  594. &udc->pdev->dev, req->req.buf, req->req.length,
  595. ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  596. req->mapped = 1;
  597. } else {
  598. dma_sync_single_for_device(
  599. &udc->pdev->dev, req->req.dma, req->req.length,
  600. ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  601. req->mapped = 0;
  602. }
  603. req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length)
  604. | USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE
  605. | USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE;
  606. if (ep->is_in)
  607. req->ctrl |= USBA_DMA_END_BUF_EN;
  608. /*
  609. * Add this request to the queue and submit for DMA if
  610. * possible. Check if we're still alive first -- we may have
  611. * received a reset since last time we checked.
  612. */
  613. ret = -ESHUTDOWN;
  614. spin_lock_irqsave(&udc->lock, flags);
  615. if (ep->desc) {
  616. if (list_empty(&ep->queue))
  617. submit_request(ep, req);
  618. list_add_tail(&req->queue, &ep->queue);
  619. ret = 0;
  620. }
  621. spin_unlock_irqrestore(&udc->lock, flags);
  622. return ret;
  623. }
  624. static int
  625. usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
  626. {
  627. struct usba_request *req = to_usba_req(_req);
  628. struct usba_ep *ep = to_usba_ep(_ep);
  629. struct usba_udc *udc = ep->udc;
  630. unsigned long flags;
  631. int ret;
  632. DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ, "%s: queue req %p, len %u\n",
  633. ep->ep.name, req, _req->length);
  634. if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN || !ep->desc)
  635. return -ESHUTDOWN;
  636. req->submitted = 0;
  637. req->using_dma = 0;
  638. req->last_transaction = 0;
  639. _req->status = -EINPROGRESS;
  640. _req->actual = 0;
  641. if (ep->can_dma)
  642. return queue_dma(udc, ep, req, gfp_flags);
  643. /* May have received a reset since last time we checked */
  644. ret = -ESHUTDOWN;
  645. spin_lock_irqsave(&udc->lock, flags);
  646. if (ep->desc) {
  647. list_add_tail(&req->queue, &ep->queue);
  648. if ((!ep_is_control(ep) && ep->is_in) ||
  649. (ep_is_control(ep)
  650. && (ep->state == DATA_STAGE_IN
  651. || ep->state == STATUS_STAGE_IN)))
  652. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  653. else
  654. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  655. ret = 0;
  656. }
  657. spin_unlock_irqrestore(&udc->lock, flags);
  658. return ret;
  659. }
  660. static void
  661. usba_update_req(struct usba_ep *ep, struct usba_request *req, u32 status)
  662. {
  663. req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status);
  664. }
  665. static int stop_dma(struct usba_ep *ep, u32 *pstatus)
  666. {
  667. unsigned int timeout;
  668. u32 status;
  669. /*
  670. * Stop the DMA controller. When writing both CH_EN
  671. * and LINK to 0, the other bits are not affected.
  672. */
  673. usba_dma_writel(ep, CONTROL, 0);
  674. /* Wait for the FIFO to empty */
  675. for (timeout = 40; timeout; --timeout) {
  676. status = usba_dma_readl(ep, STATUS);
  677. if (!(status & USBA_DMA_CH_EN))
  678. break;
  679. udelay(1);
  680. }
  681. if (pstatus)
  682. *pstatus = status;
  683. if (timeout == 0) {
  684. dev_err(&ep->udc->pdev->dev,
  685. "%s: timed out waiting for DMA FIFO to empty\n",
  686. ep->ep.name);
  687. return -ETIMEDOUT;
  688. }
  689. return 0;
  690. }
  691. static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  692. {
  693. struct usba_ep *ep = to_usba_ep(_ep);
  694. struct usba_udc *udc = ep->udc;
  695. struct usba_request *req = to_usba_req(_req);
  696. unsigned long flags;
  697. u32 status;
  698. DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n",
  699. ep->ep.name, req);
  700. spin_lock_irqsave(&udc->lock, flags);
  701. if (req->using_dma) {
  702. /*
  703. * If this request is currently being transferred,
  704. * stop the DMA controller and reset the FIFO.
  705. */
  706. if (ep->queue.next == &req->queue) {
  707. status = usba_dma_readl(ep, STATUS);
  708. if (status & USBA_DMA_CH_EN)
  709. stop_dma(ep, &status);
  710. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  711. ep->last_dma_status = status;
  712. #endif
  713. usba_writel(udc, EPT_RST, 1 << ep->index);
  714. usba_update_req(ep, req, status);
  715. }
  716. }
  717. /*
  718. * Errors should stop the queue from advancing until the
  719. * completion function returns.
  720. */
  721. list_del_init(&req->queue);
  722. request_complete(ep, req, -ECONNRESET);
  723. /* Process the next request if any */
  724. submit_next_request(ep);
  725. spin_unlock_irqrestore(&udc->lock, flags);
  726. return 0;
  727. }
  728. static int usba_ep_set_halt(struct usb_ep *_ep, int value)
  729. {
  730. struct usba_ep *ep = to_usba_ep(_ep);
  731. struct usba_udc *udc = ep->udc;
  732. unsigned long flags;
  733. int ret = 0;
  734. DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep->ep.name,
  735. value ? "set" : "clear");
  736. if (!ep->desc) {
  737. DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
  738. ep->ep.name);
  739. return -ENODEV;
  740. }
  741. if (ep->is_isoc) {
  742. DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
  743. ep->ep.name);
  744. return -ENOTTY;
  745. }
  746. spin_lock_irqsave(&udc->lock, flags);
  747. /*
  748. * We can't halt IN endpoints while there are still data to be
  749. * transferred
  750. */
  751. if (!list_empty(&ep->queue)
  752. || ((value && ep->is_in && (usba_ep_readl(ep, STA)
  753. & USBA_BF(BUSY_BANKS, -1L))))) {
  754. ret = -EAGAIN;
  755. } else {
  756. if (value)
  757. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  758. else
  759. usba_ep_writel(ep, CLR_STA,
  760. USBA_FORCE_STALL | USBA_TOGGLE_CLR);
  761. usba_ep_readl(ep, STA);
  762. }
  763. spin_unlock_irqrestore(&udc->lock, flags);
  764. return ret;
  765. }
  766. static int usba_ep_fifo_status(struct usb_ep *_ep)
  767. {
  768. struct usba_ep *ep = to_usba_ep(_ep);
  769. return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  770. }
  771. static void usba_ep_fifo_flush(struct usb_ep *_ep)
  772. {
  773. struct usba_ep *ep = to_usba_ep(_ep);
  774. struct usba_udc *udc = ep->udc;
  775. usba_writel(udc, EPT_RST, 1 << ep->index);
  776. }
  777. static const struct usb_ep_ops usba_ep_ops = {
  778. .enable = usba_ep_enable,
  779. .disable = usba_ep_disable,
  780. .alloc_request = usba_ep_alloc_request,
  781. .free_request = usba_ep_free_request,
  782. .queue = usba_ep_queue,
  783. .dequeue = usba_ep_dequeue,
  784. .set_halt = usba_ep_set_halt,
  785. .fifo_status = usba_ep_fifo_status,
  786. .fifo_flush = usba_ep_fifo_flush,
  787. };
  788. static int usba_udc_get_frame(struct usb_gadget *gadget)
  789. {
  790. struct usba_udc *udc = to_usba_udc(gadget);
  791. return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM));
  792. }
  793. static int usba_udc_wakeup(struct usb_gadget *gadget)
  794. {
  795. struct usba_udc *udc = to_usba_udc(gadget);
  796. unsigned long flags;
  797. u32 ctrl;
  798. int ret = -EINVAL;
  799. spin_lock_irqsave(&udc->lock, flags);
  800. if (udc->devstatus & (1 << USB_DEVICE_REMOTE_WAKEUP)) {
  801. ctrl = usba_readl(udc, CTRL);
  802. usba_writel(udc, CTRL, ctrl | USBA_REMOTE_WAKE_UP);
  803. ret = 0;
  804. }
  805. spin_unlock_irqrestore(&udc->lock, flags);
  806. return ret;
  807. }
  808. static int
  809. usba_udc_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
  810. {
  811. struct usba_udc *udc = to_usba_udc(gadget);
  812. unsigned long flags;
  813. spin_lock_irqsave(&udc->lock, flags);
  814. if (is_selfpowered)
  815. udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED;
  816. else
  817. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  818. spin_unlock_irqrestore(&udc->lock, flags);
  819. return 0;
  820. }
  821. static const struct usb_gadget_ops usba_udc_ops = {
  822. .get_frame = usba_udc_get_frame,
  823. .wakeup = usba_udc_wakeup,
  824. .set_selfpowered = usba_udc_set_selfpowered,
  825. };
  826. static struct usb_endpoint_descriptor usba_ep0_desc = {
  827. .bLength = USB_DT_ENDPOINT_SIZE,
  828. .bDescriptorType = USB_DT_ENDPOINT,
  829. .bEndpointAddress = 0,
  830. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  831. .wMaxPacketSize = cpu_to_le16(64),
  832. /* FIXME: I have no idea what to put here */
  833. .bInterval = 1,
  834. };
  835. static void nop_release(struct device *dev)
  836. {
  837. }
  838. static struct usba_udc the_udc = {
  839. .gadget = {
  840. .ops = &usba_udc_ops,
  841. .ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list),
  842. .is_dualspeed = 1,
  843. .name = "atmel_usba_udc",
  844. .dev = {
  845. .init_name = "gadget",
  846. .release = nop_release,
  847. },
  848. },
  849. };
  850. /*
  851. * Called with interrupts disabled and udc->lock held.
  852. */
  853. static void reset_all_endpoints(struct usba_udc *udc)
  854. {
  855. struct usba_ep *ep;
  856. struct usba_request *req, *tmp_req;
  857. usba_writel(udc, EPT_RST, ~0UL);
  858. ep = to_usba_ep(udc->gadget.ep0);
  859. list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
  860. list_del_init(&req->queue);
  861. request_complete(ep, req, -ECONNRESET);
  862. }
  863. /* NOTE: normally, the next call to the gadget driver is in
  864. * charge of disabling endpoints... usually disconnect().
  865. * The exception would be entering a high speed test mode.
  866. *
  867. * FIXME remove this code ... and retest thoroughly.
  868. */
  869. list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
  870. if (ep->desc) {
  871. spin_unlock(&udc->lock);
  872. usba_ep_disable(&ep->ep);
  873. spin_lock(&udc->lock);
  874. }
  875. }
  876. }
  877. static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex)
  878. {
  879. struct usba_ep *ep;
  880. if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
  881. return to_usba_ep(udc->gadget.ep0);
  882. list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
  883. u8 bEndpointAddress;
  884. if (!ep->desc)
  885. continue;
  886. bEndpointAddress = ep->desc->bEndpointAddress;
  887. if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
  888. continue;
  889. if ((bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
  890. == (wIndex & USB_ENDPOINT_NUMBER_MASK))
  891. return ep;
  892. }
  893. return NULL;
  894. }
  895. /* Called with interrupts disabled and udc->lock held */
  896. static inline void set_protocol_stall(struct usba_udc *udc, struct usba_ep *ep)
  897. {
  898. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  899. ep->state = WAIT_FOR_SETUP;
  900. }
  901. static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep)
  902. {
  903. if (usba_ep_readl(ep, STA) & USBA_FORCE_STALL)
  904. return 1;
  905. return 0;
  906. }
  907. static inline void set_address(struct usba_udc *udc, unsigned int addr)
  908. {
  909. u32 regval;
  910. DBG(DBG_BUS, "setting address %u...\n", addr);
  911. regval = usba_readl(udc, CTRL);
  912. regval = USBA_BFINS(DEV_ADDR, addr, regval);
  913. usba_writel(udc, CTRL, regval);
  914. }
  915. static int do_test_mode(struct usba_udc *udc)
  916. {
  917. static const char test_packet_buffer[] = {
  918. /* JKJKJKJK * 9 */
  919. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  920. /* JJKKJJKK * 8 */
  921. 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
  922. /* JJKKJJKK * 8 */
  923. 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
  924. /* JJJJJJJKKKKKKK * 8 */
  925. 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  926. 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  927. /* JJJJJJJK * 8 */
  928. 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD,
  929. /* {JKKKKKKK * 10}, JK */
  930. 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E
  931. };
  932. struct usba_ep *ep;
  933. struct device *dev = &udc->pdev->dev;
  934. int test_mode;
  935. test_mode = udc->test_mode;
  936. /* Start from a clean slate */
  937. reset_all_endpoints(udc);
  938. switch (test_mode) {
  939. case 0x0100:
  940. /* Test_J */
  941. usba_writel(udc, TST, USBA_TST_J_MODE);
  942. dev_info(dev, "Entering Test_J mode...\n");
  943. break;
  944. case 0x0200:
  945. /* Test_K */
  946. usba_writel(udc, TST, USBA_TST_K_MODE);
  947. dev_info(dev, "Entering Test_K mode...\n");
  948. break;
  949. case 0x0300:
  950. /*
  951. * Test_SE0_NAK: Force high-speed mode and set up ep0
  952. * for Bulk IN transfers
  953. */
  954. ep = &usba_ep[0];
  955. usba_writel(udc, TST,
  956. USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
  957. usba_ep_writel(ep, CFG,
  958. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  959. | USBA_EPT_DIR_IN
  960. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  961. | USBA_BF(BK_NUMBER, 1));
  962. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  963. set_protocol_stall(udc, ep);
  964. dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n");
  965. } else {
  966. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  967. dev_info(dev, "Entering Test_SE0_NAK mode...\n");
  968. }
  969. break;
  970. case 0x0400:
  971. /* Test_Packet */
  972. ep = &usba_ep[0];
  973. usba_ep_writel(ep, CFG,
  974. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  975. | USBA_EPT_DIR_IN
  976. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  977. | USBA_BF(BK_NUMBER, 1));
  978. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  979. set_protocol_stall(udc, ep);
  980. dev_err(dev, "Test_Packet: ep0 not mapped\n");
  981. } else {
  982. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  983. usba_writel(udc, TST, USBA_TST_PKT_MODE);
  984. memcpy_toio(ep->fifo, test_packet_buffer,
  985. sizeof(test_packet_buffer));
  986. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  987. dev_info(dev, "Entering Test_Packet mode...\n");
  988. }
  989. break;
  990. default:
  991. dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode);
  992. return -EINVAL;
  993. }
  994. return 0;
  995. }
  996. /* Avoid overly long expressions */
  997. static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq)
  998. {
  999. if (crq->wValue == cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP))
  1000. return true;
  1001. return false;
  1002. }
  1003. static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq)
  1004. {
  1005. if (crq->wValue == cpu_to_le16(USB_DEVICE_TEST_MODE))
  1006. return true;
  1007. return false;
  1008. }
  1009. static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq)
  1010. {
  1011. if (crq->wValue == cpu_to_le16(USB_ENDPOINT_HALT))
  1012. return true;
  1013. return false;
  1014. }
  1015. static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
  1016. struct usb_ctrlrequest *crq)
  1017. {
  1018. int retval = 0;
  1019. switch (crq->bRequest) {
  1020. case USB_REQ_GET_STATUS: {
  1021. u16 status;
  1022. if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
  1023. status = cpu_to_le16(udc->devstatus);
  1024. } else if (crq->bRequestType
  1025. == (USB_DIR_IN | USB_RECIP_INTERFACE)) {
  1026. status = cpu_to_le16(0);
  1027. } else if (crq->bRequestType
  1028. == (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
  1029. struct usba_ep *target;
  1030. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1031. if (!target)
  1032. goto stall;
  1033. status = 0;
  1034. if (is_stalled(udc, target))
  1035. status |= cpu_to_le16(1);
  1036. } else
  1037. goto delegate;
  1038. /* Write directly to the FIFO. No queueing is done. */
  1039. if (crq->wLength != cpu_to_le16(sizeof(status)))
  1040. goto stall;
  1041. ep->state = DATA_STAGE_IN;
  1042. __raw_writew(status, ep->fifo);
  1043. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  1044. break;
  1045. }
  1046. case USB_REQ_CLEAR_FEATURE: {
  1047. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1048. if (feature_is_dev_remote_wakeup(crq))
  1049. udc->devstatus
  1050. &= ~(1 << USB_DEVICE_REMOTE_WAKEUP);
  1051. else
  1052. /* Can't CLEAR_FEATURE TEST_MODE */
  1053. goto stall;
  1054. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1055. struct usba_ep *target;
  1056. if (crq->wLength != cpu_to_le16(0)
  1057. || !feature_is_ep_halt(crq))
  1058. goto stall;
  1059. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1060. if (!target)
  1061. goto stall;
  1062. usba_ep_writel(target, CLR_STA, USBA_FORCE_STALL);
  1063. if (target->index != 0)
  1064. usba_ep_writel(target, CLR_STA,
  1065. USBA_TOGGLE_CLR);
  1066. } else {
  1067. goto delegate;
  1068. }
  1069. send_status(udc, ep);
  1070. break;
  1071. }
  1072. case USB_REQ_SET_FEATURE: {
  1073. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1074. if (feature_is_dev_test_mode(crq)) {
  1075. send_status(udc, ep);
  1076. ep->state = STATUS_STAGE_TEST;
  1077. udc->test_mode = le16_to_cpu(crq->wIndex);
  1078. return 0;
  1079. } else if (feature_is_dev_remote_wakeup(crq)) {
  1080. udc->devstatus |= 1 << USB_DEVICE_REMOTE_WAKEUP;
  1081. } else {
  1082. goto stall;
  1083. }
  1084. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1085. struct usba_ep *target;
  1086. if (crq->wLength != cpu_to_le16(0)
  1087. || !feature_is_ep_halt(crq))
  1088. goto stall;
  1089. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1090. if (!target)
  1091. goto stall;
  1092. usba_ep_writel(target, SET_STA, USBA_FORCE_STALL);
  1093. } else
  1094. goto delegate;
  1095. send_status(udc, ep);
  1096. break;
  1097. }
  1098. case USB_REQ_SET_ADDRESS:
  1099. if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
  1100. goto delegate;
  1101. set_address(udc, le16_to_cpu(crq->wValue));
  1102. send_status(udc, ep);
  1103. ep->state = STATUS_STAGE_ADDR;
  1104. break;
  1105. default:
  1106. delegate:
  1107. spin_unlock(&udc->lock);
  1108. retval = udc->driver->setup(&udc->gadget, crq);
  1109. spin_lock(&udc->lock);
  1110. }
  1111. return retval;
  1112. stall:
  1113. pr_err("udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
  1114. "halting endpoint...\n",
  1115. ep->ep.name, crq->bRequestType, crq->bRequest,
  1116. le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
  1117. le16_to_cpu(crq->wLength));
  1118. set_protocol_stall(udc, ep);
  1119. return -1;
  1120. }
  1121. static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep)
  1122. {
  1123. struct usba_request *req;
  1124. u32 epstatus;
  1125. u32 epctrl;
  1126. restart:
  1127. epstatus = usba_ep_readl(ep, STA);
  1128. epctrl = usba_ep_readl(ep, CTL);
  1129. DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n",
  1130. ep->ep.name, ep->state, epstatus, epctrl);
  1131. req = NULL;
  1132. if (!list_empty(&ep->queue))
  1133. req = list_entry(ep->queue.next,
  1134. struct usba_request, queue);
  1135. if ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1136. if (req->submitted)
  1137. next_fifo_transaction(ep, req);
  1138. else
  1139. submit_request(ep, req);
  1140. if (req->last_transaction) {
  1141. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1142. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  1143. }
  1144. goto restart;
  1145. }
  1146. if ((epstatus & epctrl) & USBA_TX_COMPLETE) {
  1147. usba_ep_writel(ep, CLR_STA, USBA_TX_COMPLETE);
  1148. switch (ep->state) {
  1149. case DATA_STAGE_IN:
  1150. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  1151. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1152. ep->state = STATUS_STAGE_OUT;
  1153. break;
  1154. case STATUS_STAGE_ADDR:
  1155. /* Activate our new address */
  1156. usba_writel(udc, CTRL, (usba_readl(udc, CTRL)
  1157. | USBA_FADDR_EN));
  1158. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1159. ep->state = WAIT_FOR_SETUP;
  1160. break;
  1161. case STATUS_STAGE_IN:
  1162. if (req) {
  1163. list_del_init(&req->queue);
  1164. request_complete(ep, req, 0);
  1165. submit_next_request(ep);
  1166. }
  1167. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1168. ep->state = WAIT_FOR_SETUP;
  1169. break;
  1170. case STATUS_STAGE_TEST:
  1171. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1172. ep->state = WAIT_FOR_SETUP;
  1173. if (do_test_mode(udc))
  1174. set_protocol_stall(udc, ep);
  1175. break;
  1176. default:
  1177. pr_err("udc: %s: TXCOMP: Invalid endpoint state %d, "
  1178. "halting endpoint...\n",
  1179. ep->ep.name, ep->state);
  1180. set_protocol_stall(udc, ep);
  1181. break;
  1182. }
  1183. goto restart;
  1184. }
  1185. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1186. switch (ep->state) {
  1187. case STATUS_STAGE_OUT:
  1188. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1189. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1190. if (req) {
  1191. list_del_init(&req->queue);
  1192. request_complete(ep, req, 0);
  1193. }
  1194. ep->state = WAIT_FOR_SETUP;
  1195. break;
  1196. case DATA_STAGE_OUT:
  1197. receive_data(ep);
  1198. break;
  1199. default:
  1200. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1201. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1202. pr_err("udc: %s: RXRDY: Invalid endpoint state %d, "
  1203. "halting endpoint...\n",
  1204. ep->ep.name, ep->state);
  1205. set_protocol_stall(udc, ep);
  1206. break;
  1207. }
  1208. goto restart;
  1209. }
  1210. if (epstatus & USBA_RX_SETUP) {
  1211. union {
  1212. struct usb_ctrlrequest crq;
  1213. unsigned long data[2];
  1214. } crq;
  1215. unsigned int pkt_len;
  1216. int ret;
  1217. if (ep->state != WAIT_FOR_SETUP) {
  1218. /*
  1219. * Didn't expect a SETUP packet at this
  1220. * point. Clean up any pending requests (which
  1221. * may be successful).
  1222. */
  1223. int status = -EPROTO;
  1224. /*
  1225. * RXRDY and TXCOMP are dropped when SETUP
  1226. * packets arrive. Just pretend we received
  1227. * the status packet.
  1228. */
  1229. if (ep->state == STATUS_STAGE_OUT
  1230. || ep->state == STATUS_STAGE_IN) {
  1231. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1232. status = 0;
  1233. }
  1234. if (req) {
  1235. list_del_init(&req->queue);
  1236. request_complete(ep, req, status);
  1237. }
  1238. }
  1239. pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  1240. DBG(DBG_HW, "Packet length: %u\n", pkt_len);
  1241. if (pkt_len != sizeof(crq)) {
  1242. pr_warning("udc: Invalid packet length %u "
  1243. "(expected %zu)\n", pkt_len, sizeof(crq));
  1244. set_protocol_stall(udc, ep);
  1245. return;
  1246. }
  1247. DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
  1248. memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
  1249. /* Free up one bank in the FIFO so that we can
  1250. * generate or receive a reply right away. */
  1251. usba_ep_writel(ep, CLR_STA, USBA_RX_SETUP);
  1252. /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
  1253. ep->state, crq.crq.bRequestType,
  1254. crq.crq.bRequest); */
  1255. if (crq.crq.bRequestType & USB_DIR_IN) {
  1256. /*
  1257. * The USB 2.0 spec states that "if wLength is
  1258. * zero, there is no data transfer phase."
  1259. * However, testusb #14 seems to actually
  1260. * expect a data phase even if wLength = 0...
  1261. */
  1262. ep->state = DATA_STAGE_IN;
  1263. } else {
  1264. if (crq.crq.wLength != cpu_to_le16(0))
  1265. ep->state = DATA_STAGE_OUT;
  1266. else
  1267. ep->state = STATUS_STAGE_IN;
  1268. }
  1269. ret = -1;
  1270. if (ep->index == 0)
  1271. ret = handle_ep0_setup(udc, ep, &crq.crq);
  1272. else {
  1273. spin_unlock(&udc->lock);
  1274. ret = udc->driver->setup(&udc->gadget, &crq.crq);
  1275. spin_lock(&udc->lock);
  1276. }
  1277. DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
  1278. crq.crq.bRequestType, crq.crq.bRequest,
  1279. le16_to_cpu(crq.crq.wLength), ep->state, ret);
  1280. if (ret < 0) {
  1281. /* Let the host know that we failed */
  1282. set_protocol_stall(udc, ep);
  1283. }
  1284. }
  1285. }
  1286. static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep)
  1287. {
  1288. struct usba_request *req;
  1289. u32 epstatus;
  1290. u32 epctrl;
  1291. epstatus = usba_ep_readl(ep, STA);
  1292. epctrl = usba_ep_readl(ep, CTL);
  1293. DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n", ep->ep.name, epstatus);
  1294. while ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1295. DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name);
  1296. if (list_empty(&ep->queue)) {
  1297. dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
  1298. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1299. return;
  1300. }
  1301. req = list_entry(ep->queue.next, struct usba_request, queue);
  1302. if (req->using_dma) {
  1303. /* Send a zero-length packet */
  1304. usba_ep_writel(ep, SET_STA,
  1305. USBA_TX_PK_RDY);
  1306. usba_ep_writel(ep, CTL_DIS,
  1307. USBA_TX_PK_RDY);
  1308. list_del_init(&req->queue);
  1309. submit_next_request(ep);
  1310. request_complete(ep, req, 0);
  1311. } else {
  1312. if (req->submitted)
  1313. next_fifo_transaction(ep, req);
  1314. else
  1315. submit_request(ep, req);
  1316. if (req->last_transaction) {
  1317. list_del_init(&req->queue);
  1318. submit_next_request(ep);
  1319. request_complete(ep, req, 0);
  1320. }
  1321. }
  1322. epstatus = usba_ep_readl(ep, STA);
  1323. epctrl = usba_ep_readl(ep, CTL);
  1324. }
  1325. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1326. DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name);
  1327. receive_data(ep);
  1328. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1329. }
  1330. }
  1331. static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep)
  1332. {
  1333. struct usba_request *req;
  1334. u32 status, control, pending;
  1335. status = usba_dma_readl(ep, STATUS);
  1336. control = usba_dma_readl(ep, CONTROL);
  1337. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  1338. ep->last_dma_status = status;
  1339. #endif
  1340. pending = status & control;
  1341. DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n", status, control);
  1342. if (status & USBA_DMA_CH_EN) {
  1343. dev_err(&udc->pdev->dev,
  1344. "DMA_CH_EN is set after transfer is finished!\n");
  1345. dev_err(&udc->pdev->dev,
  1346. "status=%#08x, pending=%#08x, control=%#08x\n",
  1347. status, pending, control);
  1348. /*
  1349. * try to pretend nothing happened. We might have to
  1350. * do something here...
  1351. */
  1352. }
  1353. if (list_empty(&ep->queue))
  1354. /* Might happen if a reset comes along at the right moment */
  1355. return;
  1356. if (pending & (USBA_DMA_END_TR_ST | USBA_DMA_END_BUF_ST)) {
  1357. req = list_entry(ep->queue.next, struct usba_request, queue);
  1358. usba_update_req(ep, req, status);
  1359. list_del_init(&req->queue);
  1360. submit_next_request(ep);
  1361. request_complete(ep, req, 0);
  1362. }
  1363. }
  1364. static irqreturn_t usba_udc_irq(int irq, void *devid)
  1365. {
  1366. struct usba_udc *udc = devid;
  1367. u32 status;
  1368. u32 dma_status;
  1369. u32 ep_status;
  1370. spin_lock(&udc->lock);
  1371. status = usba_readl(udc, INT_STA);
  1372. DBG(DBG_INT, "irq, status=%#08x\n", status);
  1373. if (status & USBA_DET_SUSPEND) {
  1374. toggle_bias(0);
  1375. usba_writel(udc, INT_CLR, USBA_DET_SUSPEND);
  1376. DBG(DBG_BUS, "Suspend detected\n");
  1377. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1378. && udc->driver && udc->driver->suspend) {
  1379. spin_unlock(&udc->lock);
  1380. udc->driver->suspend(&udc->gadget);
  1381. spin_lock(&udc->lock);
  1382. }
  1383. }
  1384. if (status & USBA_WAKE_UP) {
  1385. toggle_bias(1);
  1386. usba_writel(udc, INT_CLR, USBA_WAKE_UP);
  1387. DBG(DBG_BUS, "Wake Up CPU detected\n");
  1388. }
  1389. if (status & USBA_END_OF_RESUME) {
  1390. usba_writel(udc, INT_CLR, USBA_END_OF_RESUME);
  1391. DBG(DBG_BUS, "Resume detected\n");
  1392. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1393. && udc->driver && udc->driver->resume) {
  1394. spin_unlock(&udc->lock);
  1395. udc->driver->resume(&udc->gadget);
  1396. spin_lock(&udc->lock);
  1397. }
  1398. }
  1399. dma_status = USBA_BFEXT(DMA_INT, status);
  1400. if (dma_status) {
  1401. int i;
  1402. for (i = 1; i < USBA_NR_ENDPOINTS; i++)
  1403. if (dma_status & (1 << i))
  1404. usba_dma_irq(udc, &usba_ep[i]);
  1405. }
  1406. ep_status = USBA_BFEXT(EPT_INT, status);
  1407. if (ep_status) {
  1408. int i;
  1409. for (i = 0; i < USBA_NR_ENDPOINTS; i++)
  1410. if (ep_status & (1 << i)) {
  1411. if (ep_is_control(&usba_ep[i]))
  1412. usba_control_irq(udc, &usba_ep[i]);
  1413. else
  1414. usba_ep_irq(udc, &usba_ep[i]);
  1415. }
  1416. }
  1417. if (status & USBA_END_OF_RESET) {
  1418. struct usba_ep *ep0;
  1419. usba_writel(udc, INT_CLR, USBA_END_OF_RESET);
  1420. reset_all_endpoints(udc);
  1421. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1422. && udc->driver->disconnect) {
  1423. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1424. spin_unlock(&udc->lock);
  1425. udc->driver->disconnect(&udc->gadget);
  1426. spin_lock(&udc->lock);
  1427. }
  1428. if (status & USBA_HIGH_SPEED) {
  1429. DBG(DBG_BUS, "High-speed bus reset detected\n");
  1430. udc->gadget.speed = USB_SPEED_HIGH;
  1431. } else {
  1432. DBG(DBG_BUS, "Full-speed bus reset detected\n");
  1433. udc->gadget.speed = USB_SPEED_FULL;
  1434. }
  1435. ep0 = &usba_ep[0];
  1436. ep0->desc = &usba_ep0_desc;
  1437. ep0->state = WAIT_FOR_SETUP;
  1438. usba_ep_writel(ep0, CFG,
  1439. (USBA_BF(EPT_SIZE, EP0_EPT_SIZE)
  1440. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL)
  1441. | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE)));
  1442. usba_ep_writel(ep0, CTL_ENB,
  1443. USBA_EPT_ENABLE | USBA_RX_SETUP);
  1444. usba_writel(udc, INT_ENB,
  1445. (usba_readl(udc, INT_ENB)
  1446. | USBA_BF(EPT_INT, 1)
  1447. | USBA_DET_SUSPEND
  1448. | USBA_END_OF_RESUME));
  1449. /*
  1450. * Unclear why we hit this irregularly, e.g. in usbtest,
  1451. * but it's clearly harmless...
  1452. */
  1453. if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED))
  1454. dev_dbg(&udc->pdev->dev,
  1455. "ODD: EP0 configuration is invalid!\n");
  1456. }
  1457. spin_unlock(&udc->lock);
  1458. return IRQ_HANDLED;
  1459. }
  1460. static irqreturn_t usba_vbus_irq(int irq, void *devid)
  1461. {
  1462. struct usba_udc *udc = devid;
  1463. int vbus;
  1464. /* debounce */
  1465. udelay(10);
  1466. spin_lock(&udc->lock);
  1467. /* May happen if Vbus pin toggles during probe() */
  1468. if (!udc->driver)
  1469. goto out;
  1470. vbus = vbus_is_present(udc);
  1471. if (vbus != udc->vbus_prev) {
  1472. if (vbus) {
  1473. toggle_bias(1);
  1474. usba_writel(udc, CTRL, USBA_ENABLE_MASK);
  1475. usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
  1476. } else {
  1477. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1478. reset_all_endpoints(udc);
  1479. toggle_bias(0);
  1480. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1481. if (udc->driver->disconnect) {
  1482. spin_unlock(&udc->lock);
  1483. udc->driver->disconnect(&udc->gadget);
  1484. spin_lock(&udc->lock);
  1485. }
  1486. }
  1487. udc->vbus_prev = vbus;
  1488. }
  1489. out:
  1490. spin_unlock(&udc->lock);
  1491. return IRQ_HANDLED;
  1492. }
  1493. int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
  1494. int (*bind)(struct usb_gadget *))
  1495. {
  1496. struct usba_udc *udc = &the_udc;
  1497. unsigned long flags;
  1498. int ret;
  1499. if (!udc->pdev)
  1500. return -ENODEV;
  1501. spin_lock_irqsave(&udc->lock, flags);
  1502. if (udc->driver) {
  1503. spin_unlock_irqrestore(&udc->lock, flags);
  1504. return -EBUSY;
  1505. }
  1506. udc->devstatus = 1 << USB_DEVICE_SELF_POWERED;
  1507. udc->driver = driver;
  1508. udc->gadget.dev.driver = &driver->driver;
  1509. spin_unlock_irqrestore(&udc->lock, flags);
  1510. clk_enable(udc->pclk);
  1511. clk_enable(udc->hclk);
  1512. ret = bind(&udc->gadget);
  1513. if (ret) {
  1514. DBG(DBG_ERR, "Could not bind to driver %s: error %d\n",
  1515. driver->driver.name, ret);
  1516. goto err_driver_bind;
  1517. }
  1518. DBG(DBG_GADGET, "registered driver `%s'\n", driver->driver.name);
  1519. udc->vbus_prev = 0;
  1520. if (gpio_is_valid(udc->vbus_pin))
  1521. enable_irq(gpio_to_irq(udc->vbus_pin));
  1522. /* If Vbus is present, enable the controller and wait for reset */
  1523. spin_lock_irqsave(&udc->lock, flags);
  1524. if (vbus_is_present(udc) && udc->vbus_prev == 0) {
  1525. toggle_bias(1);
  1526. usba_writel(udc, CTRL, USBA_ENABLE_MASK);
  1527. usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
  1528. }
  1529. spin_unlock_irqrestore(&udc->lock, flags);
  1530. return 0;
  1531. err_driver_bind:
  1532. udc->driver = NULL;
  1533. udc->gadget.dev.driver = NULL;
  1534. return ret;
  1535. }
  1536. EXPORT_SYMBOL(usb_gadget_probe_driver);
  1537. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1538. {
  1539. struct usba_udc *udc = &the_udc;
  1540. unsigned long flags;
  1541. if (!udc->pdev)
  1542. return -ENODEV;
  1543. if (driver != udc->driver || !driver->unbind)
  1544. return -EINVAL;
  1545. if (gpio_is_valid(udc->vbus_pin))
  1546. disable_irq(gpio_to_irq(udc->vbus_pin));
  1547. spin_lock_irqsave(&udc->lock, flags);
  1548. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1549. reset_all_endpoints(udc);
  1550. spin_unlock_irqrestore(&udc->lock, flags);
  1551. /* This will also disable the DP pullup */
  1552. toggle_bias(0);
  1553. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1554. if (udc->driver->disconnect)
  1555. udc->driver->disconnect(&udc->gadget);
  1556. driver->unbind(&udc->gadget);
  1557. udc->gadget.dev.driver = NULL;
  1558. udc->driver = NULL;
  1559. clk_disable(udc->hclk);
  1560. clk_disable(udc->pclk);
  1561. DBG(DBG_GADGET, "unregistered driver `%s'\n", driver->driver.name);
  1562. return 0;
  1563. }
  1564. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1565. static int __init usba_udc_probe(struct platform_device *pdev)
  1566. {
  1567. struct usba_platform_data *pdata = pdev->dev.platform_data;
  1568. struct resource *regs, *fifo;
  1569. struct clk *pclk, *hclk;
  1570. struct usba_udc *udc = &the_udc;
  1571. int irq, ret, i;
  1572. regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
  1573. fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
  1574. if (!regs || !fifo || !pdata)
  1575. return -ENXIO;
  1576. irq = platform_get_irq(pdev, 0);
  1577. if (irq < 0)
  1578. return irq;
  1579. pclk = clk_get(&pdev->dev, "pclk");
  1580. if (IS_ERR(pclk))
  1581. return PTR_ERR(pclk);
  1582. hclk = clk_get(&pdev->dev, "hclk");
  1583. if (IS_ERR(hclk)) {
  1584. ret = PTR_ERR(hclk);
  1585. goto err_get_hclk;
  1586. }
  1587. spin_lock_init(&udc->lock);
  1588. udc->pdev = pdev;
  1589. udc->pclk = pclk;
  1590. udc->hclk = hclk;
  1591. udc->vbus_pin = -ENODEV;
  1592. ret = -ENOMEM;
  1593. udc->regs = ioremap(regs->start, resource_size(regs));
  1594. if (!udc->regs) {
  1595. dev_err(&pdev->dev, "Unable to map I/O memory, aborting.\n");
  1596. goto err_map_regs;
  1597. }
  1598. dev_info(&pdev->dev, "MMIO registers at 0x%08lx mapped at %p\n",
  1599. (unsigned long)regs->start, udc->regs);
  1600. udc->fifo = ioremap(fifo->start, resource_size(fifo));
  1601. if (!udc->fifo) {
  1602. dev_err(&pdev->dev, "Unable to map FIFO, aborting.\n");
  1603. goto err_map_fifo;
  1604. }
  1605. dev_info(&pdev->dev, "FIFO at 0x%08lx mapped at %p\n",
  1606. (unsigned long)fifo->start, udc->fifo);
  1607. device_initialize(&udc->gadget.dev);
  1608. udc->gadget.dev.parent = &pdev->dev;
  1609. udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1610. platform_set_drvdata(pdev, udc);
  1611. /* Make sure we start from a clean slate */
  1612. clk_enable(pclk);
  1613. toggle_bias(0);
  1614. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1615. clk_disable(pclk);
  1616. usba_ep = kzalloc(sizeof(struct usba_ep) * pdata->num_ep,
  1617. GFP_KERNEL);
  1618. if (!usba_ep)
  1619. goto err_alloc_ep;
  1620. the_udc.gadget.ep0 = &usba_ep[0].ep;
  1621. INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
  1622. usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
  1623. usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
  1624. usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
  1625. usba_ep[0].ep.ops = &usba_ep_ops;
  1626. usba_ep[0].ep.name = pdata->ep[0].name;
  1627. usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
  1628. usba_ep[0].udc = &the_udc;
  1629. INIT_LIST_HEAD(&usba_ep[0].queue);
  1630. usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
  1631. usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
  1632. usba_ep[0].index = pdata->ep[0].index;
  1633. usba_ep[0].can_dma = pdata->ep[0].can_dma;
  1634. usba_ep[0].can_isoc = pdata->ep[0].can_isoc;
  1635. for (i = 1; i < pdata->num_ep; i++) {
  1636. struct usba_ep *ep = &usba_ep[i];
  1637. ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
  1638. ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
  1639. ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
  1640. ep->ep.ops = &usba_ep_ops;
  1641. ep->ep.name = pdata->ep[i].name;
  1642. ep->ep.maxpacket = pdata->ep[i].fifo_size;
  1643. ep->udc = &the_udc;
  1644. INIT_LIST_HEAD(&ep->queue);
  1645. ep->fifo_size = pdata->ep[i].fifo_size;
  1646. ep->nr_banks = pdata->ep[i].nr_banks;
  1647. ep->index = pdata->ep[i].index;
  1648. ep->can_dma = pdata->ep[i].can_dma;
  1649. ep->can_isoc = pdata->ep[i].can_isoc;
  1650. list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
  1651. }
  1652. ret = request_irq(irq, usba_udc_irq, 0, "atmel_usba_udc", udc);
  1653. if (ret) {
  1654. dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
  1655. irq, ret);
  1656. goto err_request_irq;
  1657. }
  1658. udc->irq = irq;
  1659. ret = device_add(&udc->gadget.dev);
  1660. if (ret) {
  1661. dev_dbg(&pdev->dev, "Could not add gadget: %d\n", ret);
  1662. goto err_device_add;
  1663. }
  1664. if (gpio_is_valid(pdata->vbus_pin)) {
  1665. if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
  1666. udc->vbus_pin = pdata->vbus_pin;
  1667. udc->vbus_pin_inverted = pdata->vbus_pin_inverted;
  1668. ret = request_irq(gpio_to_irq(udc->vbus_pin),
  1669. usba_vbus_irq, 0,
  1670. "atmel_usba_udc", udc);
  1671. if (ret) {
  1672. gpio_free(udc->vbus_pin);
  1673. udc->vbus_pin = -ENODEV;
  1674. dev_warn(&udc->pdev->dev,
  1675. "failed to request vbus irq; "
  1676. "assuming always on\n");
  1677. } else {
  1678. disable_irq(gpio_to_irq(udc->vbus_pin));
  1679. }
  1680. } else {
  1681. /* gpio_request fail so use -EINVAL for gpio_is_valid */
  1682. udc->vbus_pin = -EINVAL;
  1683. }
  1684. }
  1685. usba_init_debugfs(udc);
  1686. for (i = 1; i < pdata->num_ep; i++)
  1687. usba_ep_init_debugfs(udc, &usba_ep[i]);
  1688. return 0;
  1689. err_device_add:
  1690. free_irq(irq, udc);
  1691. err_request_irq:
  1692. kfree(usba_ep);
  1693. err_alloc_ep:
  1694. iounmap(udc->fifo);
  1695. err_map_fifo:
  1696. iounmap(udc->regs);
  1697. err_map_regs:
  1698. clk_put(hclk);
  1699. err_get_hclk:
  1700. clk_put(pclk);
  1701. platform_set_drvdata(pdev, NULL);
  1702. return ret;
  1703. }
  1704. static int __exit usba_udc_remove(struct platform_device *pdev)
  1705. {
  1706. struct usba_udc *udc;
  1707. int i;
  1708. struct usba_platform_data *pdata = pdev->dev.platform_data;
  1709. udc = platform_get_drvdata(pdev);
  1710. for (i = 1; i < pdata->num_ep; i++)
  1711. usba_ep_cleanup_debugfs(&usba_ep[i]);
  1712. usba_cleanup_debugfs(udc);
  1713. if (gpio_is_valid(udc->vbus_pin)) {
  1714. free_irq(gpio_to_irq(udc->vbus_pin), udc);
  1715. gpio_free(udc->vbus_pin);
  1716. }
  1717. free_irq(udc->irq, udc);
  1718. kfree(usba_ep);
  1719. iounmap(udc->fifo);
  1720. iounmap(udc->regs);
  1721. clk_put(udc->hclk);
  1722. clk_put(udc->pclk);
  1723. device_unregister(&udc->gadget.dev);
  1724. return 0;
  1725. }
  1726. static struct platform_driver udc_driver = {
  1727. .remove = __exit_p(usba_udc_remove),
  1728. .driver = {
  1729. .name = "atmel_usba_udc",
  1730. .owner = THIS_MODULE,
  1731. },
  1732. };
  1733. static int __init udc_init(void)
  1734. {
  1735. return platform_driver_probe(&udc_driver, usba_udc_probe);
  1736. }
  1737. module_init(udc_init);
  1738. static void __exit udc_exit(void)
  1739. {
  1740. platform_driver_unregister(&udc_driver);
  1741. }
  1742. module_exit(udc_exit);
  1743. MODULE_DESCRIPTION("Atmel USBA UDC driver");
  1744. MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
  1745. MODULE_LICENSE("GPL");
  1746. MODULE_ALIAS("platform:atmel_usba_udc");