qeth_core_main.c 130 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007, 2009
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/tcp.h>
  19. #include <linux/mii.h>
  20. #include <linux/kthread.h>
  21. #include <linux/slab.h>
  22. #include <asm/ebcdic.h>
  23. #include <asm/io.h>
  24. #include "qeth_core.h"
  25. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  26. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  27. /* N P A M L V H */
  28. [QETH_DBF_SETUP] = {"qeth_setup",
  29. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  30. [QETH_DBF_MSG] = {"qeth_msg",
  31. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  32. [QETH_DBF_CTRL] = {"qeth_control",
  33. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  34. };
  35. EXPORT_SYMBOL_GPL(qeth_dbf);
  36. struct qeth_card_list_struct qeth_core_card_list;
  37. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  38. struct kmem_cache *qeth_core_header_cache;
  39. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  40. static struct device *qeth_core_root_dev;
  41. static unsigned int known_devices[][6] = QETH_MODELLIST_ARRAY;
  42. static struct lock_class_key qdio_out_skb_queue_key;
  43. static void qeth_send_control_data_cb(struct qeth_channel *,
  44. struct qeth_cmd_buffer *);
  45. static int qeth_issue_next_read(struct qeth_card *);
  46. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  47. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  48. static void qeth_free_buffer_pool(struct qeth_card *);
  49. static int qeth_qdio_establish(struct qeth_card *);
  50. static inline const char *qeth_get_cardname(struct qeth_card *card)
  51. {
  52. if (card->info.guestlan) {
  53. switch (card->info.type) {
  54. case QETH_CARD_TYPE_OSD:
  55. return " Guest LAN QDIO";
  56. case QETH_CARD_TYPE_IQD:
  57. return " Guest LAN Hiper";
  58. case QETH_CARD_TYPE_OSM:
  59. return " Guest LAN QDIO - OSM";
  60. case QETH_CARD_TYPE_OSX:
  61. return " Guest LAN QDIO - OSX";
  62. default:
  63. return " unknown";
  64. }
  65. } else {
  66. switch (card->info.type) {
  67. case QETH_CARD_TYPE_OSD:
  68. return " OSD Express";
  69. case QETH_CARD_TYPE_IQD:
  70. return " HiperSockets";
  71. case QETH_CARD_TYPE_OSN:
  72. return " OSN QDIO";
  73. case QETH_CARD_TYPE_OSM:
  74. return " OSM QDIO";
  75. case QETH_CARD_TYPE_OSX:
  76. return " OSX QDIO";
  77. default:
  78. return " unknown";
  79. }
  80. }
  81. return " n/a";
  82. }
  83. /* max length to be returned: 14 */
  84. const char *qeth_get_cardname_short(struct qeth_card *card)
  85. {
  86. if (card->info.guestlan) {
  87. switch (card->info.type) {
  88. case QETH_CARD_TYPE_OSD:
  89. return "GuestLAN QDIO";
  90. case QETH_CARD_TYPE_IQD:
  91. return "GuestLAN Hiper";
  92. case QETH_CARD_TYPE_OSM:
  93. return "GuestLAN OSM";
  94. case QETH_CARD_TYPE_OSX:
  95. return "GuestLAN OSX";
  96. default:
  97. return "unknown";
  98. }
  99. } else {
  100. switch (card->info.type) {
  101. case QETH_CARD_TYPE_OSD:
  102. switch (card->info.link_type) {
  103. case QETH_LINK_TYPE_FAST_ETH:
  104. return "OSD_100";
  105. case QETH_LINK_TYPE_HSTR:
  106. return "HSTR";
  107. case QETH_LINK_TYPE_GBIT_ETH:
  108. return "OSD_1000";
  109. case QETH_LINK_TYPE_10GBIT_ETH:
  110. return "OSD_10GIG";
  111. case QETH_LINK_TYPE_LANE_ETH100:
  112. return "OSD_FE_LANE";
  113. case QETH_LINK_TYPE_LANE_TR:
  114. return "OSD_TR_LANE";
  115. case QETH_LINK_TYPE_LANE_ETH1000:
  116. return "OSD_GbE_LANE";
  117. case QETH_LINK_TYPE_LANE:
  118. return "OSD_ATM_LANE";
  119. default:
  120. return "OSD_Express";
  121. }
  122. case QETH_CARD_TYPE_IQD:
  123. return "HiperSockets";
  124. case QETH_CARD_TYPE_OSN:
  125. return "OSN";
  126. case QETH_CARD_TYPE_OSM:
  127. return "OSM_1000";
  128. case QETH_CARD_TYPE_OSX:
  129. return "OSX_10GIG";
  130. default:
  131. return "unknown";
  132. }
  133. }
  134. return "n/a";
  135. }
  136. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  137. int clear_start_mask)
  138. {
  139. unsigned long flags;
  140. spin_lock_irqsave(&card->thread_mask_lock, flags);
  141. card->thread_allowed_mask = threads;
  142. if (clear_start_mask)
  143. card->thread_start_mask &= threads;
  144. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  145. wake_up(&card->wait_q);
  146. }
  147. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  148. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  149. {
  150. unsigned long flags;
  151. int rc = 0;
  152. spin_lock_irqsave(&card->thread_mask_lock, flags);
  153. rc = (card->thread_running_mask & threads);
  154. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  155. return rc;
  156. }
  157. EXPORT_SYMBOL_GPL(qeth_threads_running);
  158. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  159. {
  160. return wait_event_interruptible(card->wait_q,
  161. qeth_threads_running(card, threads) == 0);
  162. }
  163. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  164. void qeth_clear_working_pool_list(struct qeth_card *card)
  165. {
  166. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  167. QETH_CARD_TEXT(card, 5, "clwrklst");
  168. list_for_each_entry_safe(pool_entry, tmp,
  169. &card->qdio.in_buf_pool.entry_list, list){
  170. list_del(&pool_entry->list);
  171. }
  172. }
  173. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  174. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  175. {
  176. struct qeth_buffer_pool_entry *pool_entry;
  177. void *ptr;
  178. int i, j;
  179. QETH_CARD_TEXT(card, 5, "alocpool");
  180. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  181. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  182. if (!pool_entry) {
  183. qeth_free_buffer_pool(card);
  184. return -ENOMEM;
  185. }
  186. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  187. ptr = (void *) __get_free_page(GFP_KERNEL);
  188. if (!ptr) {
  189. while (j > 0)
  190. free_page((unsigned long)
  191. pool_entry->elements[--j]);
  192. kfree(pool_entry);
  193. qeth_free_buffer_pool(card);
  194. return -ENOMEM;
  195. }
  196. pool_entry->elements[j] = ptr;
  197. }
  198. list_add(&pool_entry->init_list,
  199. &card->qdio.init_pool.entry_list);
  200. }
  201. return 0;
  202. }
  203. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  204. {
  205. QETH_CARD_TEXT(card, 2, "realcbp");
  206. if ((card->state != CARD_STATE_DOWN) &&
  207. (card->state != CARD_STATE_RECOVER))
  208. return -EPERM;
  209. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  210. qeth_clear_working_pool_list(card);
  211. qeth_free_buffer_pool(card);
  212. card->qdio.in_buf_pool.buf_count = bufcnt;
  213. card->qdio.init_pool.buf_count = bufcnt;
  214. return qeth_alloc_buffer_pool(card);
  215. }
  216. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  217. static int qeth_issue_next_read(struct qeth_card *card)
  218. {
  219. int rc;
  220. struct qeth_cmd_buffer *iob;
  221. QETH_CARD_TEXT(card, 5, "issnxrd");
  222. if (card->read.state != CH_STATE_UP)
  223. return -EIO;
  224. iob = qeth_get_buffer(&card->read);
  225. if (!iob) {
  226. dev_warn(&card->gdev->dev, "The qeth device driver "
  227. "failed to recover an error on the device\n");
  228. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  229. "available\n", dev_name(&card->gdev->dev));
  230. return -ENOMEM;
  231. }
  232. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  233. QETH_CARD_TEXT(card, 6, "noirqpnd");
  234. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  235. (addr_t) iob, 0, 0);
  236. if (rc) {
  237. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  238. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  239. atomic_set(&card->read.irq_pending, 0);
  240. card->read_or_write_problem = 1;
  241. qeth_schedule_recovery(card);
  242. wake_up(&card->wait_q);
  243. }
  244. return rc;
  245. }
  246. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  247. {
  248. struct qeth_reply *reply;
  249. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  250. if (reply) {
  251. atomic_set(&reply->refcnt, 1);
  252. atomic_set(&reply->received, 0);
  253. reply->card = card;
  254. };
  255. return reply;
  256. }
  257. static void qeth_get_reply(struct qeth_reply *reply)
  258. {
  259. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  260. atomic_inc(&reply->refcnt);
  261. }
  262. static void qeth_put_reply(struct qeth_reply *reply)
  263. {
  264. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  265. if (atomic_dec_and_test(&reply->refcnt))
  266. kfree(reply);
  267. }
  268. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  269. struct qeth_card *card)
  270. {
  271. char *ipa_name;
  272. int com = cmd->hdr.command;
  273. ipa_name = qeth_get_ipa_cmd_name(com);
  274. if (rc)
  275. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  276. ipa_name, com, QETH_CARD_IFNAME(card),
  277. rc, qeth_get_ipa_msg(rc));
  278. else
  279. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  280. ipa_name, com, QETH_CARD_IFNAME(card));
  281. }
  282. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  283. struct qeth_cmd_buffer *iob)
  284. {
  285. struct qeth_ipa_cmd *cmd = NULL;
  286. QETH_CARD_TEXT(card, 5, "chkipad");
  287. if (IS_IPA(iob->data)) {
  288. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  289. if (IS_IPA_REPLY(cmd)) {
  290. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  291. cmd->hdr.command != IPA_CMD_DELCCID &&
  292. cmd->hdr.command != IPA_CMD_MODCCID &&
  293. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  294. qeth_issue_ipa_msg(cmd,
  295. cmd->hdr.return_code, card);
  296. return cmd;
  297. } else {
  298. switch (cmd->hdr.command) {
  299. case IPA_CMD_STOPLAN:
  300. dev_warn(&card->gdev->dev,
  301. "The link for interface %s on CHPID"
  302. " 0x%X failed\n",
  303. QETH_CARD_IFNAME(card),
  304. card->info.chpid);
  305. card->lan_online = 0;
  306. if (card->dev && netif_carrier_ok(card->dev))
  307. netif_carrier_off(card->dev);
  308. return NULL;
  309. case IPA_CMD_STARTLAN:
  310. dev_info(&card->gdev->dev,
  311. "The link for %s on CHPID 0x%X has"
  312. " been restored\n",
  313. QETH_CARD_IFNAME(card),
  314. card->info.chpid);
  315. netif_carrier_on(card->dev);
  316. card->lan_online = 1;
  317. qeth_schedule_recovery(card);
  318. return NULL;
  319. case IPA_CMD_MODCCID:
  320. return cmd;
  321. case IPA_CMD_REGISTER_LOCAL_ADDR:
  322. QETH_CARD_TEXT(card, 3, "irla");
  323. break;
  324. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  325. QETH_CARD_TEXT(card, 3, "urla");
  326. break;
  327. default:
  328. QETH_DBF_MESSAGE(2, "Received data is IPA "
  329. "but not a reply!\n");
  330. break;
  331. }
  332. }
  333. }
  334. return cmd;
  335. }
  336. void qeth_clear_ipacmd_list(struct qeth_card *card)
  337. {
  338. struct qeth_reply *reply, *r;
  339. unsigned long flags;
  340. QETH_CARD_TEXT(card, 4, "clipalst");
  341. spin_lock_irqsave(&card->lock, flags);
  342. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  343. qeth_get_reply(reply);
  344. reply->rc = -EIO;
  345. atomic_inc(&reply->received);
  346. list_del_init(&reply->list);
  347. wake_up(&reply->wait_q);
  348. qeth_put_reply(reply);
  349. }
  350. spin_unlock_irqrestore(&card->lock, flags);
  351. atomic_set(&card->write.irq_pending, 0);
  352. }
  353. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  354. static int qeth_check_idx_response(struct qeth_card *card,
  355. unsigned char *buffer)
  356. {
  357. if (!buffer)
  358. return 0;
  359. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  360. if ((buffer[2] & 0xc0) == 0xc0) {
  361. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  362. "with cause code 0x%02x%s\n",
  363. buffer[4],
  364. ((buffer[4] == 0x22) ?
  365. " -- try another portname" : ""));
  366. QETH_CARD_TEXT(card, 2, "ckidxres");
  367. QETH_CARD_TEXT(card, 2, " idxterm");
  368. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  369. if (buffer[4] == 0xf6) {
  370. dev_err(&card->gdev->dev,
  371. "The qeth device is not configured "
  372. "for the OSI layer required by z/VM\n");
  373. return -EPERM;
  374. }
  375. return -EIO;
  376. }
  377. return 0;
  378. }
  379. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  380. __u32 len)
  381. {
  382. struct qeth_card *card;
  383. card = CARD_FROM_CDEV(channel->ccwdev);
  384. QETH_CARD_TEXT(card, 4, "setupccw");
  385. if (channel == &card->read)
  386. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  387. else
  388. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  389. channel->ccw.count = len;
  390. channel->ccw.cda = (__u32) __pa(iob);
  391. }
  392. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  393. {
  394. __u8 index;
  395. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "getbuff");
  396. index = channel->io_buf_no;
  397. do {
  398. if (channel->iob[index].state == BUF_STATE_FREE) {
  399. channel->iob[index].state = BUF_STATE_LOCKED;
  400. channel->io_buf_no = (channel->io_buf_no + 1) %
  401. QETH_CMD_BUFFER_NO;
  402. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  403. return channel->iob + index;
  404. }
  405. index = (index + 1) % QETH_CMD_BUFFER_NO;
  406. } while (index != channel->io_buf_no);
  407. return NULL;
  408. }
  409. void qeth_release_buffer(struct qeth_channel *channel,
  410. struct qeth_cmd_buffer *iob)
  411. {
  412. unsigned long flags;
  413. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "relbuff");
  414. spin_lock_irqsave(&channel->iob_lock, flags);
  415. memset(iob->data, 0, QETH_BUFSIZE);
  416. iob->state = BUF_STATE_FREE;
  417. iob->callback = qeth_send_control_data_cb;
  418. iob->rc = 0;
  419. spin_unlock_irqrestore(&channel->iob_lock, flags);
  420. }
  421. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  422. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  423. {
  424. struct qeth_cmd_buffer *buffer = NULL;
  425. unsigned long flags;
  426. spin_lock_irqsave(&channel->iob_lock, flags);
  427. buffer = __qeth_get_buffer(channel);
  428. spin_unlock_irqrestore(&channel->iob_lock, flags);
  429. return buffer;
  430. }
  431. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  432. {
  433. struct qeth_cmd_buffer *buffer;
  434. wait_event(channel->wait_q,
  435. ((buffer = qeth_get_buffer(channel)) != NULL));
  436. return buffer;
  437. }
  438. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  439. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  440. {
  441. int cnt;
  442. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  443. qeth_release_buffer(channel, &channel->iob[cnt]);
  444. channel->buf_no = 0;
  445. channel->io_buf_no = 0;
  446. }
  447. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  448. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  449. struct qeth_cmd_buffer *iob)
  450. {
  451. struct qeth_card *card;
  452. struct qeth_reply *reply, *r;
  453. struct qeth_ipa_cmd *cmd;
  454. unsigned long flags;
  455. int keep_reply;
  456. int rc = 0;
  457. card = CARD_FROM_CDEV(channel->ccwdev);
  458. QETH_CARD_TEXT(card, 4, "sndctlcb");
  459. rc = qeth_check_idx_response(card, iob->data);
  460. switch (rc) {
  461. case 0:
  462. break;
  463. case -EIO:
  464. qeth_clear_ipacmd_list(card);
  465. qeth_schedule_recovery(card);
  466. /* fall through */
  467. default:
  468. goto out;
  469. }
  470. cmd = qeth_check_ipa_data(card, iob);
  471. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  472. goto out;
  473. /*in case of OSN : check if cmd is set */
  474. if (card->info.type == QETH_CARD_TYPE_OSN &&
  475. cmd &&
  476. cmd->hdr.command != IPA_CMD_STARTLAN &&
  477. card->osn_info.assist_cb != NULL) {
  478. card->osn_info.assist_cb(card->dev, cmd);
  479. goto out;
  480. }
  481. spin_lock_irqsave(&card->lock, flags);
  482. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  483. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  484. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  485. qeth_get_reply(reply);
  486. list_del_init(&reply->list);
  487. spin_unlock_irqrestore(&card->lock, flags);
  488. keep_reply = 0;
  489. if (reply->callback != NULL) {
  490. if (cmd) {
  491. reply->offset = (__u16)((char *)cmd -
  492. (char *)iob->data);
  493. keep_reply = reply->callback(card,
  494. reply,
  495. (unsigned long)cmd);
  496. } else
  497. keep_reply = reply->callback(card,
  498. reply,
  499. (unsigned long)iob);
  500. }
  501. if (cmd)
  502. reply->rc = (u16) cmd->hdr.return_code;
  503. else if (iob->rc)
  504. reply->rc = iob->rc;
  505. if (keep_reply) {
  506. spin_lock_irqsave(&card->lock, flags);
  507. list_add_tail(&reply->list,
  508. &card->cmd_waiter_list);
  509. spin_unlock_irqrestore(&card->lock, flags);
  510. } else {
  511. atomic_inc(&reply->received);
  512. wake_up(&reply->wait_q);
  513. }
  514. qeth_put_reply(reply);
  515. goto out;
  516. }
  517. }
  518. spin_unlock_irqrestore(&card->lock, flags);
  519. out:
  520. memcpy(&card->seqno.pdu_hdr_ack,
  521. QETH_PDU_HEADER_SEQ_NO(iob->data),
  522. QETH_SEQ_NO_LENGTH);
  523. qeth_release_buffer(channel, iob);
  524. }
  525. static int qeth_setup_channel(struct qeth_channel *channel)
  526. {
  527. int cnt;
  528. QETH_DBF_TEXT(SETUP, 2, "setupch");
  529. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  530. channel->iob[cnt].data =
  531. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  532. if (channel->iob[cnt].data == NULL)
  533. break;
  534. channel->iob[cnt].state = BUF_STATE_FREE;
  535. channel->iob[cnt].channel = channel;
  536. channel->iob[cnt].callback = qeth_send_control_data_cb;
  537. channel->iob[cnt].rc = 0;
  538. }
  539. if (cnt < QETH_CMD_BUFFER_NO) {
  540. while (cnt-- > 0)
  541. kfree(channel->iob[cnt].data);
  542. return -ENOMEM;
  543. }
  544. channel->buf_no = 0;
  545. channel->io_buf_no = 0;
  546. atomic_set(&channel->irq_pending, 0);
  547. spin_lock_init(&channel->iob_lock);
  548. init_waitqueue_head(&channel->wait_q);
  549. return 0;
  550. }
  551. static int qeth_set_thread_start_bit(struct qeth_card *card,
  552. unsigned long thread)
  553. {
  554. unsigned long flags;
  555. spin_lock_irqsave(&card->thread_mask_lock, flags);
  556. if (!(card->thread_allowed_mask & thread) ||
  557. (card->thread_start_mask & thread)) {
  558. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  559. return -EPERM;
  560. }
  561. card->thread_start_mask |= thread;
  562. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  563. return 0;
  564. }
  565. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  566. {
  567. unsigned long flags;
  568. spin_lock_irqsave(&card->thread_mask_lock, flags);
  569. card->thread_start_mask &= ~thread;
  570. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  571. wake_up(&card->wait_q);
  572. }
  573. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  574. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  575. {
  576. unsigned long flags;
  577. spin_lock_irqsave(&card->thread_mask_lock, flags);
  578. card->thread_running_mask &= ~thread;
  579. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  580. wake_up(&card->wait_q);
  581. }
  582. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  583. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  584. {
  585. unsigned long flags;
  586. int rc = 0;
  587. spin_lock_irqsave(&card->thread_mask_lock, flags);
  588. if (card->thread_start_mask & thread) {
  589. if ((card->thread_allowed_mask & thread) &&
  590. !(card->thread_running_mask & thread)) {
  591. rc = 1;
  592. card->thread_start_mask &= ~thread;
  593. card->thread_running_mask |= thread;
  594. } else
  595. rc = -EPERM;
  596. }
  597. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  598. return rc;
  599. }
  600. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  601. {
  602. int rc = 0;
  603. wait_event(card->wait_q,
  604. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  605. return rc;
  606. }
  607. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  608. void qeth_schedule_recovery(struct qeth_card *card)
  609. {
  610. QETH_CARD_TEXT(card, 2, "startrec");
  611. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  612. schedule_work(&card->kernel_thread_starter);
  613. }
  614. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  615. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  616. {
  617. int dstat, cstat;
  618. char *sense;
  619. struct qeth_card *card;
  620. sense = (char *) irb->ecw;
  621. cstat = irb->scsw.cmd.cstat;
  622. dstat = irb->scsw.cmd.dstat;
  623. card = CARD_FROM_CDEV(cdev);
  624. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  625. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  626. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  627. QETH_CARD_TEXT(card, 2, "CGENCHK");
  628. dev_warn(&cdev->dev, "The qeth device driver "
  629. "failed to recover an error on the device\n");
  630. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x\n",
  631. dev_name(&cdev->dev), dstat, cstat);
  632. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  633. 16, 1, irb, 64, 1);
  634. return 1;
  635. }
  636. if (dstat & DEV_STAT_UNIT_CHECK) {
  637. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  638. SENSE_RESETTING_EVENT_FLAG) {
  639. QETH_CARD_TEXT(card, 2, "REVIND");
  640. return 1;
  641. }
  642. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  643. SENSE_COMMAND_REJECT_FLAG) {
  644. QETH_CARD_TEXT(card, 2, "CMDREJi");
  645. return 1;
  646. }
  647. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  648. QETH_CARD_TEXT(card, 2, "AFFE");
  649. return 1;
  650. }
  651. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  652. QETH_CARD_TEXT(card, 2, "ZEROSEN");
  653. return 0;
  654. }
  655. QETH_CARD_TEXT(card, 2, "DGENCHK");
  656. return 1;
  657. }
  658. return 0;
  659. }
  660. static long __qeth_check_irb_error(struct ccw_device *cdev,
  661. unsigned long intparm, struct irb *irb)
  662. {
  663. struct qeth_card *card;
  664. card = CARD_FROM_CDEV(cdev);
  665. if (!IS_ERR(irb))
  666. return 0;
  667. switch (PTR_ERR(irb)) {
  668. case -EIO:
  669. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  670. dev_name(&cdev->dev));
  671. QETH_CARD_TEXT(card, 2, "ckirberr");
  672. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  673. break;
  674. case -ETIMEDOUT:
  675. dev_warn(&cdev->dev, "A hardware operation timed out"
  676. " on the device\n");
  677. QETH_CARD_TEXT(card, 2, "ckirberr");
  678. QETH_CARD_TEXT_(card, 2, " rc%d", -ETIMEDOUT);
  679. if (intparm == QETH_RCD_PARM) {
  680. if (card && (card->data.ccwdev == cdev)) {
  681. card->data.state = CH_STATE_DOWN;
  682. wake_up(&card->wait_q);
  683. }
  684. }
  685. break;
  686. default:
  687. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  688. dev_name(&cdev->dev), PTR_ERR(irb));
  689. QETH_CARD_TEXT(card, 2, "ckirberr");
  690. QETH_CARD_TEXT(card, 2, " rc???");
  691. }
  692. return PTR_ERR(irb);
  693. }
  694. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  695. struct irb *irb)
  696. {
  697. int rc;
  698. int cstat, dstat;
  699. struct qeth_cmd_buffer *buffer;
  700. struct qeth_channel *channel;
  701. struct qeth_card *card;
  702. struct qeth_cmd_buffer *iob;
  703. __u8 index;
  704. if (__qeth_check_irb_error(cdev, intparm, irb))
  705. return;
  706. cstat = irb->scsw.cmd.cstat;
  707. dstat = irb->scsw.cmd.dstat;
  708. card = CARD_FROM_CDEV(cdev);
  709. if (!card)
  710. return;
  711. QETH_CARD_TEXT(card, 5, "irq");
  712. if (card->read.ccwdev == cdev) {
  713. channel = &card->read;
  714. QETH_CARD_TEXT(card, 5, "read");
  715. } else if (card->write.ccwdev == cdev) {
  716. channel = &card->write;
  717. QETH_CARD_TEXT(card, 5, "write");
  718. } else {
  719. channel = &card->data;
  720. QETH_CARD_TEXT(card, 5, "data");
  721. }
  722. atomic_set(&channel->irq_pending, 0);
  723. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  724. channel->state = CH_STATE_STOPPED;
  725. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  726. channel->state = CH_STATE_HALTED;
  727. /*let's wake up immediately on data channel*/
  728. if ((channel == &card->data) && (intparm != 0) &&
  729. (intparm != QETH_RCD_PARM))
  730. goto out;
  731. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  732. QETH_CARD_TEXT(card, 6, "clrchpar");
  733. /* we don't have to handle this further */
  734. intparm = 0;
  735. }
  736. if (intparm == QETH_HALT_CHANNEL_PARM) {
  737. QETH_CARD_TEXT(card, 6, "hltchpar");
  738. /* we don't have to handle this further */
  739. intparm = 0;
  740. }
  741. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  742. (dstat & DEV_STAT_UNIT_CHECK) ||
  743. (cstat)) {
  744. if (irb->esw.esw0.erw.cons) {
  745. dev_warn(&channel->ccwdev->dev,
  746. "The qeth device driver failed to recover "
  747. "an error on the device\n");
  748. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  749. "0x%X dstat 0x%X\n",
  750. dev_name(&channel->ccwdev->dev), cstat, dstat);
  751. print_hex_dump(KERN_WARNING, "qeth: irb ",
  752. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  753. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  754. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  755. }
  756. if (intparm == QETH_RCD_PARM) {
  757. channel->state = CH_STATE_DOWN;
  758. goto out;
  759. }
  760. rc = qeth_get_problem(cdev, irb);
  761. if (rc) {
  762. qeth_clear_ipacmd_list(card);
  763. qeth_schedule_recovery(card);
  764. goto out;
  765. }
  766. }
  767. if (intparm == QETH_RCD_PARM) {
  768. channel->state = CH_STATE_RCD_DONE;
  769. goto out;
  770. }
  771. if (intparm) {
  772. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  773. buffer->state = BUF_STATE_PROCESSED;
  774. }
  775. if (channel == &card->data)
  776. return;
  777. if (channel == &card->read &&
  778. channel->state == CH_STATE_UP)
  779. qeth_issue_next_read(card);
  780. iob = channel->iob;
  781. index = channel->buf_no;
  782. while (iob[index].state == BUF_STATE_PROCESSED) {
  783. if (iob[index].callback != NULL)
  784. iob[index].callback(channel, iob + index);
  785. index = (index + 1) % QETH_CMD_BUFFER_NO;
  786. }
  787. channel->buf_no = index;
  788. out:
  789. wake_up(&card->wait_q);
  790. return;
  791. }
  792. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  793. struct qeth_qdio_out_buffer *buf)
  794. {
  795. int i;
  796. struct sk_buff *skb;
  797. /* is PCI flag set on buffer? */
  798. if (buf->buffer->element[0].flags & 0x40)
  799. atomic_dec(&queue->set_pci_flags_count);
  800. skb = skb_dequeue(&buf->skb_list);
  801. while (skb) {
  802. atomic_dec(&skb->users);
  803. dev_kfree_skb_any(skb);
  804. skb = skb_dequeue(&buf->skb_list);
  805. }
  806. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  807. if (buf->buffer->element[i].addr && buf->is_header[i])
  808. kmem_cache_free(qeth_core_header_cache,
  809. buf->buffer->element[i].addr);
  810. buf->is_header[i] = 0;
  811. buf->buffer->element[i].length = 0;
  812. buf->buffer->element[i].addr = NULL;
  813. buf->buffer->element[i].flags = 0;
  814. }
  815. buf->buffer->element[15].flags = 0;
  816. buf->next_element_to_fill = 0;
  817. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  818. }
  819. void qeth_clear_qdio_buffers(struct qeth_card *card)
  820. {
  821. int i, j;
  822. QETH_CARD_TEXT(card, 2, "clearqdbf");
  823. /* clear outbound buffers to free skbs */
  824. for (i = 0; i < card->qdio.no_out_queues; ++i)
  825. if (card->qdio.out_qs[i]) {
  826. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  827. qeth_clear_output_buffer(card->qdio.out_qs[i],
  828. &card->qdio.out_qs[i]->bufs[j]);
  829. }
  830. }
  831. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  832. static void qeth_free_buffer_pool(struct qeth_card *card)
  833. {
  834. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  835. int i = 0;
  836. list_for_each_entry_safe(pool_entry, tmp,
  837. &card->qdio.init_pool.entry_list, init_list){
  838. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  839. free_page((unsigned long)pool_entry->elements[i]);
  840. list_del(&pool_entry->init_list);
  841. kfree(pool_entry);
  842. }
  843. }
  844. static void qeth_free_qdio_buffers(struct qeth_card *card)
  845. {
  846. int i, j;
  847. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  848. QETH_QDIO_UNINITIALIZED)
  849. return;
  850. kfree(card->qdio.in_q);
  851. card->qdio.in_q = NULL;
  852. /* inbound buffer pool */
  853. qeth_free_buffer_pool(card);
  854. /* free outbound qdio_qs */
  855. if (card->qdio.out_qs) {
  856. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  857. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  858. qeth_clear_output_buffer(card->qdio.out_qs[i],
  859. &card->qdio.out_qs[i]->bufs[j]);
  860. kfree(card->qdio.out_qs[i]);
  861. }
  862. kfree(card->qdio.out_qs);
  863. card->qdio.out_qs = NULL;
  864. }
  865. }
  866. static void qeth_clean_channel(struct qeth_channel *channel)
  867. {
  868. int cnt;
  869. QETH_DBF_TEXT(SETUP, 2, "freech");
  870. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  871. kfree(channel->iob[cnt].data);
  872. }
  873. static void qeth_get_channel_path_desc(struct qeth_card *card)
  874. {
  875. struct ccw_device *ccwdev;
  876. struct channelPath_dsc {
  877. u8 flags;
  878. u8 lsn;
  879. u8 desc;
  880. u8 chpid;
  881. u8 swla;
  882. u8 zeroes;
  883. u8 chla;
  884. u8 chpp;
  885. } *chp_dsc;
  886. QETH_DBF_TEXT(SETUP, 2, "chp_desc");
  887. ccwdev = card->data.ccwdev;
  888. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  889. if (chp_dsc != NULL) {
  890. /* CHPP field bit 6 == 1 -> single queue */
  891. if ((chp_dsc->chpp & 0x02) == 0x02)
  892. card->qdio.no_out_queues = 1;
  893. card->info.func_level = 0x4100 + chp_dsc->desc;
  894. kfree(chp_dsc);
  895. }
  896. if (card->qdio.no_out_queues == 1) {
  897. card->qdio.default_out_queue = 0;
  898. dev_info(&card->gdev->dev,
  899. "Priority Queueing not supported\n");
  900. }
  901. QETH_DBF_TEXT_(SETUP, 2, "nr:%x", card->qdio.no_out_queues);
  902. QETH_DBF_TEXT_(SETUP, 2, "lvl:%02x", card->info.func_level);
  903. return;
  904. }
  905. static void qeth_init_qdio_info(struct qeth_card *card)
  906. {
  907. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  908. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  909. /* inbound */
  910. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  911. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  912. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  913. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  914. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  915. }
  916. static void qeth_set_intial_options(struct qeth_card *card)
  917. {
  918. card->options.route4.type = NO_ROUTER;
  919. card->options.route6.type = NO_ROUTER;
  920. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  921. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  922. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  923. card->options.fake_broadcast = 0;
  924. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  925. card->options.performance_stats = 0;
  926. card->options.rx_sg_cb = QETH_RX_SG_CB;
  927. card->options.isolation = ISOLATION_MODE_NONE;
  928. }
  929. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  930. {
  931. unsigned long flags;
  932. int rc = 0;
  933. spin_lock_irqsave(&card->thread_mask_lock, flags);
  934. QETH_CARD_TEXT_(card, 4, " %02x%02x%02x",
  935. (u8) card->thread_start_mask,
  936. (u8) card->thread_allowed_mask,
  937. (u8) card->thread_running_mask);
  938. rc = (card->thread_start_mask & thread);
  939. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  940. return rc;
  941. }
  942. static void qeth_start_kernel_thread(struct work_struct *work)
  943. {
  944. struct qeth_card *card = container_of(work, struct qeth_card,
  945. kernel_thread_starter);
  946. QETH_CARD_TEXT(card , 2, "strthrd");
  947. if (card->read.state != CH_STATE_UP &&
  948. card->write.state != CH_STATE_UP)
  949. return;
  950. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  951. kthread_run(card->discipline.recover, (void *) card,
  952. "qeth_recover");
  953. }
  954. static int qeth_setup_card(struct qeth_card *card)
  955. {
  956. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  957. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  958. card->read.state = CH_STATE_DOWN;
  959. card->write.state = CH_STATE_DOWN;
  960. card->data.state = CH_STATE_DOWN;
  961. card->state = CARD_STATE_DOWN;
  962. card->lan_online = 0;
  963. card->use_hard_stop = 0;
  964. card->read_or_write_problem = 0;
  965. card->dev = NULL;
  966. spin_lock_init(&card->vlanlock);
  967. spin_lock_init(&card->mclock);
  968. card->vlangrp = NULL;
  969. spin_lock_init(&card->lock);
  970. spin_lock_init(&card->ip_lock);
  971. spin_lock_init(&card->thread_mask_lock);
  972. mutex_init(&card->conf_mutex);
  973. mutex_init(&card->discipline_mutex);
  974. card->thread_start_mask = 0;
  975. card->thread_allowed_mask = 0;
  976. card->thread_running_mask = 0;
  977. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  978. INIT_LIST_HEAD(&card->ip_list);
  979. INIT_LIST_HEAD(card->ip_tbd_list);
  980. INIT_LIST_HEAD(&card->cmd_waiter_list);
  981. init_waitqueue_head(&card->wait_q);
  982. /* intial options */
  983. qeth_set_intial_options(card);
  984. /* IP address takeover */
  985. INIT_LIST_HEAD(&card->ipato.entries);
  986. card->ipato.enabled = 0;
  987. card->ipato.invert4 = 0;
  988. card->ipato.invert6 = 0;
  989. /* init QDIO stuff */
  990. qeth_init_qdio_info(card);
  991. return 0;
  992. }
  993. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  994. {
  995. struct qeth_card *card = container_of(slr, struct qeth_card,
  996. qeth_service_level);
  997. if (card->info.mcl_level[0])
  998. seq_printf(m, "qeth: %s firmware level %s\n",
  999. CARD_BUS_ID(card), card->info.mcl_level);
  1000. }
  1001. static struct qeth_card *qeth_alloc_card(void)
  1002. {
  1003. struct qeth_card *card;
  1004. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1005. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1006. if (!card)
  1007. goto out;
  1008. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1009. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1010. if (!card->ip_tbd_list) {
  1011. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1012. goto out_card;
  1013. }
  1014. if (qeth_setup_channel(&card->read))
  1015. goto out_ip;
  1016. if (qeth_setup_channel(&card->write))
  1017. goto out_channel;
  1018. card->options.layer2 = -1;
  1019. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1020. register_service_level(&card->qeth_service_level);
  1021. return card;
  1022. out_channel:
  1023. qeth_clean_channel(&card->read);
  1024. out_ip:
  1025. kfree(card->ip_tbd_list);
  1026. out_card:
  1027. kfree(card);
  1028. out:
  1029. return NULL;
  1030. }
  1031. static int qeth_determine_card_type(struct qeth_card *card)
  1032. {
  1033. int i = 0;
  1034. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1035. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1036. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1037. while (known_devices[i][QETH_DEV_MODEL_IND]) {
  1038. if ((CARD_RDEV(card)->id.dev_type ==
  1039. known_devices[i][QETH_DEV_TYPE_IND]) &&
  1040. (CARD_RDEV(card)->id.dev_model ==
  1041. known_devices[i][QETH_DEV_MODEL_IND])) {
  1042. card->info.type = known_devices[i][QETH_DEV_MODEL_IND];
  1043. card->qdio.no_out_queues =
  1044. known_devices[i][QETH_QUEUE_NO_IND];
  1045. card->info.is_multicast_different =
  1046. known_devices[i][QETH_MULTICAST_IND];
  1047. qeth_get_channel_path_desc(card);
  1048. return 0;
  1049. }
  1050. i++;
  1051. }
  1052. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1053. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1054. "unknown type\n");
  1055. return -ENOENT;
  1056. }
  1057. static int qeth_clear_channel(struct qeth_channel *channel)
  1058. {
  1059. unsigned long flags;
  1060. struct qeth_card *card;
  1061. int rc;
  1062. card = CARD_FROM_CDEV(channel->ccwdev);
  1063. QETH_CARD_TEXT(card, 3, "clearch");
  1064. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1065. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1066. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1067. if (rc)
  1068. return rc;
  1069. rc = wait_event_interruptible_timeout(card->wait_q,
  1070. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1071. if (rc == -ERESTARTSYS)
  1072. return rc;
  1073. if (channel->state != CH_STATE_STOPPED)
  1074. return -ETIME;
  1075. channel->state = CH_STATE_DOWN;
  1076. return 0;
  1077. }
  1078. static int qeth_halt_channel(struct qeth_channel *channel)
  1079. {
  1080. unsigned long flags;
  1081. struct qeth_card *card;
  1082. int rc;
  1083. card = CARD_FROM_CDEV(channel->ccwdev);
  1084. QETH_CARD_TEXT(card, 3, "haltch");
  1085. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1086. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1087. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1088. if (rc)
  1089. return rc;
  1090. rc = wait_event_interruptible_timeout(card->wait_q,
  1091. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1092. if (rc == -ERESTARTSYS)
  1093. return rc;
  1094. if (channel->state != CH_STATE_HALTED)
  1095. return -ETIME;
  1096. return 0;
  1097. }
  1098. static int qeth_halt_channels(struct qeth_card *card)
  1099. {
  1100. int rc1 = 0, rc2 = 0, rc3 = 0;
  1101. QETH_CARD_TEXT(card, 3, "haltchs");
  1102. rc1 = qeth_halt_channel(&card->read);
  1103. rc2 = qeth_halt_channel(&card->write);
  1104. rc3 = qeth_halt_channel(&card->data);
  1105. if (rc1)
  1106. return rc1;
  1107. if (rc2)
  1108. return rc2;
  1109. return rc3;
  1110. }
  1111. static int qeth_clear_channels(struct qeth_card *card)
  1112. {
  1113. int rc1 = 0, rc2 = 0, rc3 = 0;
  1114. QETH_CARD_TEXT(card, 3, "clearchs");
  1115. rc1 = qeth_clear_channel(&card->read);
  1116. rc2 = qeth_clear_channel(&card->write);
  1117. rc3 = qeth_clear_channel(&card->data);
  1118. if (rc1)
  1119. return rc1;
  1120. if (rc2)
  1121. return rc2;
  1122. return rc3;
  1123. }
  1124. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1125. {
  1126. int rc = 0;
  1127. QETH_CARD_TEXT(card, 3, "clhacrd");
  1128. if (halt)
  1129. rc = qeth_halt_channels(card);
  1130. if (rc)
  1131. return rc;
  1132. return qeth_clear_channels(card);
  1133. }
  1134. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1135. {
  1136. int rc = 0;
  1137. QETH_CARD_TEXT(card, 3, "qdioclr");
  1138. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1139. QETH_QDIO_CLEANING)) {
  1140. case QETH_QDIO_ESTABLISHED:
  1141. if (card->info.type == QETH_CARD_TYPE_IQD)
  1142. rc = qdio_shutdown(CARD_DDEV(card),
  1143. QDIO_FLAG_CLEANUP_USING_HALT);
  1144. else
  1145. rc = qdio_shutdown(CARD_DDEV(card),
  1146. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1147. if (rc)
  1148. QETH_CARD_TEXT_(card, 3, "1err%d", rc);
  1149. qdio_free(CARD_DDEV(card));
  1150. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1151. break;
  1152. case QETH_QDIO_CLEANING:
  1153. return rc;
  1154. default:
  1155. break;
  1156. }
  1157. rc = qeth_clear_halt_card(card, use_halt);
  1158. if (rc)
  1159. QETH_CARD_TEXT_(card, 3, "2err%d", rc);
  1160. card->state = CARD_STATE_DOWN;
  1161. return rc;
  1162. }
  1163. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1164. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1165. int *length)
  1166. {
  1167. struct ciw *ciw;
  1168. char *rcd_buf;
  1169. int ret;
  1170. struct qeth_channel *channel = &card->data;
  1171. unsigned long flags;
  1172. /*
  1173. * scan for RCD command in extended SenseID data
  1174. */
  1175. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1176. if (!ciw || ciw->cmd == 0)
  1177. return -EOPNOTSUPP;
  1178. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1179. if (!rcd_buf)
  1180. return -ENOMEM;
  1181. channel->ccw.cmd_code = ciw->cmd;
  1182. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1183. channel->ccw.count = ciw->count;
  1184. channel->ccw.flags = CCW_FLAG_SLI;
  1185. channel->state = CH_STATE_RCD;
  1186. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1187. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1188. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1189. QETH_RCD_TIMEOUT);
  1190. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1191. if (!ret)
  1192. wait_event(card->wait_q,
  1193. (channel->state == CH_STATE_RCD_DONE ||
  1194. channel->state == CH_STATE_DOWN));
  1195. if (channel->state == CH_STATE_DOWN)
  1196. ret = -EIO;
  1197. else
  1198. channel->state = CH_STATE_DOWN;
  1199. if (ret) {
  1200. kfree(rcd_buf);
  1201. *buffer = NULL;
  1202. *length = 0;
  1203. } else {
  1204. *length = ciw->count;
  1205. *buffer = rcd_buf;
  1206. }
  1207. return ret;
  1208. }
  1209. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1210. {
  1211. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1212. card->info.chpid = prcd[30];
  1213. card->info.unit_addr2 = prcd[31];
  1214. card->info.cula = prcd[63];
  1215. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1216. (prcd[0x11] == _ascebc['M']));
  1217. }
  1218. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1219. {
  1220. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1221. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 && prcd[76] == 0xF5) {
  1222. card->info.blkt.time_total = 250;
  1223. card->info.blkt.inter_packet = 5;
  1224. card->info.blkt.inter_packet_jumbo = 15;
  1225. } else {
  1226. card->info.blkt.time_total = 0;
  1227. card->info.blkt.inter_packet = 0;
  1228. card->info.blkt.inter_packet_jumbo = 0;
  1229. }
  1230. }
  1231. static void qeth_init_tokens(struct qeth_card *card)
  1232. {
  1233. card->token.issuer_rm_w = 0x00010103UL;
  1234. card->token.cm_filter_w = 0x00010108UL;
  1235. card->token.cm_connection_w = 0x0001010aUL;
  1236. card->token.ulp_filter_w = 0x0001010bUL;
  1237. card->token.ulp_connection_w = 0x0001010dUL;
  1238. }
  1239. static void qeth_init_func_level(struct qeth_card *card)
  1240. {
  1241. switch (card->info.type) {
  1242. case QETH_CARD_TYPE_IQD:
  1243. card->info.func_level = QETH_IDX_FUNC_LEVEL_IQD;
  1244. break;
  1245. case QETH_CARD_TYPE_OSD:
  1246. case QETH_CARD_TYPE_OSN:
  1247. card->info.func_level = QETH_IDX_FUNC_LEVEL_OSD;
  1248. break;
  1249. default:
  1250. break;
  1251. }
  1252. }
  1253. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1254. void (*idx_reply_cb)(struct qeth_channel *,
  1255. struct qeth_cmd_buffer *))
  1256. {
  1257. struct qeth_cmd_buffer *iob;
  1258. unsigned long flags;
  1259. int rc;
  1260. struct qeth_card *card;
  1261. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1262. card = CARD_FROM_CDEV(channel->ccwdev);
  1263. iob = qeth_get_buffer(channel);
  1264. iob->callback = idx_reply_cb;
  1265. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1266. channel->ccw.count = QETH_BUFSIZE;
  1267. channel->ccw.cda = (__u32) __pa(iob->data);
  1268. wait_event(card->wait_q,
  1269. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1270. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1271. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1272. rc = ccw_device_start(channel->ccwdev,
  1273. &channel->ccw, (addr_t) iob, 0, 0);
  1274. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1275. if (rc) {
  1276. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1277. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1278. atomic_set(&channel->irq_pending, 0);
  1279. wake_up(&card->wait_q);
  1280. return rc;
  1281. }
  1282. rc = wait_event_interruptible_timeout(card->wait_q,
  1283. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1284. if (rc == -ERESTARTSYS)
  1285. return rc;
  1286. if (channel->state != CH_STATE_UP) {
  1287. rc = -ETIME;
  1288. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1289. qeth_clear_cmd_buffers(channel);
  1290. } else
  1291. rc = 0;
  1292. return rc;
  1293. }
  1294. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1295. void (*idx_reply_cb)(struct qeth_channel *,
  1296. struct qeth_cmd_buffer *))
  1297. {
  1298. struct qeth_card *card;
  1299. struct qeth_cmd_buffer *iob;
  1300. unsigned long flags;
  1301. __u16 temp;
  1302. __u8 tmp;
  1303. int rc;
  1304. struct ccw_dev_id temp_devid;
  1305. card = CARD_FROM_CDEV(channel->ccwdev);
  1306. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1307. iob = qeth_get_buffer(channel);
  1308. iob->callback = idx_reply_cb;
  1309. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1310. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1311. channel->ccw.cda = (__u32) __pa(iob->data);
  1312. if (channel == &card->write) {
  1313. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1314. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1315. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1316. card->seqno.trans_hdr++;
  1317. } else {
  1318. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1319. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1320. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1321. }
  1322. tmp = ((__u8)card->info.portno) | 0x80;
  1323. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1324. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1325. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1326. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1327. &card->info.func_level, sizeof(__u16));
  1328. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1329. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1330. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1331. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1332. wait_event(card->wait_q,
  1333. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1334. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1335. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1336. rc = ccw_device_start(channel->ccwdev,
  1337. &channel->ccw, (addr_t) iob, 0, 0);
  1338. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1339. if (rc) {
  1340. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1341. rc);
  1342. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1343. atomic_set(&channel->irq_pending, 0);
  1344. wake_up(&card->wait_q);
  1345. return rc;
  1346. }
  1347. rc = wait_event_interruptible_timeout(card->wait_q,
  1348. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1349. if (rc == -ERESTARTSYS)
  1350. return rc;
  1351. if (channel->state != CH_STATE_ACTIVATING) {
  1352. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1353. " failed to recover an error on the device\n");
  1354. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1355. dev_name(&channel->ccwdev->dev));
  1356. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1357. qeth_clear_cmd_buffers(channel);
  1358. return -ETIME;
  1359. }
  1360. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1361. }
  1362. static int qeth_peer_func_level(int level)
  1363. {
  1364. if ((level & 0xff) == 8)
  1365. return (level & 0xff) + 0x400;
  1366. if (((level >> 8) & 3) == 1)
  1367. return (level & 0xff) + 0x200;
  1368. return level;
  1369. }
  1370. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1371. struct qeth_cmd_buffer *iob)
  1372. {
  1373. struct qeth_card *card;
  1374. __u16 temp;
  1375. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1376. if (channel->state == CH_STATE_DOWN) {
  1377. channel->state = CH_STATE_ACTIVATING;
  1378. goto out;
  1379. }
  1380. card = CARD_FROM_CDEV(channel->ccwdev);
  1381. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1382. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == QETH_IDX_ACT_ERR_EXCL)
  1383. dev_err(&card->write.ccwdev->dev,
  1384. "The adapter is used exclusively by another "
  1385. "host\n");
  1386. else
  1387. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1388. " negative reply\n",
  1389. dev_name(&card->write.ccwdev->dev));
  1390. goto out;
  1391. }
  1392. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1393. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1394. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1395. "function level mismatch (sent: 0x%x, received: "
  1396. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1397. card->info.func_level, temp);
  1398. goto out;
  1399. }
  1400. channel->state = CH_STATE_UP;
  1401. out:
  1402. qeth_release_buffer(channel, iob);
  1403. }
  1404. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1405. struct qeth_cmd_buffer *iob)
  1406. {
  1407. struct qeth_card *card;
  1408. __u16 temp;
  1409. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1410. if (channel->state == CH_STATE_DOWN) {
  1411. channel->state = CH_STATE_ACTIVATING;
  1412. goto out;
  1413. }
  1414. card = CARD_FROM_CDEV(channel->ccwdev);
  1415. if (qeth_check_idx_response(card, iob->data))
  1416. goto out;
  1417. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1418. switch (QETH_IDX_ACT_CAUSE_CODE(iob->data)) {
  1419. case QETH_IDX_ACT_ERR_EXCL:
  1420. dev_err(&card->write.ccwdev->dev,
  1421. "The adapter is used exclusively by another "
  1422. "host\n");
  1423. break;
  1424. case QETH_IDX_ACT_ERR_AUTH:
  1425. case QETH_IDX_ACT_ERR_AUTH_USER:
  1426. dev_err(&card->read.ccwdev->dev,
  1427. "Setting the device online failed because of "
  1428. "insufficient authorization\n");
  1429. break;
  1430. default:
  1431. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1432. " negative reply\n",
  1433. dev_name(&card->read.ccwdev->dev));
  1434. }
  1435. QETH_CARD_TEXT_(card, 2, "idxread%c",
  1436. QETH_IDX_ACT_CAUSE_CODE(iob->data));
  1437. goto out;
  1438. }
  1439. /**
  1440. * * temporary fix for microcode bug
  1441. * * to revert it,replace OR by AND
  1442. * */
  1443. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1444. (card->info.type == QETH_CARD_TYPE_OSD))
  1445. card->info.portname_required = 1;
  1446. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1447. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1448. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1449. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1450. dev_name(&card->read.ccwdev->dev),
  1451. card->info.func_level, temp);
  1452. goto out;
  1453. }
  1454. memcpy(&card->token.issuer_rm_r,
  1455. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1456. QETH_MPC_TOKEN_LENGTH);
  1457. memcpy(&card->info.mcl_level[0],
  1458. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1459. channel->state = CH_STATE_UP;
  1460. out:
  1461. qeth_release_buffer(channel, iob);
  1462. }
  1463. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1464. struct qeth_cmd_buffer *iob)
  1465. {
  1466. qeth_setup_ccw(&card->write, iob->data, len);
  1467. iob->callback = qeth_release_buffer;
  1468. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1469. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1470. card->seqno.trans_hdr++;
  1471. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1472. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1473. card->seqno.pdu_hdr++;
  1474. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1475. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1476. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1477. }
  1478. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1479. int qeth_send_control_data(struct qeth_card *card, int len,
  1480. struct qeth_cmd_buffer *iob,
  1481. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1482. unsigned long),
  1483. void *reply_param)
  1484. {
  1485. int rc;
  1486. unsigned long flags;
  1487. struct qeth_reply *reply = NULL;
  1488. unsigned long timeout, event_timeout;
  1489. struct qeth_ipa_cmd *cmd;
  1490. QETH_CARD_TEXT(card, 2, "sendctl");
  1491. if (card->read_or_write_problem) {
  1492. qeth_release_buffer(iob->channel, iob);
  1493. return -EIO;
  1494. }
  1495. reply = qeth_alloc_reply(card);
  1496. if (!reply) {
  1497. return -ENOMEM;
  1498. }
  1499. reply->callback = reply_cb;
  1500. reply->param = reply_param;
  1501. if (card->state == CARD_STATE_DOWN)
  1502. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1503. else
  1504. reply->seqno = card->seqno.ipa++;
  1505. init_waitqueue_head(&reply->wait_q);
  1506. spin_lock_irqsave(&card->lock, flags);
  1507. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1508. spin_unlock_irqrestore(&card->lock, flags);
  1509. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1510. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1511. qeth_prepare_control_data(card, len, iob);
  1512. if (IS_IPA(iob->data))
  1513. event_timeout = QETH_IPA_TIMEOUT;
  1514. else
  1515. event_timeout = QETH_TIMEOUT;
  1516. timeout = jiffies + event_timeout;
  1517. QETH_CARD_TEXT(card, 6, "noirqpnd");
  1518. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1519. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1520. (addr_t) iob, 0, 0);
  1521. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1522. if (rc) {
  1523. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1524. "ccw_device_start rc = %i\n",
  1525. dev_name(&card->write.ccwdev->dev), rc);
  1526. QETH_CARD_TEXT_(card, 2, " err%d", rc);
  1527. spin_lock_irqsave(&card->lock, flags);
  1528. list_del_init(&reply->list);
  1529. qeth_put_reply(reply);
  1530. spin_unlock_irqrestore(&card->lock, flags);
  1531. qeth_release_buffer(iob->channel, iob);
  1532. atomic_set(&card->write.irq_pending, 0);
  1533. wake_up(&card->wait_q);
  1534. return rc;
  1535. }
  1536. /* we have only one long running ipassist, since we can ensure
  1537. process context of this command we can sleep */
  1538. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1539. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1540. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1541. if (!wait_event_timeout(reply->wait_q,
  1542. atomic_read(&reply->received), event_timeout))
  1543. goto time_err;
  1544. } else {
  1545. while (!atomic_read(&reply->received)) {
  1546. if (time_after(jiffies, timeout))
  1547. goto time_err;
  1548. cpu_relax();
  1549. };
  1550. }
  1551. rc = reply->rc;
  1552. qeth_put_reply(reply);
  1553. return rc;
  1554. time_err:
  1555. spin_lock_irqsave(&reply->card->lock, flags);
  1556. list_del_init(&reply->list);
  1557. spin_unlock_irqrestore(&reply->card->lock, flags);
  1558. reply->rc = -ETIME;
  1559. atomic_inc(&reply->received);
  1560. atomic_set(&card->write.irq_pending, 0);
  1561. qeth_release_buffer(iob->channel, iob);
  1562. card->write.buf_no = (card->write.buf_no + 1) % QETH_CMD_BUFFER_NO;
  1563. wake_up(&reply->wait_q);
  1564. rc = reply->rc;
  1565. qeth_put_reply(reply);
  1566. return rc;
  1567. }
  1568. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1569. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1570. unsigned long data)
  1571. {
  1572. struct qeth_cmd_buffer *iob;
  1573. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1574. iob = (struct qeth_cmd_buffer *) data;
  1575. memcpy(&card->token.cm_filter_r,
  1576. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1577. QETH_MPC_TOKEN_LENGTH);
  1578. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1579. return 0;
  1580. }
  1581. static int qeth_cm_enable(struct qeth_card *card)
  1582. {
  1583. int rc;
  1584. struct qeth_cmd_buffer *iob;
  1585. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1586. iob = qeth_wait_for_buffer(&card->write);
  1587. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1588. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1589. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1590. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1591. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1592. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1593. qeth_cm_enable_cb, NULL);
  1594. return rc;
  1595. }
  1596. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1597. unsigned long data)
  1598. {
  1599. struct qeth_cmd_buffer *iob;
  1600. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1601. iob = (struct qeth_cmd_buffer *) data;
  1602. memcpy(&card->token.cm_connection_r,
  1603. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1604. QETH_MPC_TOKEN_LENGTH);
  1605. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1606. return 0;
  1607. }
  1608. static int qeth_cm_setup(struct qeth_card *card)
  1609. {
  1610. int rc;
  1611. struct qeth_cmd_buffer *iob;
  1612. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1613. iob = qeth_wait_for_buffer(&card->write);
  1614. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1615. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1616. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1617. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1618. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1619. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1620. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1621. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1622. qeth_cm_setup_cb, NULL);
  1623. return rc;
  1624. }
  1625. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1626. {
  1627. switch (card->info.type) {
  1628. case QETH_CARD_TYPE_UNKNOWN:
  1629. return 1500;
  1630. case QETH_CARD_TYPE_IQD:
  1631. return card->info.max_mtu;
  1632. case QETH_CARD_TYPE_OSD:
  1633. switch (card->info.link_type) {
  1634. case QETH_LINK_TYPE_HSTR:
  1635. case QETH_LINK_TYPE_LANE_TR:
  1636. return 2000;
  1637. default:
  1638. return 1492;
  1639. }
  1640. case QETH_CARD_TYPE_OSM:
  1641. case QETH_CARD_TYPE_OSX:
  1642. return 1492;
  1643. default:
  1644. return 1500;
  1645. }
  1646. }
  1647. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1648. {
  1649. switch (cardtype) {
  1650. case QETH_CARD_TYPE_UNKNOWN:
  1651. case QETH_CARD_TYPE_OSD:
  1652. case QETH_CARD_TYPE_OSN:
  1653. case QETH_CARD_TYPE_OSM:
  1654. case QETH_CARD_TYPE_OSX:
  1655. return 61440;
  1656. case QETH_CARD_TYPE_IQD:
  1657. return 57344;
  1658. default:
  1659. return 1500;
  1660. }
  1661. }
  1662. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1663. {
  1664. switch (cardtype) {
  1665. case QETH_CARD_TYPE_IQD:
  1666. return 1;
  1667. default:
  1668. return 0;
  1669. }
  1670. }
  1671. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1672. {
  1673. switch (framesize) {
  1674. case 0x4000:
  1675. return 8192;
  1676. case 0x6000:
  1677. return 16384;
  1678. case 0xa000:
  1679. return 32768;
  1680. case 0xffff:
  1681. return 57344;
  1682. default:
  1683. return 0;
  1684. }
  1685. }
  1686. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1687. {
  1688. switch (card->info.type) {
  1689. case QETH_CARD_TYPE_OSD:
  1690. case QETH_CARD_TYPE_OSM:
  1691. case QETH_CARD_TYPE_OSX:
  1692. return ((mtu >= 576) && (mtu <= 61440));
  1693. case QETH_CARD_TYPE_IQD:
  1694. return ((mtu >= 576) &&
  1695. (mtu <= card->info.max_mtu + 4096 - 32));
  1696. case QETH_CARD_TYPE_OSN:
  1697. case QETH_CARD_TYPE_UNKNOWN:
  1698. default:
  1699. return 1;
  1700. }
  1701. }
  1702. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1703. unsigned long data)
  1704. {
  1705. __u16 mtu, framesize;
  1706. __u16 len;
  1707. __u8 link_type;
  1708. struct qeth_cmd_buffer *iob;
  1709. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1710. iob = (struct qeth_cmd_buffer *) data;
  1711. memcpy(&card->token.ulp_filter_r,
  1712. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1713. QETH_MPC_TOKEN_LENGTH);
  1714. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1715. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1716. mtu = qeth_get_mtu_outof_framesize(framesize);
  1717. if (!mtu) {
  1718. iob->rc = -EINVAL;
  1719. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1720. return 0;
  1721. }
  1722. card->info.max_mtu = mtu;
  1723. card->info.initial_mtu = mtu;
  1724. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1725. } else {
  1726. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1727. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1728. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1729. }
  1730. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1731. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1732. memcpy(&link_type,
  1733. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1734. card->info.link_type = link_type;
  1735. } else
  1736. card->info.link_type = 0;
  1737. QETH_DBF_TEXT_(SETUP, 2, "link%d", card->info.link_type);
  1738. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1739. return 0;
  1740. }
  1741. static int qeth_ulp_enable(struct qeth_card *card)
  1742. {
  1743. int rc;
  1744. char prot_type;
  1745. struct qeth_cmd_buffer *iob;
  1746. /*FIXME: trace view callbacks*/
  1747. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1748. iob = qeth_wait_for_buffer(&card->write);
  1749. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1750. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1751. (__u8) card->info.portno;
  1752. if (card->options.layer2)
  1753. if (card->info.type == QETH_CARD_TYPE_OSN)
  1754. prot_type = QETH_PROT_OSN2;
  1755. else
  1756. prot_type = QETH_PROT_LAYER2;
  1757. else
  1758. prot_type = QETH_PROT_TCPIP;
  1759. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1760. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1761. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1762. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1763. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1764. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1765. card->info.portname, 9);
  1766. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1767. qeth_ulp_enable_cb, NULL);
  1768. return rc;
  1769. }
  1770. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1771. unsigned long data)
  1772. {
  1773. struct qeth_cmd_buffer *iob;
  1774. int rc = 0;
  1775. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1776. iob = (struct qeth_cmd_buffer *) data;
  1777. memcpy(&card->token.ulp_connection_r,
  1778. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1779. QETH_MPC_TOKEN_LENGTH);
  1780. if (!strncmp("00S", QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1781. 3)) {
  1782. QETH_DBF_TEXT(SETUP, 2, "olmlimit");
  1783. dev_err(&card->gdev->dev, "A connection could not be "
  1784. "established because of an OLM limit\n");
  1785. iob->rc = -EMLINK;
  1786. }
  1787. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1788. return rc;
  1789. }
  1790. static int qeth_ulp_setup(struct qeth_card *card)
  1791. {
  1792. int rc;
  1793. __u16 temp;
  1794. struct qeth_cmd_buffer *iob;
  1795. struct ccw_dev_id dev_id;
  1796. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1797. iob = qeth_wait_for_buffer(&card->write);
  1798. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1799. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1800. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1801. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1802. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1803. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1804. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1805. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1806. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1807. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1808. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1809. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1810. qeth_ulp_setup_cb, NULL);
  1811. return rc;
  1812. }
  1813. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1814. {
  1815. int i, j;
  1816. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1817. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1818. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1819. return 0;
  1820. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1821. GFP_KERNEL);
  1822. if (!card->qdio.in_q)
  1823. goto out_nomem;
  1824. QETH_DBF_TEXT(SETUP, 2, "inq");
  1825. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1826. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1827. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1828. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1829. card->qdio.in_q->bufs[i].buffer =
  1830. &card->qdio.in_q->qdio_bufs[i];
  1831. /* inbound buffer pool */
  1832. if (qeth_alloc_buffer_pool(card))
  1833. goto out_freeinq;
  1834. /* outbound */
  1835. card->qdio.out_qs =
  1836. kmalloc(card->qdio.no_out_queues *
  1837. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1838. if (!card->qdio.out_qs)
  1839. goto out_freepool;
  1840. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1841. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1842. GFP_KERNEL);
  1843. if (!card->qdio.out_qs[i])
  1844. goto out_freeoutq;
  1845. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1846. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1847. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1848. card->qdio.out_qs[i]->queue_no = i;
  1849. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1850. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1851. card->qdio.out_qs[i]->bufs[j].buffer =
  1852. &card->qdio.out_qs[i]->qdio_bufs[j];
  1853. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1854. skb_list);
  1855. lockdep_set_class(
  1856. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1857. &qdio_out_skb_queue_key);
  1858. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1859. }
  1860. }
  1861. return 0;
  1862. out_freeoutq:
  1863. while (i > 0)
  1864. kfree(card->qdio.out_qs[--i]);
  1865. kfree(card->qdio.out_qs);
  1866. card->qdio.out_qs = NULL;
  1867. out_freepool:
  1868. qeth_free_buffer_pool(card);
  1869. out_freeinq:
  1870. kfree(card->qdio.in_q);
  1871. card->qdio.in_q = NULL;
  1872. out_nomem:
  1873. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1874. return -ENOMEM;
  1875. }
  1876. static void qeth_create_qib_param_field(struct qeth_card *card,
  1877. char *param_field)
  1878. {
  1879. param_field[0] = _ascebc['P'];
  1880. param_field[1] = _ascebc['C'];
  1881. param_field[2] = _ascebc['I'];
  1882. param_field[3] = _ascebc['T'];
  1883. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1884. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1885. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1886. }
  1887. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1888. char *param_field)
  1889. {
  1890. param_field[16] = _ascebc['B'];
  1891. param_field[17] = _ascebc['L'];
  1892. param_field[18] = _ascebc['K'];
  1893. param_field[19] = _ascebc['T'];
  1894. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1895. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1896. *((unsigned int *) (&param_field[28])) =
  1897. card->info.blkt.inter_packet_jumbo;
  1898. }
  1899. static int qeth_qdio_activate(struct qeth_card *card)
  1900. {
  1901. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1902. return qdio_activate(CARD_DDEV(card));
  1903. }
  1904. static int qeth_dm_act(struct qeth_card *card)
  1905. {
  1906. int rc;
  1907. struct qeth_cmd_buffer *iob;
  1908. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1909. iob = qeth_wait_for_buffer(&card->write);
  1910. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1911. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1912. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1913. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1914. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1915. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1916. return rc;
  1917. }
  1918. static int qeth_mpc_initialize(struct qeth_card *card)
  1919. {
  1920. int rc;
  1921. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1922. rc = qeth_issue_next_read(card);
  1923. if (rc) {
  1924. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1925. return rc;
  1926. }
  1927. rc = qeth_cm_enable(card);
  1928. if (rc) {
  1929. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1930. goto out_qdio;
  1931. }
  1932. rc = qeth_cm_setup(card);
  1933. if (rc) {
  1934. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1935. goto out_qdio;
  1936. }
  1937. rc = qeth_ulp_enable(card);
  1938. if (rc) {
  1939. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1940. goto out_qdio;
  1941. }
  1942. rc = qeth_ulp_setup(card);
  1943. if (rc) {
  1944. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1945. goto out_qdio;
  1946. }
  1947. rc = qeth_alloc_qdio_buffers(card);
  1948. if (rc) {
  1949. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1950. goto out_qdio;
  1951. }
  1952. rc = qeth_qdio_establish(card);
  1953. if (rc) {
  1954. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1955. qeth_free_qdio_buffers(card);
  1956. goto out_qdio;
  1957. }
  1958. rc = qeth_qdio_activate(card);
  1959. if (rc) {
  1960. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1961. goto out_qdio;
  1962. }
  1963. rc = qeth_dm_act(card);
  1964. if (rc) {
  1965. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1966. goto out_qdio;
  1967. }
  1968. return 0;
  1969. out_qdio:
  1970. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1971. return rc;
  1972. }
  1973. static void qeth_print_status_with_portname(struct qeth_card *card)
  1974. {
  1975. char dbf_text[15];
  1976. int i;
  1977. sprintf(dbf_text, "%s", card->info.portname + 1);
  1978. for (i = 0; i < 8; i++)
  1979. dbf_text[i] =
  1980. (char) _ebcasc[(__u8) dbf_text[i]];
  1981. dbf_text[8] = 0;
  1982. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  1983. "with link type %s (portname: %s)\n",
  1984. qeth_get_cardname(card),
  1985. (card->info.mcl_level[0]) ? " (level: " : "",
  1986. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1987. (card->info.mcl_level[0]) ? ")" : "",
  1988. qeth_get_cardname_short(card),
  1989. dbf_text);
  1990. }
  1991. static void qeth_print_status_no_portname(struct qeth_card *card)
  1992. {
  1993. if (card->info.portname[0])
  1994. dev_info(&card->gdev->dev, "Device is a%s "
  1995. "card%s%s%s\nwith link type %s "
  1996. "(no portname needed by interface).\n",
  1997. qeth_get_cardname(card),
  1998. (card->info.mcl_level[0]) ? " (level: " : "",
  1999. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2000. (card->info.mcl_level[0]) ? ")" : "",
  2001. qeth_get_cardname_short(card));
  2002. else
  2003. dev_info(&card->gdev->dev, "Device is a%s "
  2004. "card%s%s%s\nwith link type %s.\n",
  2005. qeth_get_cardname(card),
  2006. (card->info.mcl_level[0]) ? " (level: " : "",
  2007. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2008. (card->info.mcl_level[0]) ? ")" : "",
  2009. qeth_get_cardname_short(card));
  2010. }
  2011. void qeth_print_status_message(struct qeth_card *card)
  2012. {
  2013. switch (card->info.type) {
  2014. case QETH_CARD_TYPE_OSD:
  2015. case QETH_CARD_TYPE_OSM:
  2016. case QETH_CARD_TYPE_OSX:
  2017. /* VM will use a non-zero first character
  2018. * to indicate a HiperSockets like reporting
  2019. * of the level OSA sets the first character to zero
  2020. * */
  2021. if (!card->info.mcl_level[0]) {
  2022. sprintf(card->info.mcl_level, "%02x%02x",
  2023. card->info.mcl_level[2],
  2024. card->info.mcl_level[3]);
  2025. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2026. break;
  2027. }
  2028. /* fallthrough */
  2029. case QETH_CARD_TYPE_IQD:
  2030. if ((card->info.guestlan) ||
  2031. (card->info.mcl_level[0] & 0x80)) {
  2032. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2033. card->info.mcl_level[0]];
  2034. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2035. card->info.mcl_level[1]];
  2036. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2037. card->info.mcl_level[2]];
  2038. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2039. card->info.mcl_level[3]];
  2040. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2041. }
  2042. break;
  2043. default:
  2044. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2045. }
  2046. if (card->info.portname_required)
  2047. qeth_print_status_with_portname(card);
  2048. else
  2049. qeth_print_status_no_portname(card);
  2050. }
  2051. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2052. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2053. {
  2054. struct qeth_buffer_pool_entry *entry;
  2055. QETH_CARD_TEXT(card, 5, "inwrklst");
  2056. list_for_each_entry(entry,
  2057. &card->qdio.init_pool.entry_list, init_list) {
  2058. qeth_put_buffer_pool_entry(card, entry);
  2059. }
  2060. }
  2061. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2062. struct qeth_card *card)
  2063. {
  2064. struct list_head *plh;
  2065. struct qeth_buffer_pool_entry *entry;
  2066. int i, free;
  2067. struct page *page;
  2068. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2069. return NULL;
  2070. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2071. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2072. free = 1;
  2073. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2074. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2075. free = 0;
  2076. break;
  2077. }
  2078. }
  2079. if (free) {
  2080. list_del_init(&entry->list);
  2081. return entry;
  2082. }
  2083. }
  2084. /* no free buffer in pool so take first one and swap pages */
  2085. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2086. struct qeth_buffer_pool_entry, list);
  2087. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2088. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2089. page = alloc_page(GFP_ATOMIC);
  2090. if (!page) {
  2091. return NULL;
  2092. } else {
  2093. free_page((unsigned long)entry->elements[i]);
  2094. entry->elements[i] = page_address(page);
  2095. if (card->options.performance_stats)
  2096. card->perf_stats.sg_alloc_page_rx++;
  2097. }
  2098. }
  2099. }
  2100. list_del_init(&entry->list);
  2101. return entry;
  2102. }
  2103. static int qeth_init_input_buffer(struct qeth_card *card,
  2104. struct qeth_qdio_buffer *buf)
  2105. {
  2106. struct qeth_buffer_pool_entry *pool_entry;
  2107. int i;
  2108. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2109. if (!pool_entry)
  2110. return 1;
  2111. /*
  2112. * since the buffer is accessed only from the input_tasklet
  2113. * there shouldn't be a need to synchronize; also, since we use
  2114. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2115. * buffers
  2116. */
  2117. buf->pool_entry = pool_entry;
  2118. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2119. buf->buffer->element[i].length = PAGE_SIZE;
  2120. buf->buffer->element[i].addr = pool_entry->elements[i];
  2121. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2122. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2123. else
  2124. buf->buffer->element[i].flags = 0;
  2125. }
  2126. return 0;
  2127. }
  2128. int qeth_init_qdio_queues(struct qeth_card *card)
  2129. {
  2130. int i, j;
  2131. int rc;
  2132. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2133. /* inbound queue */
  2134. memset(card->qdio.in_q->qdio_bufs, 0,
  2135. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2136. qeth_initialize_working_pool_list(card);
  2137. /*give only as many buffers to hardware as we have buffer pool entries*/
  2138. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2139. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2140. card->qdio.in_q->next_buf_to_init =
  2141. card->qdio.in_buf_pool.buf_count - 1;
  2142. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2143. card->qdio.in_buf_pool.buf_count - 1);
  2144. if (rc) {
  2145. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2146. return rc;
  2147. }
  2148. /* outbound queue */
  2149. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2150. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2151. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2152. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2153. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2154. &card->qdio.out_qs[i]->bufs[j]);
  2155. }
  2156. card->qdio.out_qs[i]->card = card;
  2157. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2158. card->qdio.out_qs[i]->do_pack = 0;
  2159. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2160. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2161. atomic_set(&card->qdio.out_qs[i]->state,
  2162. QETH_OUT_Q_UNLOCKED);
  2163. }
  2164. return 0;
  2165. }
  2166. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2167. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2168. {
  2169. switch (link_type) {
  2170. case QETH_LINK_TYPE_HSTR:
  2171. return 2;
  2172. default:
  2173. return 1;
  2174. }
  2175. }
  2176. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2177. struct qeth_ipa_cmd *cmd, __u8 command,
  2178. enum qeth_prot_versions prot)
  2179. {
  2180. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2181. cmd->hdr.command = command;
  2182. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2183. cmd->hdr.seqno = card->seqno.ipa;
  2184. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2185. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2186. if (card->options.layer2)
  2187. cmd->hdr.prim_version_no = 2;
  2188. else
  2189. cmd->hdr.prim_version_no = 1;
  2190. cmd->hdr.param_count = 1;
  2191. cmd->hdr.prot_version = prot;
  2192. cmd->hdr.ipa_supported = 0;
  2193. cmd->hdr.ipa_enabled = 0;
  2194. }
  2195. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2196. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2197. {
  2198. struct qeth_cmd_buffer *iob;
  2199. struct qeth_ipa_cmd *cmd;
  2200. iob = qeth_wait_for_buffer(&card->write);
  2201. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2202. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2203. return iob;
  2204. }
  2205. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2206. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2207. char prot_type)
  2208. {
  2209. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2210. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2211. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2212. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2213. }
  2214. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2215. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2216. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2217. unsigned long),
  2218. void *reply_param)
  2219. {
  2220. int rc;
  2221. char prot_type;
  2222. QETH_CARD_TEXT(card, 4, "sendipa");
  2223. if (card->options.layer2)
  2224. if (card->info.type == QETH_CARD_TYPE_OSN)
  2225. prot_type = QETH_PROT_OSN2;
  2226. else
  2227. prot_type = QETH_PROT_LAYER2;
  2228. else
  2229. prot_type = QETH_PROT_TCPIP;
  2230. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2231. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2232. iob, reply_cb, reply_param);
  2233. if (rc == -ETIME) {
  2234. qeth_clear_ipacmd_list(card);
  2235. qeth_schedule_recovery(card);
  2236. }
  2237. return rc;
  2238. }
  2239. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2240. static int qeth_send_startstoplan(struct qeth_card *card,
  2241. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2242. {
  2243. int rc;
  2244. struct qeth_cmd_buffer *iob;
  2245. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2246. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2247. return rc;
  2248. }
  2249. int qeth_send_startlan(struct qeth_card *card)
  2250. {
  2251. int rc;
  2252. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2253. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2254. return rc;
  2255. }
  2256. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2257. int qeth_send_stoplan(struct qeth_card *card)
  2258. {
  2259. int rc = 0;
  2260. /*
  2261. * TODO: according to the IPA format document page 14,
  2262. * TCP/IP (we!) never issue a STOPLAN
  2263. * is this right ?!?
  2264. */
  2265. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2266. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2267. return rc;
  2268. }
  2269. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2270. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2271. struct qeth_reply *reply, unsigned long data)
  2272. {
  2273. struct qeth_ipa_cmd *cmd;
  2274. QETH_CARD_TEXT(card, 4, "defadpcb");
  2275. cmd = (struct qeth_ipa_cmd *) data;
  2276. if (cmd->hdr.return_code == 0)
  2277. cmd->hdr.return_code =
  2278. cmd->data.setadapterparms.hdr.return_code;
  2279. return 0;
  2280. }
  2281. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2282. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2283. struct qeth_reply *reply, unsigned long data)
  2284. {
  2285. struct qeth_ipa_cmd *cmd;
  2286. QETH_CARD_TEXT(card, 3, "quyadpcb");
  2287. cmd = (struct qeth_ipa_cmd *) data;
  2288. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f) {
  2289. card->info.link_type =
  2290. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2291. QETH_DBF_TEXT_(SETUP, 2, "lnk %d", card->info.link_type);
  2292. }
  2293. card->options.adp.supported_funcs =
  2294. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2295. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2296. }
  2297. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2298. __u32 command, __u32 cmdlen)
  2299. {
  2300. struct qeth_cmd_buffer *iob;
  2301. struct qeth_ipa_cmd *cmd;
  2302. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2303. QETH_PROT_IPV4);
  2304. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2305. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2306. cmd->data.setadapterparms.hdr.command_code = command;
  2307. cmd->data.setadapterparms.hdr.used_total = 1;
  2308. cmd->data.setadapterparms.hdr.seq_no = 1;
  2309. return iob;
  2310. }
  2311. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2312. int qeth_query_setadapterparms(struct qeth_card *card)
  2313. {
  2314. int rc;
  2315. struct qeth_cmd_buffer *iob;
  2316. QETH_CARD_TEXT(card, 3, "queryadp");
  2317. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2318. sizeof(struct qeth_ipacmd_setadpparms));
  2319. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2320. return rc;
  2321. }
  2322. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2323. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2324. unsigned int qdio_error, const char *dbftext)
  2325. {
  2326. if (qdio_error) {
  2327. QETH_CARD_TEXT(card, 2, dbftext);
  2328. QETH_CARD_TEXT_(card, 2, " F15=%02X",
  2329. buf->element[15].flags & 0xff);
  2330. QETH_CARD_TEXT_(card, 2, " F14=%02X",
  2331. buf->element[14].flags & 0xff);
  2332. QETH_CARD_TEXT_(card, 2, " qerr=%X", qdio_error);
  2333. if ((buf->element[15].flags & 0xff) == 0x12) {
  2334. card->stats.rx_dropped++;
  2335. return 0;
  2336. } else
  2337. return 1;
  2338. }
  2339. return 0;
  2340. }
  2341. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2342. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2343. {
  2344. struct qeth_qdio_q *queue = card->qdio.in_q;
  2345. int count;
  2346. int i;
  2347. int rc;
  2348. int newcount = 0;
  2349. count = (index < queue->next_buf_to_init)?
  2350. card->qdio.in_buf_pool.buf_count -
  2351. (queue->next_buf_to_init - index) :
  2352. card->qdio.in_buf_pool.buf_count -
  2353. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2354. /* only requeue at a certain threshold to avoid SIGAs */
  2355. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2356. for (i = queue->next_buf_to_init;
  2357. i < queue->next_buf_to_init + count; ++i) {
  2358. if (qeth_init_input_buffer(card,
  2359. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2360. break;
  2361. } else {
  2362. newcount++;
  2363. }
  2364. }
  2365. if (newcount < count) {
  2366. /* we are in memory shortage so we switch back to
  2367. traditional skb allocation and drop packages */
  2368. atomic_set(&card->force_alloc_skb, 3);
  2369. count = newcount;
  2370. } else {
  2371. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2372. }
  2373. /*
  2374. * according to old code it should be avoided to requeue all
  2375. * 128 buffers in order to benefit from PCI avoidance.
  2376. * this function keeps at least one buffer (the buffer at
  2377. * 'index') un-requeued -> this buffer is the first buffer that
  2378. * will be requeued the next time
  2379. */
  2380. if (card->options.performance_stats) {
  2381. card->perf_stats.inbound_do_qdio_cnt++;
  2382. card->perf_stats.inbound_do_qdio_start_time =
  2383. qeth_get_micros();
  2384. }
  2385. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2386. queue->next_buf_to_init, count);
  2387. if (card->options.performance_stats)
  2388. card->perf_stats.inbound_do_qdio_time +=
  2389. qeth_get_micros() -
  2390. card->perf_stats.inbound_do_qdio_start_time;
  2391. if (rc) {
  2392. dev_warn(&card->gdev->dev,
  2393. "QDIO reported an error, rc=%i\n", rc);
  2394. QETH_CARD_TEXT(card, 2, "qinberr");
  2395. }
  2396. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2397. QDIO_MAX_BUFFERS_PER_Q;
  2398. }
  2399. }
  2400. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2401. static int qeth_handle_send_error(struct qeth_card *card,
  2402. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2403. {
  2404. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2405. QETH_CARD_TEXT(card, 6, "hdsnderr");
  2406. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2407. if (sbalf15 == 0) {
  2408. qdio_err = 0;
  2409. } else {
  2410. qdio_err = 1;
  2411. }
  2412. }
  2413. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2414. if (!qdio_err)
  2415. return QETH_SEND_ERROR_NONE;
  2416. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2417. return QETH_SEND_ERROR_RETRY;
  2418. QETH_CARD_TEXT(card, 1, "lnkfail");
  2419. QETH_CARD_TEXT_(card, 1, "%04x %02x",
  2420. (u16)qdio_err, (u8)sbalf15);
  2421. return QETH_SEND_ERROR_LINK_FAILURE;
  2422. }
  2423. /*
  2424. * Switched to packing state if the number of used buffers on a queue
  2425. * reaches a certain limit.
  2426. */
  2427. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2428. {
  2429. if (!queue->do_pack) {
  2430. if (atomic_read(&queue->used_buffers)
  2431. >= QETH_HIGH_WATERMARK_PACK){
  2432. /* switch non-PACKING -> PACKING */
  2433. QETH_CARD_TEXT(queue->card, 6, "np->pack");
  2434. if (queue->card->options.performance_stats)
  2435. queue->card->perf_stats.sc_dp_p++;
  2436. queue->do_pack = 1;
  2437. }
  2438. }
  2439. }
  2440. /*
  2441. * Switches from packing to non-packing mode. If there is a packing
  2442. * buffer on the queue this buffer will be prepared to be flushed.
  2443. * In that case 1 is returned to inform the caller. If no buffer
  2444. * has to be flushed, zero is returned.
  2445. */
  2446. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2447. {
  2448. struct qeth_qdio_out_buffer *buffer;
  2449. int flush_count = 0;
  2450. if (queue->do_pack) {
  2451. if (atomic_read(&queue->used_buffers)
  2452. <= QETH_LOW_WATERMARK_PACK) {
  2453. /* switch PACKING -> non-PACKING */
  2454. QETH_CARD_TEXT(queue->card, 6, "pack->np");
  2455. if (queue->card->options.performance_stats)
  2456. queue->card->perf_stats.sc_p_dp++;
  2457. queue->do_pack = 0;
  2458. /* flush packing buffers */
  2459. buffer = &queue->bufs[queue->next_buf_to_fill];
  2460. if ((atomic_read(&buffer->state) ==
  2461. QETH_QDIO_BUF_EMPTY) &&
  2462. (buffer->next_element_to_fill > 0)) {
  2463. atomic_set(&buffer->state,
  2464. QETH_QDIO_BUF_PRIMED);
  2465. flush_count++;
  2466. queue->next_buf_to_fill =
  2467. (queue->next_buf_to_fill + 1) %
  2468. QDIO_MAX_BUFFERS_PER_Q;
  2469. }
  2470. }
  2471. }
  2472. return flush_count;
  2473. }
  2474. /*
  2475. * Called to flush a packing buffer if no more pci flags are on the queue.
  2476. * Checks if there is a packing buffer and prepares it to be flushed.
  2477. * In that case returns 1, otherwise zero.
  2478. */
  2479. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2480. {
  2481. struct qeth_qdio_out_buffer *buffer;
  2482. buffer = &queue->bufs[queue->next_buf_to_fill];
  2483. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2484. (buffer->next_element_to_fill > 0)) {
  2485. /* it's a packing buffer */
  2486. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2487. queue->next_buf_to_fill =
  2488. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2489. return 1;
  2490. }
  2491. return 0;
  2492. }
  2493. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2494. int count)
  2495. {
  2496. struct qeth_qdio_out_buffer *buf;
  2497. int rc;
  2498. int i;
  2499. unsigned int qdio_flags;
  2500. for (i = index; i < index + count; ++i) {
  2501. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2502. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2503. SBAL_FLAGS_LAST_ENTRY;
  2504. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2505. continue;
  2506. if (!queue->do_pack) {
  2507. if ((atomic_read(&queue->used_buffers) >=
  2508. (QETH_HIGH_WATERMARK_PACK -
  2509. QETH_WATERMARK_PACK_FUZZ)) &&
  2510. !atomic_read(&queue->set_pci_flags_count)) {
  2511. /* it's likely that we'll go to packing
  2512. * mode soon */
  2513. atomic_inc(&queue->set_pci_flags_count);
  2514. buf->buffer->element[0].flags |= 0x40;
  2515. }
  2516. } else {
  2517. if (!atomic_read(&queue->set_pci_flags_count)) {
  2518. /*
  2519. * there's no outstanding PCI any more, so we
  2520. * have to request a PCI to be sure the the PCI
  2521. * will wake at some time in the future then we
  2522. * can flush packed buffers that might still be
  2523. * hanging around, which can happen if no
  2524. * further send was requested by the stack
  2525. */
  2526. atomic_inc(&queue->set_pci_flags_count);
  2527. buf->buffer->element[0].flags |= 0x40;
  2528. }
  2529. }
  2530. }
  2531. queue->card->dev->trans_start = jiffies;
  2532. if (queue->card->options.performance_stats) {
  2533. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2534. queue->card->perf_stats.outbound_do_qdio_start_time =
  2535. qeth_get_micros();
  2536. }
  2537. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2538. if (atomic_read(&queue->set_pci_flags_count))
  2539. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2540. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2541. queue->queue_no, index, count);
  2542. if (queue->card->options.performance_stats)
  2543. queue->card->perf_stats.outbound_do_qdio_time +=
  2544. qeth_get_micros() -
  2545. queue->card->perf_stats.outbound_do_qdio_start_time;
  2546. atomic_add(count, &queue->used_buffers);
  2547. if (rc) {
  2548. queue->card->stats.tx_errors += count;
  2549. /* ignore temporary SIGA errors without busy condition */
  2550. if (rc == QDIO_ERROR_SIGA_TARGET)
  2551. return;
  2552. QETH_CARD_TEXT(queue->card, 2, "flushbuf");
  2553. QETH_CARD_TEXT_(queue->card, 2, " err%d", rc);
  2554. /* this must not happen under normal circumstances. if it
  2555. * happens something is really wrong -> recover */
  2556. qeth_schedule_recovery(queue->card);
  2557. return;
  2558. }
  2559. if (queue->card->options.performance_stats)
  2560. queue->card->perf_stats.bufs_sent += count;
  2561. }
  2562. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2563. {
  2564. int index;
  2565. int flush_cnt = 0;
  2566. int q_was_packing = 0;
  2567. /*
  2568. * check if weed have to switch to non-packing mode or if
  2569. * we have to get a pci flag out on the queue
  2570. */
  2571. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2572. !atomic_read(&queue->set_pci_flags_count)) {
  2573. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2574. QETH_OUT_Q_UNLOCKED) {
  2575. /*
  2576. * If we get in here, there was no action in
  2577. * do_send_packet. So, we check if there is a
  2578. * packing buffer to be flushed here.
  2579. */
  2580. netif_stop_queue(queue->card->dev);
  2581. index = queue->next_buf_to_fill;
  2582. q_was_packing = queue->do_pack;
  2583. /* queue->do_pack may change */
  2584. barrier();
  2585. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2586. if (!flush_cnt &&
  2587. !atomic_read(&queue->set_pci_flags_count))
  2588. flush_cnt +=
  2589. qeth_flush_buffers_on_no_pci(queue);
  2590. if (queue->card->options.performance_stats &&
  2591. q_was_packing)
  2592. queue->card->perf_stats.bufs_sent_pack +=
  2593. flush_cnt;
  2594. if (flush_cnt)
  2595. qeth_flush_buffers(queue, index, flush_cnt);
  2596. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2597. }
  2598. }
  2599. }
  2600. void qeth_qdio_start_poll(struct ccw_device *ccwdev, int queue,
  2601. unsigned long card_ptr)
  2602. {
  2603. struct qeth_card *card = (struct qeth_card *)card_ptr;
  2604. if (card->dev && (card->dev->flags & IFF_UP))
  2605. napi_schedule(&card->napi);
  2606. }
  2607. EXPORT_SYMBOL_GPL(qeth_qdio_start_poll);
  2608. void qeth_qdio_input_handler(struct ccw_device *ccwdev, unsigned int qdio_err,
  2609. unsigned int queue, int first_element, int count,
  2610. unsigned long card_ptr)
  2611. {
  2612. struct qeth_card *card = (struct qeth_card *)card_ptr;
  2613. if (qdio_err)
  2614. qeth_schedule_recovery(card);
  2615. }
  2616. EXPORT_SYMBOL_GPL(qeth_qdio_input_handler);
  2617. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2618. unsigned int qdio_error, int __queue, int first_element,
  2619. int count, unsigned long card_ptr)
  2620. {
  2621. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2622. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2623. struct qeth_qdio_out_buffer *buffer;
  2624. int i;
  2625. QETH_CARD_TEXT(card, 6, "qdouhdl");
  2626. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2627. QETH_CARD_TEXT(card, 2, "achkcond");
  2628. netif_stop_queue(card->dev);
  2629. qeth_schedule_recovery(card);
  2630. return;
  2631. }
  2632. if (card->options.performance_stats) {
  2633. card->perf_stats.outbound_handler_cnt++;
  2634. card->perf_stats.outbound_handler_start_time =
  2635. qeth_get_micros();
  2636. }
  2637. for (i = first_element; i < (first_element + count); ++i) {
  2638. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2639. qeth_handle_send_error(card, buffer, qdio_error);
  2640. qeth_clear_output_buffer(queue, buffer);
  2641. }
  2642. atomic_sub(count, &queue->used_buffers);
  2643. /* check if we need to do something on this outbound queue */
  2644. if (card->info.type != QETH_CARD_TYPE_IQD)
  2645. qeth_check_outbound_queue(queue);
  2646. netif_wake_queue(queue->card->dev);
  2647. if (card->options.performance_stats)
  2648. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2649. card->perf_stats.outbound_handler_start_time;
  2650. }
  2651. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2652. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2653. int ipv, int cast_type)
  2654. {
  2655. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSD ||
  2656. card->info.type == QETH_CARD_TYPE_OSX))
  2657. return card->qdio.default_out_queue;
  2658. switch (card->qdio.no_out_queues) {
  2659. case 4:
  2660. if (cast_type && card->info.is_multicast_different)
  2661. return card->info.is_multicast_different &
  2662. (card->qdio.no_out_queues - 1);
  2663. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2664. const u8 tos = ip_hdr(skb)->tos;
  2665. if (card->qdio.do_prio_queueing ==
  2666. QETH_PRIO_Q_ING_TOS) {
  2667. if (tos & IP_TOS_NOTIMPORTANT)
  2668. return 3;
  2669. if (tos & IP_TOS_HIGHRELIABILITY)
  2670. return 2;
  2671. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2672. return 1;
  2673. if (tos & IP_TOS_LOWDELAY)
  2674. return 0;
  2675. }
  2676. if (card->qdio.do_prio_queueing ==
  2677. QETH_PRIO_Q_ING_PREC)
  2678. return 3 - (tos >> 6);
  2679. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2680. /* TODO: IPv6!!! */
  2681. }
  2682. return card->qdio.default_out_queue;
  2683. case 1: /* fallthrough for single-out-queue 1920-device */
  2684. default:
  2685. return card->qdio.default_out_queue;
  2686. }
  2687. }
  2688. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2689. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2690. struct sk_buff *skb, int elems)
  2691. {
  2692. int dlen = skb->len - skb->data_len;
  2693. int elements_needed = PFN_UP((unsigned long)skb->data + dlen - 1) -
  2694. PFN_DOWN((unsigned long)skb->data);
  2695. elements_needed += skb_shinfo(skb)->nr_frags;
  2696. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2697. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2698. "(Number=%d / Length=%d). Discarded.\n",
  2699. (elements_needed+elems), skb->len);
  2700. return 0;
  2701. }
  2702. return elements_needed;
  2703. }
  2704. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2705. int qeth_hdr_chk_and_bounce(struct sk_buff *skb, int len)
  2706. {
  2707. int hroom, inpage, rest;
  2708. if (((unsigned long)skb->data & PAGE_MASK) !=
  2709. (((unsigned long)skb->data + len - 1) & PAGE_MASK)) {
  2710. hroom = skb_headroom(skb);
  2711. inpage = PAGE_SIZE - ((unsigned long) skb->data % PAGE_SIZE);
  2712. rest = len - inpage;
  2713. if (rest > hroom)
  2714. return 1;
  2715. memmove(skb->data - rest, skb->data, skb->len - skb->data_len);
  2716. skb->data -= rest;
  2717. QETH_DBF_MESSAGE(2, "skb bounce len: %d rest: %d\n", len, rest);
  2718. }
  2719. return 0;
  2720. }
  2721. EXPORT_SYMBOL_GPL(qeth_hdr_chk_and_bounce);
  2722. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2723. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2724. int offset)
  2725. {
  2726. int length = skb->len - skb->data_len;
  2727. int length_here;
  2728. int element;
  2729. char *data;
  2730. int first_lap, cnt;
  2731. struct skb_frag_struct *frag;
  2732. element = *next_element_to_fill;
  2733. data = skb->data;
  2734. first_lap = (is_tso == 0 ? 1 : 0);
  2735. if (offset >= 0) {
  2736. data = skb->data + offset;
  2737. length -= offset;
  2738. first_lap = 0;
  2739. }
  2740. while (length > 0) {
  2741. /* length_here is the remaining amount of data in this page */
  2742. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2743. if (length < length_here)
  2744. length_here = length;
  2745. buffer->element[element].addr = data;
  2746. buffer->element[element].length = length_here;
  2747. length -= length_here;
  2748. if (!length) {
  2749. if (first_lap)
  2750. if (skb_shinfo(skb)->nr_frags)
  2751. buffer->element[element].flags =
  2752. SBAL_FLAGS_FIRST_FRAG;
  2753. else
  2754. buffer->element[element].flags = 0;
  2755. else
  2756. buffer->element[element].flags =
  2757. SBAL_FLAGS_MIDDLE_FRAG;
  2758. } else {
  2759. if (first_lap)
  2760. buffer->element[element].flags =
  2761. SBAL_FLAGS_FIRST_FRAG;
  2762. else
  2763. buffer->element[element].flags =
  2764. SBAL_FLAGS_MIDDLE_FRAG;
  2765. }
  2766. data += length_here;
  2767. element++;
  2768. first_lap = 0;
  2769. }
  2770. for (cnt = 0; cnt < skb_shinfo(skb)->nr_frags; cnt++) {
  2771. frag = &skb_shinfo(skb)->frags[cnt];
  2772. buffer->element[element].addr = (char *)page_to_phys(frag->page)
  2773. + frag->page_offset;
  2774. buffer->element[element].length = frag->size;
  2775. buffer->element[element].flags = SBAL_FLAGS_MIDDLE_FRAG;
  2776. element++;
  2777. }
  2778. if (buffer->element[element - 1].flags)
  2779. buffer->element[element - 1].flags = SBAL_FLAGS_LAST_FRAG;
  2780. *next_element_to_fill = element;
  2781. }
  2782. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2783. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2784. struct qeth_hdr *hdr, int offset, int hd_len)
  2785. {
  2786. struct qdio_buffer *buffer;
  2787. int flush_cnt = 0, hdr_len, large_send = 0;
  2788. buffer = buf->buffer;
  2789. atomic_inc(&skb->users);
  2790. skb_queue_tail(&buf->skb_list, skb);
  2791. /*check first on TSO ....*/
  2792. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2793. int element = buf->next_element_to_fill;
  2794. hdr_len = sizeof(struct qeth_hdr_tso) +
  2795. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2796. /*fill first buffer entry only with header information */
  2797. buffer->element[element].addr = skb->data;
  2798. buffer->element[element].length = hdr_len;
  2799. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2800. buf->next_element_to_fill++;
  2801. skb->data += hdr_len;
  2802. skb->len -= hdr_len;
  2803. large_send = 1;
  2804. }
  2805. if (offset >= 0) {
  2806. int element = buf->next_element_to_fill;
  2807. buffer->element[element].addr = hdr;
  2808. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2809. hd_len;
  2810. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2811. buf->is_header[element] = 1;
  2812. buf->next_element_to_fill++;
  2813. }
  2814. __qeth_fill_buffer(skb, buffer, large_send,
  2815. (int *)&buf->next_element_to_fill, offset);
  2816. if (!queue->do_pack) {
  2817. QETH_CARD_TEXT(queue->card, 6, "fillbfnp");
  2818. /* set state to PRIMED -> will be flushed */
  2819. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2820. flush_cnt = 1;
  2821. } else {
  2822. QETH_CARD_TEXT(queue->card, 6, "fillbfpa");
  2823. if (queue->card->options.performance_stats)
  2824. queue->card->perf_stats.skbs_sent_pack++;
  2825. if (buf->next_element_to_fill >=
  2826. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2827. /*
  2828. * packed buffer if full -> set state PRIMED
  2829. * -> will be flushed
  2830. */
  2831. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2832. flush_cnt = 1;
  2833. }
  2834. }
  2835. return flush_cnt;
  2836. }
  2837. int qeth_do_send_packet_fast(struct qeth_card *card,
  2838. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2839. struct qeth_hdr *hdr, int elements_needed,
  2840. int offset, int hd_len)
  2841. {
  2842. struct qeth_qdio_out_buffer *buffer;
  2843. int index;
  2844. /* spin until we get the queue ... */
  2845. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2846. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2847. /* ... now we've got the queue */
  2848. index = queue->next_buf_to_fill;
  2849. buffer = &queue->bufs[queue->next_buf_to_fill];
  2850. /*
  2851. * check if buffer is empty to make sure that we do not 'overtake'
  2852. * ourselves and try to fill a buffer that is already primed
  2853. */
  2854. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2855. goto out;
  2856. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2857. QDIO_MAX_BUFFERS_PER_Q;
  2858. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2859. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2860. qeth_flush_buffers(queue, index, 1);
  2861. return 0;
  2862. out:
  2863. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2864. return -EBUSY;
  2865. }
  2866. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2867. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2868. struct sk_buff *skb, struct qeth_hdr *hdr,
  2869. int elements_needed)
  2870. {
  2871. struct qeth_qdio_out_buffer *buffer;
  2872. int start_index;
  2873. int flush_count = 0;
  2874. int do_pack = 0;
  2875. int tmp;
  2876. int rc = 0;
  2877. /* spin until we get the queue ... */
  2878. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2879. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2880. start_index = queue->next_buf_to_fill;
  2881. buffer = &queue->bufs[queue->next_buf_to_fill];
  2882. /*
  2883. * check if buffer is empty to make sure that we do not 'overtake'
  2884. * ourselves and try to fill a buffer that is already primed
  2885. */
  2886. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2887. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2888. return -EBUSY;
  2889. }
  2890. /* check if we need to switch packing state of this queue */
  2891. qeth_switch_to_packing_if_needed(queue);
  2892. if (queue->do_pack) {
  2893. do_pack = 1;
  2894. /* does packet fit in current buffer? */
  2895. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2896. buffer->next_element_to_fill) < elements_needed) {
  2897. /* ... no -> set state PRIMED */
  2898. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2899. flush_count++;
  2900. queue->next_buf_to_fill =
  2901. (queue->next_buf_to_fill + 1) %
  2902. QDIO_MAX_BUFFERS_PER_Q;
  2903. buffer = &queue->bufs[queue->next_buf_to_fill];
  2904. /* we did a step forward, so check buffer state
  2905. * again */
  2906. if (atomic_read(&buffer->state) !=
  2907. QETH_QDIO_BUF_EMPTY) {
  2908. qeth_flush_buffers(queue, start_index,
  2909. flush_count);
  2910. atomic_set(&queue->state,
  2911. QETH_OUT_Q_UNLOCKED);
  2912. return -EBUSY;
  2913. }
  2914. }
  2915. }
  2916. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  2917. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2918. QDIO_MAX_BUFFERS_PER_Q;
  2919. flush_count += tmp;
  2920. if (flush_count)
  2921. qeth_flush_buffers(queue, start_index, flush_count);
  2922. else if (!atomic_read(&queue->set_pci_flags_count))
  2923. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2924. /*
  2925. * queue->state will go from LOCKED -> UNLOCKED or from
  2926. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2927. * (switch packing state or flush buffer to get another pci flag out).
  2928. * In that case we will enter this loop
  2929. */
  2930. while (atomic_dec_return(&queue->state)) {
  2931. flush_count = 0;
  2932. start_index = queue->next_buf_to_fill;
  2933. /* check if we can go back to non-packing state */
  2934. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2935. /*
  2936. * check if we need to flush a packing buffer to get a pci
  2937. * flag out on the queue
  2938. */
  2939. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2940. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2941. if (flush_count)
  2942. qeth_flush_buffers(queue, start_index, flush_count);
  2943. }
  2944. /* at this point the queue is UNLOCKED again */
  2945. if (queue->card->options.performance_stats && do_pack)
  2946. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2947. return rc;
  2948. }
  2949. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2950. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2951. struct qeth_reply *reply, unsigned long data)
  2952. {
  2953. struct qeth_ipa_cmd *cmd;
  2954. struct qeth_ipacmd_setadpparms *setparms;
  2955. QETH_CARD_TEXT(card, 4, "prmadpcb");
  2956. cmd = (struct qeth_ipa_cmd *) data;
  2957. setparms = &(cmd->data.setadapterparms);
  2958. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2959. if (cmd->hdr.return_code) {
  2960. QETH_CARD_TEXT_(card, 4, "prmrc%2.2x", cmd->hdr.return_code);
  2961. setparms->data.mode = SET_PROMISC_MODE_OFF;
  2962. }
  2963. card->info.promisc_mode = setparms->data.mode;
  2964. return 0;
  2965. }
  2966. void qeth_setadp_promisc_mode(struct qeth_card *card)
  2967. {
  2968. enum qeth_ipa_promisc_modes mode;
  2969. struct net_device *dev = card->dev;
  2970. struct qeth_cmd_buffer *iob;
  2971. struct qeth_ipa_cmd *cmd;
  2972. QETH_CARD_TEXT(card, 4, "setprom");
  2973. if (((dev->flags & IFF_PROMISC) &&
  2974. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  2975. (!(dev->flags & IFF_PROMISC) &&
  2976. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  2977. return;
  2978. mode = SET_PROMISC_MODE_OFF;
  2979. if (dev->flags & IFF_PROMISC)
  2980. mode = SET_PROMISC_MODE_ON;
  2981. QETH_CARD_TEXT_(card, 4, "mode:%x", mode);
  2982. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  2983. sizeof(struct qeth_ipacmd_setadpparms));
  2984. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  2985. cmd->data.setadapterparms.data.mode = mode;
  2986. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  2987. }
  2988. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  2989. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  2990. {
  2991. struct qeth_card *card;
  2992. char dbf_text[15];
  2993. card = dev->ml_priv;
  2994. QETH_CARD_TEXT(card, 4, "chgmtu");
  2995. sprintf(dbf_text, "%8x", new_mtu);
  2996. QETH_CARD_TEXT(card, 4, dbf_text);
  2997. if (new_mtu < 64)
  2998. return -EINVAL;
  2999. if (new_mtu > 65535)
  3000. return -EINVAL;
  3001. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3002. (!qeth_mtu_is_valid(card, new_mtu)))
  3003. return -EINVAL;
  3004. dev->mtu = new_mtu;
  3005. return 0;
  3006. }
  3007. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3008. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3009. {
  3010. struct qeth_card *card;
  3011. card = dev->ml_priv;
  3012. QETH_CARD_TEXT(card, 5, "getstat");
  3013. return &card->stats;
  3014. }
  3015. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3016. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3017. struct qeth_reply *reply, unsigned long data)
  3018. {
  3019. struct qeth_ipa_cmd *cmd;
  3020. QETH_CARD_TEXT(card, 4, "chgmaccb");
  3021. cmd = (struct qeth_ipa_cmd *) data;
  3022. if (!card->options.layer2 ||
  3023. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3024. memcpy(card->dev->dev_addr,
  3025. &cmd->data.setadapterparms.data.change_addr.addr,
  3026. OSA_ADDR_LEN);
  3027. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3028. }
  3029. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3030. return 0;
  3031. }
  3032. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3033. {
  3034. int rc;
  3035. struct qeth_cmd_buffer *iob;
  3036. struct qeth_ipa_cmd *cmd;
  3037. QETH_CARD_TEXT(card, 4, "chgmac");
  3038. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3039. sizeof(struct qeth_ipacmd_setadpparms));
  3040. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3041. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3042. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3043. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3044. card->dev->dev_addr, OSA_ADDR_LEN);
  3045. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3046. NULL);
  3047. return rc;
  3048. }
  3049. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3050. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3051. struct qeth_reply *reply, unsigned long data)
  3052. {
  3053. struct qeth_ipa_cmd *cmd;
  3054. struct qeth_set_access_ctrl *access_ctrl_req;
  3055. QETH_CARD_TEXT(card, 4, "setaccb");
  3056. cmd = (struct qeth_ipa_cmd *) data;
  3057. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3058. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3059. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3060. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3061. cmd->data.setadapterparms.hdr.return_code);
  3062. switch (cmd->data.setadapterparms.hdr.return_code) {
  3063. case SET_ACCESS_CTRL_RC_SUCCESS:
  3064. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3065. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3066. {
  3067. card->options.isolation = access_ctrl_req->subcmd_code;
  3068. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3069. dev_info(&card->gdev->dev,
  3070. "QDIO data connection isolation is deactivated\n");
  3071. } else {
  3072. dev_info(&card->gdev->dev,
  3073. "QDIO data connection isolation is activated\n");
  3074. }
  3075. QETH_DBF_MESSAGE(3, "OK:SET_ACCESS_CTRL(%s, %d)==%d\n",
  3076. card->gdev->dev.kobj.name,
  3077. access_ctrl_req->subcmd_code,
  3078. cmd->data.setadapterparms.hdr.return_code);
  3079. break;
  3080. }
  3081. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3082. {
  3083. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3084. card->gdev->dev.kobj.name,
  3085. access_ctrl_req->subcmd_code,
  3086. cmd->data.setadapterparms.hdr.return_code);
  3087. dev_err(&card->gdev->dev, "Adapter does not "
  3088. "support QDIO data connection isolation\n");
  3089. /* ensure isolation mode is "none" */
  3090. card->options.isolation = ISOLATION_MODE_NONE;
  3091. break;
  3092. }
  3093. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3094. {
  3095. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3096. card->gdev->dev.kobj.name,
  3097. access_ctrl_req->subcmd_code,
  3098. cmd->data.setadapterparms.hdr.return_code);
  3099. dev_err(&card->gdev->dev,
  3100. "Adapter is dedicated. "
  3101. "QDIO data connection isolation not supported\n");
  3102. /* ensure isolation mode is "none" */
  3103. card->options.isolation = ISOLATION_MODE_NONE;
  3104. break;
  3105. }
  3106. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3107. {
  3108. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3109. card->gdev->dev.kobj.name,
  3110. access_ctrl_req->subcmd_code,
  3111. cmd->data.setadapterparms.hdr.return_code);
  3112. dev_err(&card->gdev->dev,
  3113. "TSO does not permit QDIO data connection isolation\n");
  3114. /* ensure isolation mode is "none" */
  3115. card->options.isolation = ISOLATION_MODE_NONE;
  3116. break;
  3117. }
  3118. default:
  3119. {
  3120. /* this should never happen */
  3121. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d"
  3122. "==UNKNOWN\n",
  3123. card->gdev->dev.kobj.name,
  3124. access_ctrl_req->subcmd_code,
  3125. cmd->data.setadapterparms.hdr.return_code);
  3126. /* ensure isolation mode is "none" */
  3127. card->options.isolation = ISOLATION_MODE_NONE;
  3128. break;
  3129. }
  3130. }
  3131. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3132. return 0;
  3133. }
  3134. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3135. enum qeth_ipa_isolation_modes isolation)
  3136. {
  3137. int rc;
  3138. struct qeth_cmd_buffer *iob;
  3139. struct qeth_ipa_cmd *cmd;
  3140. struct qeth_set_access_ctrl *access_ctrl_req;
  3141. QETH_CARD_TEXT(card, 4, "setacctl");
  3142. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3143. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3144. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3145. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3146. sizeof(struct qeth_set_access_ctrl));
  3147. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3148. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3149. access_ctrl_req->subcmd_code = isolation;
  3150. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3151. NULL);
  3152. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3153. return rc;
  3154. }
  3155. int qeth_set_access_ctrl_online(struct qeth_card *card)
  3156. {
  3157. int rc = 0;
  3158. QETH_CARD_TEXT(card, 4, "setactlo");
  3159. if ((card->info.type == QETH_CARD_TYPE_OSD ||
  3160. card->info.type == QETH_CARD_TYPE_OSX) &&
  3161. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3162. rc = qeth_setadpparms_set_access_ctrl(card,
  3163. card->options.isolation);
  3164. if (rc) {
  3165. QETH_DBF_MESSAGE(3,
  3166. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed\n",
  3167. card->gdev->dev.kobj.name,
  3168. rc);
  3169. }
  3170. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3171. card->options.isolation = ISOLATION_MODE_NONE;
  3172. dev_err(&card->gdev->dev, "Adapter does not "
  3173. "support QDIO data connection isolation\n");
  3174. rc = -EOPNOTSUPP;
  3175. }
  3176. return rc;
  3177. }
  3178. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3179. void qeth_tx_timeout(struct net_device *dev)
  3180. {
  3181. struct qeth_card *card;
  3182. card = dev->ml_priv;
  3183. QETH_CARD_TEXT(card, 4, "txtimeo");
  3184. card->stats.tx_errors++;
  3185. qeth_schedule_recovery(card);
  3186. }
  3187. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3188. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3189. {
  3190. struct qeth_card *card = dev->ml_priv;
  3191. int rc = 0;
  3192. switch (regnum) {
  3193. case MII_BMCR: /* Basic mode control register */
  3194. rc = BMCR_FULLDPLX;
  3195. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3196. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3197. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3198. rc |= BMCR_SPEED100;
  3199. break;
  3200. case MII_BMSR: /* Basic mode status register */
  3201. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3202. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3203. BMSR_100BASE4;
  3204. break;
  3205. case MII_PHYSID1: /* PHYS ID 1 */
  3206. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3207. dev->dev_addr[2];
  3208. rc = (rc >> 5) & 0xFFFF;
  3209. break;
  3210. case MII_PHYSID2: /* PHYS ID 2 */
  3211. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3212. break;
  3213. case MII_ADVERTISE: /* Advertisement control reg */
  3214. rc = ADVERTISE_ALL;
  3215. break;
  3216. case MII_LPA: /* Link partner ability reg */
  3217. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3218. LPA_100BASE4 | LPA_LPACK;
  3219. break;
  3220. case MII_EXPANSION: /* Expansion register */
  3221. break;
  3222. case MII_DCOUNTER: /* disconnect counter */
  3223. break;
  3224. case MII_FCSCOUNTER: /* false carrier counter */
  3225. break;
  3226. case MII_NWAYTEST: /* N-way auto-neg test register */
  3227. break;
  3228. case MII_RERRCOUNTER: /* rx error counter */
  3229. rc = card->stats.rx_errors;
  3230. break;
  3231. case MII_SREVISION: /* silicon revision */
  3232. break;
  3233. case MII_RESV1: /* reserved 1 */
  3234. break;
  3235. case MII_LBRERROR: /* loopback, rx, bypass error */
  3236. break;
  3237. case MII_PHYADDR: /* physical address */
  3238. break;
  3239. case MII_RESV2: /* reserved 2 */
  3240. break;
  3241. case MII_TPISTATUS: /* TPI status for 10mbps */
  3242. break;
  3243. case MII_NCONFIG: /* network interface config */
  3244. break;
  3245. default:
  3246. break;
  3247. }
  3248. return rc;
  3249. }
  3250. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3251. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3252. struct qeth_cmd_buffer *iob, int len,
  3253. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3254. unsigned long),
  3255. void *reply_param)
  3256. {
  3257. u16 s1, s2;
  3258. QETH_CARD_TEXT(card, 4, "sendsnmp");
  3259. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3260. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3261. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3262. /* adjust PDU length fields in IPA_PDU_HEADER */
  3263. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3264. s2 = (u32) len;
  3265. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3266. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3267. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3268. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3269. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3270. reply_cb, reply_param);
  3271. }
  3272. static int qeth_snmp_command_cb(struct qeth_card *card,
  3273. struct qeth_reply *reply, unsigned long sdata)
  3274. {
  3275. struct qeth_ipa_cmd *cmd;
  3276. struct qeth_arp_query_info *qinfo;
  3277. struct qeth_snmp_cmd *snmp;
  3278. unsigned char *data;
  3279. __u16 data_len;
  3280. QETH_CARD_TEXT(card, 3, "snpcmdcb");
  3281. cmd = (struct qeth_ipa_cmd *) sdata;
  3282. data = (unsigned char *)((char *)cmd - reply->offset);
  3283. qinfo = (struct qeth_arp_query_info *) reply->param;
  3284. snmp = &cmd->data.setadapterparms.data.snmp;
  3285. if (cmd->hdr.return_code) {
  3286. QETH_CARD_TEXT_(card, 4, "scer1%i", cmd->hdr.return_code);
  3287. return 0;
  3288. }
  3289. if (cmd->data.setadapterparms.hdr.return_code) {
  3290. cmd->hdr.return_code =
  3291. cmd->data.setadapterparms.hdr.return_code;
  3292. QETH_CARD_TEXT_(card, 4, "scer2%i", cmd->hdr.return_code);
  3293. return 0;
  3294. }
  3295. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3296. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3297. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3298. else
  3299. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3300. /* check if there is enough room in userspace */
  3301. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3302. QETH_CARD_TEXT_(card, 4, "scer3%i", -ENOMEM);
  3303. cmd->hdr.return_code = -ENOMEM;
  3304. return 0;
  3305. }
  3306. QETH_CARD_TEXT_(card, 4, "snore%i",
  3307. cmd->data.setadapterparms.hdr.used_total);
  3308. QETH_CARD_TEXT_(card, 4, "sseqn%i",
  3309. cmd->data.setadapterparms.hdr.seq_no);
  3310. /*copy entries to user buffer*/
  3311. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3312. memcpy(qinfo->udata + qinfo->udata_offset,
  3313. (char *)snmp,
  3314. data_len + offsetof(struct qeth_snmp_cmd, data));
  3315. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3316. } else {
  3317. memcpy(qinfo->udata + qinfo->udata_offset,
  3318. (char *)&snmp->request, data_len);
  3319. }
  3320. qinfo->udata_offset += data_len;
  3321. /* check if all replies received ... */
  3322. QETH_CARD_TEXT_(card, 4, "srtot%i",
  3323. cmd->data.setadapterparms.hdr.used_total);
  3324. QETH_CARD_TEXT_(card, 4, "srseq%i",
  3325. cmd->data.setadapterparms.hdr.seq_no);
  3326. if (cmd->data.setadapterparms.hdr.seq_no <
  3327. cmd->data.setadapterparms.hdr.used_total)
  3328. return 1;
  3329. return 0;
  3330. }
  3331. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3332. {
  3333. struct qeth_cmd_buffer *iob;
  3334. struct qeth_ipa_cmd *cmd;
  3335. struct qeth_snmp_ureq *ureq;
  3336. int req_len;
  3337. struct qeth_arp_query_info qinfo = {0, };
  3338. int rc = 0;
  3339. QETH_CARD_TEXT(card, 3, "snmpcmd");
  3340. if (card->info.guestlan)
  3341. return -EOPNOTSUPP;
  3342. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3343. (!card->options.layer2)) {
  3344. return -EOPNOTSUPP;
  3345. }
  3346. /* skip 4 bytes (data_len struct member) to get req_len */
  3347. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3348. return -EFAULT;
  3349. ureq = memdup_user(udata, req_len + sizeof(struct qeth_snmp_ureq_hdr));
  3350. if (IS_ERR(ureq)) {
  3351. QETH_CARD_TEXT(card, 2, "snmpnome");
  3352. return PTR_ERR(ureq);
  3353. }
  3354. qinfo.udata_len = ureq->hdr.data_len;
  3355. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3356. if (!qinfo.udata) {
  3357. kfree(ureq);
  3358. return -ENOMEM;
  3359. }
  3360. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3361. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3362. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3363. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3364. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3365. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3366. qeth_snmp_command_cb, (void *)&qinfo);
  3367. if (rc)
  3368. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3369. QETH_CARD_IFNAME(card), rc);
  3370. else {
  3371. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3372. rc = -EFAULT;
  3373. }
  3374. kfree(ureq);
  3375. kfree(qinfo.udata);
  3376. return rc;
  3377. }
  3378. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3379. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3380. {
  3381. switch (card->info.type) {
  3382. case QETH_CARD_TYPE_IQD:
  3383. return 2;
  3384. default:
  3385. return 0;
  3386. }
  3387. }
  3388. static int qeth_qdio_establish(struct qeth_card *card)
  3389. {
  3390. struct qdio_initialize init_data;
  3391. char *qib_param_field;
  3392. struct qdio_buffer **in_sbal_ptrs;
  3393. struct qdio_buffer **out_sbal_ptrs;
  3394. int i, j, k;
  3395. int rc = 0;
  3396. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3397. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3398. GFP_KERNEL);
  3399. if (!qib_param_field)
  3400. return -ENOMEM;
  3401. qeth_create_qib_param_field(card, qib_param_field);
  3402. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3403. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3404. GFP_KERNEL);
  3405. if (!in_sbal_ptrs) {
  3406. kfree(qib_param_field);
  3407. return -ENOMEM;
  3408. }
  3409. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3410. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3411. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3412. out_sbal_ptrs =
  3413. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3414. sizeof(void *), GFP_KERNEL);
  3415. if (!out_sbal_ptrs) {
  3416. kfree(in_sbal_ptrs);
  3417. kfree(qib_param_field);
  3418. return -ENOMEM;
  3419. }
  3420. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3421. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3422. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3423. card->qdio.out_qs[i]->bufs[j].buffer);
  3424. }
  3425. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3426. init_data.cdev = CARD_DDEV(card);
  3427. init_data.q_format = qeth_get_qdio_q_format(card);
  3428. init_data.qib_param_field_format = 0;
  3429. init_data.qib_param_field = qib_param_field;
  3430. init_data.no_input_qs = 1;
  3431. init_data.no_output_qs = card->qdio.no_out_queues;
  3432. init_data.input_handler = card->discipline.input_handler;
  3433. init_data.output_handler = card->discipline.output_handler;
  3434. init_data.queue_start_poll = card->discipline.start_poll;
  3435. init_data.int_parm = (unsigned long) card;
  3436. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3437. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3438. init_data.scan_threshold =
  3439. (card->info.type == QETH_CARD_TYPE_IQD) ? 8 : 32;
  3440. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3441. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3442. rc = qdio_allocate(&init_data);
  3443. if (rc) {
  3444. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3445. goto out;
  3446. }
  3447. rc = qdio_establish(&init_data);
  3448. if (rc) {
  3449. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3450. qdio_free(CARD_DDEV(card));
  3451. }
  3452. }
  3453. out:
  3454. kfree(out_sbal_ptrs);
  3455. kfree(in_sbal_ptrs);
  3456. kfree(qib_param_field);
  3457. return rc;
  3458. }
  3459. static void qeth_core_free_card(struct qeth_card *card)
  3460. {
  3461. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3462. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3463. qeth_clean_channel(&card->read);
  3464. qeth_clean_channel(&card->write);
  3465. if (card->dev)
  3466. free_netdev(card->dev);
  3467. kfree(card->ip_tbd_list);
  3468. qeth_free_qdio_buffers(card);
  3469. unregister_service_level(&card->qeth_service_level);
  3470. kfree(card);
  3471. }
  3472. static struct ccw_device_id qeth_ids[] = {
  3473. {CCW_DEVICE_DEVTYPE(0x1731, 0x01, 0x1732, 0x01),
  3474. .driver_info = QETH_CARD_TYPE_OSD},
  3475. {CCW_DEVICE_DEVTYPE(0x1731, 0x05, 0x1732, 0x05),
  3476. .driver_info = QETH_CARD_TYPE_IQD},
  3477. {CCW_DEVICE_DEVTYPE(0x1731, 0x06, 0x1732, 0x06),
  3478. .driver_info = QETH_CARD_TYPE_OSN},
  3479. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x03),
  3480. .driver_info = QETH_CARD_TYPE_OSM},
  3481. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x02),
  3482. .driver_info = QETH_CARD_TYPE_OSX},
  3483. {},
  3484. };
  3485. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3486. static struct ccw_driver qeth_ccw_driver = {
  3487. .name = "qeth",
  3488. .ids = qeth_ids,
  3489. .probe = ccwgroup_probe_ccwdev,
  3490. .remove = ccwgroup_remove_ccwdev,
  3491. };
  3492. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3493. unsigned long driver_id)
  3494. {
  3495. return ccwgroup_create_from_string(root_dev, driver_id,
  3496. &qeth_ccw_driver, 3, buf);
  3497. }
  3498. int qeth_core_hardsetup_card(struct qeth_card *card)
  3499. {
  3500. int retries = 0;
  3501. int rc;
  3502. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3503. atomic_set(&card->force_alloc_skb, 0);
  3504. retry:
  3505. if (retries)
  3506. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  3507. dev_name(&card->gdev->dev));
  3508. ccw_device_set_offline(CARD_DDEV(card));
  3509. ccw_device_set_offline(CARD_WDEV(card));
  3510. ccw_device_set_offline(CARD_RDEV(card));
  3511. rc = ccw_device_set_online(CARD_RDEV(card));
  3512. if (rc)
  3513. goto retriable;
  3514. rc = ccw_device_set_online(CARD_WDEV(card));
  3515. if (rc)
  3516. goto retriable;
  3517. rc = ccw_device_set_online(CARD_DDEV(card));
  3518. if (rc)
  3519. goto retriable;
  3520. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3521. retriable:
  3522. if (rc == -ERESTARTSYS) {
  3523. QETH_DBF_TEXT(SETUP, 2, "break1");
  3524. return rc;
  3525. } else if (rc) {
  3526. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3527. if (++retries > 3)
  3528. goto out;
  3529. else
  3530. goto retry;
  3531. }
  3532. qeth_init_tokens(card);
  3533. qeth_init_func_level(card);
  3534. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3535. if (rc == -ERESTARTSYS) {
  3536. QETH_DBF_TEXT(SETUP, 2, "break2");
  3537. return rc;
  3538. } else if (rc) {
  3539. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3540. if (--retries < 0)
  3541. goto out;
  3542. else
  3543. goto retry;
  3544. }
  3545. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3546. if (rc == -ERESTARTSYS) {
  3547. QETH_DBF_TEXT(SETUP, 2, "break3");
  3548. return rc;
  3549. } else if (rc) {
  3550. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3551. if (--retries < 0)
  3552. goto out;
  3553. else
  3554. goto retry;
  3555. }
  3556. card->read_or_write_problem = 0;
  3557. rc = qeth_mpc_initialize(card);
  3558. if (rc) {
  3559. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3560. goto out;
  3561. }
  3562. return 0;
  3563. out:
  3564. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  3565. "an error on the device\n");
  3566. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  3567. dev_name(&card->gdev->dev), rc);
  3568. return rc;
  3569. }
  3570. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3571. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3572. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3573. {
  3574. struct page *page = virt_to_page(element->addr);
  3575. if (*pskb == NULL) {
  3576. /* the upper protocol layers assume that there is data in the
  3577. * skb itself. Copy a small amount (64 bytes) to make them
  3578. * happy. */
  3579. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3580. if (!(*pskb))
  3581. return -ENOMEM;
  3582. skb_reserve(*pskb, ETH_HLEN);
  3583. if (data_len <= 64) {
  3584. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3585. data_len);
  3586. } else {
  3587. get_page(page);
  3588. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3589. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3590. data_len - 64);
  3591. (*pskb)->data_len += data_len - 64;
  3592. (*pskb)->len += data_len - 64;
  3593. (*pskb)->truesize += data_len - 64;
  3594. (*pfrag)++;
  3595. }
  3596. } else {
  3597. get_page(page);
  3598. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3599. (*pskb)->data_len += data_len;
  3600. (*pskb)->len += data_len;
  3601. (*pskb)->truesize += data_len;
  3602. (*pfrag)++;
  3603. }
  3604. return 0;
  3605. }
  3606. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3607. struct qdio_buffer *buffer,
  3608. struct qdio_buffer_element **__element, int *__offset,
  3609. struct qeth_hdr **hdr)
  3610. {
  3611. struct qdio_buffer_element *element = *__element;
  3612. int offset = *__offset;
  3613. struct sk_buff *skb = NULL;
  3614. int skb_len = 0;
  3615. void *data_ptr;
  3616. int data_len;
  3617. int headroom = 0;
  3618. int use_rx_sg = 0;
  3619. int frag = 0;
  3620. /* qeth_hdr must not cross element boundaries */
  3621. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3622. if (qeth_is_last_sbale(element))
  3623. return NULL;
  3624. element++;
  3625. offset = 0;
  3626. if (element->length < sizeof(struct qeth_hdr))
  3627. return NULL;
  3628. }
  3629. *hdr = element->addr + offset;
  3630. offset += sizeof(struct qeth_hdr);
  3631. switch ((*hdr)->hdr.l2.id) {
  3632. case QETH_HEADER_TYPE_LAYER2:
  3633. skb_len = (*hdr)->hdr.l2.pkt_length;
  3634. break;
  3635. case QETH_HEADER_TYPE_LAYER3:
  3636. skb_len = (*hdr)->hdr.l3.length;
  3637. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3638. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3639. headroom = TR_HLEN;
  3640. else
  3641. headroom = ETH_HLEN;
  3642. break;
  3643. case QETH_HEADER_TYPE_OSN:
  3644. skb_len = (*hdr)->hdr.osn.pdu_length;
  3645. headroom = sizeof(struct qeth_hdr);
  3646. break;
  3647. default:
  3648. break;
  3649. }
  3650. if (!skb_len)
  3651. return NULL;
  3652. if ((skb_len >= card->options.rx_sg_cb) &&
  3653. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3654. (!atomic_read(&card->force_alloc_skb))) {
  3655. use_rx_sg = 1;
  3656. } else {
  3657. skb = dev_alloc_skb(skb_len + headroom);
  3658. if (!skb)
  3659. goto no_mem;
  3660. if (headroom)
  3661. skb_reserve(skb, headroom);
  3662. }
  3663. data_ptr = element->addr + offset;
  3664. while (skb_len) {
  3665. data_len = min(skb_len, (int)(element->length - offset));
  3666. if (data_len) {
  3667. if (use_rx_sg) {
  3668. if (qeth_create_skb_frag(element, &skb, offset,
  3669. &frag, data_len))
  3670. goto no_mem;
  3671. } else {
  3672. memcpy(skb_put(skb, data_len), data_ptr,
  3673. data_len);
  3674. }
  3675. }
  3676. skb_len -= data_len;
  3677. if (skb_len) {
  3678. if (qeth_is_last_sbale(element)) {
  3679. QETH_CARD_TEXT(card, 4, "unexeob");
  3680. QETH_CARD_HEX(card, 2, buffer, sizeof(void *));
  3681. dev_kfree_skb_any(skb);
  3682. card->stats.rx_errors++;
  3683. return NULL;
  3684. }
  3685. element++;
  3686. offset = 0;
  3687. data_ptr = element->addr;
  3688. } else {
  3689. offset += data_len;
  3690. }
  3691. }
  3692. *__element = element;
  3693. *__offset = offset;
  3694. if (use_rx_sg && card->options.performance_stats) {
  3695. card->perf_stats.sg_skbs_rx++;
  3696. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3697. }
  3698. return skb;
  3699. no_mem:
  3700. if (net_ratelimit()) {
  3701. QETH_CARD_TEXT(card, 2, "noskbmem");
  3702. }
  3703. card->stats.rx_dropped++;
  3704. return NULL;
  3705. }
  3706. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3707. static void qeth_unregister_dbf_views(void)
  3708. {
  3709. int x;
  3710. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3711. debug_unregister(qeth_dbf[x].id);
  3712. qeth_dbf[x].id = NULL;
  3713. }
  3714. }
  3715. void qeth_dbf_longtext(debug_info_t *id, int level, char *fmt, ...)
  3716. {
  3717. char dbf_txt_buf[32];
  3718. va_list args;
  3719. if (level > id->level)
  3720. return;
  3721. va_start(args, fmt);
  3722. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3723. va_end(args);
  3724. debug_text_event(id, level, dbf_txt_buf);
  3725. }
  3726. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3727. static int qeth_register_dbf_views(void)
  3728. {
  3729. int ret;
  3730. int x;
  3731. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3732. /* register the areas */
  3733. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3734. qeth_dbf[x].pages,
  3735. qeth_dbf[x].areas,
  3736. qeth_dbf[x].len);
  3737. if (qeth_dbf[x].id == NULL) {
  3738. qeth_unregister_dbf_views();
  3739. return -ENOMEM;
  3740. }
  3741. /* register a view */
  3742. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3743. if (ret) {
  3744. qeth_unregister_dbf_views();
  3745. return ret;
  3746. }
  3747. /* set a passing level */
  3748. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3749. }
  3750. return 0;
  3751. }
  3752. int qeth_core_load_discipline(struct qeth_card *card,
  3753. enum qeth_discipline_id discipline)
  3754. {
  3755. int rc = 0;
  3756. switch (discipline) {
  3757. case QETH_DISCIPLINE_LAYER3:
  3758. card->discipline.ccwgdriver = try_then_request_module(
  3759. symbol_get(qeth_l3_ccwgroup_driver),
  3760. "qeth_l3");
  3761. break;
  3762. case QETH_DISCIPLINE_LAYER2:
  3763. card->discipline.ccwgdriver = try_then_request_module(
  3764. symbol_get(qeth_l2_ccwgroup_driver),
  3765. "qeth_l2");
  3766. break;
  3767. }
  3768. if (!card->discipline.ccwgdriver) {
  3769. dev_err(&card->gdev->dev, "There is no kernel module to "
  3770. "support discipline %d\n", discipline);
  3771. rc = -EINVAL;
  3772. }
  3773. return rc;
  3774. }
  3775. void qeth_core_free_discipline(struct qeth_card *card)
  3776. {
  3777. if (card->options.layer2)
  3778. symbol_put(qeth_l2_ccwgroup_driver);
  3779. else
  3780. symbol_put(qeth_l3_ccwgroup_driver);
  3781. card->discipline.ccwgdriver = NULL;
  3782. }
  3783. static void qeth_determine_capabilities(struct qeth_card *card)
  3784. {
  3785. int rc;
  3786. int length;
  3787. char *prcd;
  3788. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  3789. rc = ccw_device_set_online(CARD_DDEV(card));
  3790. if (rc) {
  3791. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3792. goto out;
  3793. }
  3794. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  3795. if (rc) {
  3796. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  3797. dev_name(&card->gdev->dev), rc);
  3798. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3799. goto out_offline;
  3800. }
  3801. qeth_configure_unitaddr(card, prcd);
  3802. qeth_configure_blkt_default(card, prcd);
  3803. kfree(prcd);
  3804. rc = qdio_get_ssqd_desc(CARD_DDEV(card), &card->ssqd);
  3805. if (rc)
  3806. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  3807. out_offline:
  3808. ccw_device_set_offline(CARD_DDEV(card));
  3809. out:
  3810. return;
  3811. }
  3812. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3813. {
  3814. struct qeth_card *card;
  3815. struct device *dev;
  3816. int rc;
  3817. unsigned long flags;
  3818. char dbf_name[20];
  3819. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3820. dev = &gdev->dev;
  3821. if (!get_device(dev))
  3822. return -ENODEV;
  3823. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  3824. card = qeth_alloc_card();
  3825. if (!card) {
  3826. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3827. rc = -ENOMEM;
  3828. goto err_dev;
  3829. }
  3830. snprintf(dbf_name, sizeof(dbf_name), "qeth_card_%s",
  3831. dev_name(&gdev->dev));
  3832. card->debug = debug_register(dbf_name, 2, 1, 8);
  3833. if (!card->debug) {
  3834. QETH_DBF_TEXT_(SETUP, 2, "%s", "qcdbf");
  3835. rc = -ENOMEM;
  3836. goto err_card;
  3837. }
  3838. debug_register_view(card->debug, &debug_hex_ascii_view);
  3839. card->read.ccwdev = gdev->cdev[0];
  3840. card->write.ccwdev = gdev->cdev[1];
  3841. card->data.ccwdev = gdev->cdev[2];
  3842. dev_set_drvdata(&gdev->dev, card);
  3843. card->gdev = gdev;
  3844. gdev->cdev[0]->handler = qeth_irq;
  3845. gdev->cdev[1]->handler = qeth_irq;
  3846. gdev->cdev[2]->handler = qeth_irq;
  3847. rc = qeth_determine_card_type(card);
  3848. if (rc) {
  3849. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3850. goto err_dbf;
  3851. }
  3852. rc = qeth_setup_card(card);
  3853. if (rc) {
  3854. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3855. goto err_dbf;
  3856. }
  3857. if (card->info.type == QETH_CARD_TYPE_OSN)
  3858. rc = qeth_core_create_osn_attributes(dev);
  3859. else
  3860. rc = qeth_core_create_device_attributes(dev);
  3861. if (rc)
  3862. goto err_dbf;
  3863. switch (card->info.type) {
  3864. case QETH_CARD_TYPE_OSN:
  3865. case QETH_CARD_TYPE_OSM:
  3866. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3867. if (rc)
  3868. goto err_attr;
  3869. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3870. if (rc)
  3871. goto err_disc;
  3872. case QETH_CARD_TYPE_OSD:
  3873. case QETH_CARD_TYPE_OSX:
  3874. default:
  3875. break;
  3876. }
  3877. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3878. list_add_tail(&card->list, &qeth_core_card_list.list);
  3879. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3880. qeth_determine_capabilities(card);
  3881. return 0;
  3882. err_disc:
  3883. qeth_core_free_discipline(card);
  3884. err_attr:
  3885. if (card->info.type == QETH_CARD_TYPE_OSN)
  3886. qeth_core_remove_osn_attributes(dev);
  3887. else
  3888. qeth_core_remove_device_attributes(dev);
  3889. err_dbf:
  3890. debug_unregister(card->debug);
  3891. err_card:
  3892. qeth_core_free_card(card);
  3893. err_dev:
  3894. put_device(dev);
  3895. return rc;
  3896. }
  3897. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3898. {
  3899. unsigned long flags;
  3900. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3901. QETH_DBF_TEXT(SETUP, 2, "removedv");
  3902. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3903. qeth_core_remove_osn_attributes(&gdev->dev);
  3904. } else {
  3905. qeth_core_remove_device_attributes(&gdev->dev);
  3906. }
  3907. if (card->discipline.ccwgdriver) {
  3908. card->discipline.ccwgdriver->remove(gdev);
  3909. qeth_core_free_discipline(card);
  3910. }
  3911. debug_unregister(card->debug);
  3912. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3913. list_del(&card->list);
  3914. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3915. qeth_core_free_card(card);
  3916. dev_set_drvdata(&gdev->dev, NULL);
  3917. put_device(&gdev->dev);
  3918. return;
  3919. }
  3920. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3921. {
  3922. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3923. int rc = 0;
  3924. int def_discipline;
  3925. if (!card->discipline.ccwgdriver) {
  3926. if (card->info.type == QETH_CARD_TYPE_IQD)
  3927. def_discipline = QETH_DISCIPLINE_LAYER3;
  3928. else
  3929. def_discipline = QETH_DISCIPLINE_LAYER2;
  3930. rc = qeth_core_load_discipline(card, def_discipline);
  3931. if (rc)
  3932. goto err;
  3933. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3934. if (rc)
  3935. goto err;
  3936. }
  3937. rc = card->discipline.ccwgdriver->set_online(gdev);
  3938. err:
  3939. return rc;
  3940. }
  3941. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3942. {
  3943. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3944. return card->discipline.ccwgdriver->set_offline(gdev);
  3945. }
  3946. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3947. {
  3948. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3949. if (card->discipline.ccwgdriver &&
  3950. card->discipline.ccwgdriver->shutdown)
  3951. card->discipline.ccwgdriver->shutdown(gdev);
  3952. }
  3953. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  3954. {
  3955. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3956. if (card->discipline.ccwgdriver &&
  3957. card->discipline.ccwgdriver->prepare)
  3958. return card->discipline.ccwgdriver->prepare(gdev);
  3959. return 0;
  3960. }
  3961. static void qeth_core_complete(struct ccwgroup_device *gdev)
  3962. {
  3963. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3964. if (card->discipline.ccwgdriver &&
  3965. card->discipline.ccwgdriver->complete)
  3966. card->discipline.ccwgdriver->complete(gdev);
  3967. }
  3968. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  3969. {
  3970. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3971. if (card->discipline.ccwgdriver &&
  3972. card->discipline.ccwgdriver->freeze)
  3973. return card->discipline.ccwgdriver->freeze(gdev);
  3974. return 0;
  3975. }
  3976. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  3977. {
  3978. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3979. if (card->discipline.ccwgdriver &&
  3980. card->discipline.ccwgdriver->thaw)
  3981. return card->discipline.ccwgdriver->thaw(gdev);
  3982. return 0;
  3983. }
  3984. static int qeth_core_restore(struct ccwgroup_device *gdev)
  3985. {
  3986. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3987. if (card->discipline.ccwgdriver &&
  3988. card->discipline.ccwgdriver->restore)
  3989. return card->discipline.ccwgdriver->restore(gdev);
  3990. return 0;
  3991. }
  3992. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  3993. .owner = THIS_MODULE,
  3994. .name = "qeth",
  3995. .driver_id = 0xD8C5E3C8,
  3996. .probe = qeth_core_probe_device,
  3997. .remove = qeth_core_remove_device,
  3998. .set_online = qeth_core_set_online,
  3999. .set_offline = qeth_core_set_offline,
  4000. .shutdown = qeth_core_shutdown,
  4001. .prepare = qeth_core_prepare,
  4002. .complete = qeth_core_complete,
  4003. .freeze = qeth_core_freeze,
  4004. .thaw = qeth_core_thaw,
  4005. .restore = qeth_core_restore,
  4006. };
  4007. static ssize_t
  4008. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  4009. size_t count)
  4010. {
  4011. int err;
  4012. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  4013. qeth_core_ccwgroup_driver.driver_id);
  4014. if (err)
  4015. return err;
  4016. else
  4017. return count;
  4018. }
  4019. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  4020. static struct {
  4021. const char str[ETH_GSTRING_LEN];
  4022. } qeth_ethtool_stats_keys[] = {
  4023. /* 0 */{"rx skbs"},
  4024. {"rx buffers"},
  4025. {"tx skbs"},
  4026. {"tx buffers"},
  4027. {"tx skbs no packing"},
  4028. {"tx buffers no packing"},
  4029. {"tx skbs packing"},
  4030. {"tx buffers packing"},
  4031. {"tx sg skbs"},
  4032. {"tx sg frags"},
  4033. /* 10 */{"rx sg skbs"},
  4034. {"rx sg frags"},
  4035. {"rx sg page allocs"},
  4036. {"tx large kbytes"},
  4037. {"tx large count"},
  4038. {"tx pk state ch n->p"},
  4039. {"tx pk state ch p->n"},
  4040. {"tx pk watermark low"},
  4041. {"tx pk watermark high"},
  4042. {"queue 0 buffer usage"},
  4043. /* 20 */{"queue 1 buffer usage"},
  4044. {"queue 2 buffer usage"},
  4045. {"queue 3 buffer usage"},
  4046. {"rx poll time"},
  4047. {"rx poll count"},
  4048. {"rx do_QDIO time"},
  4049. {"rx do_QDIO count"},
  4050. {"tx handler time"},
  4051. {"tx handler count"},
  4052. {"tx time"},
  4053. /* 30 */{"tx count"},
  4054. {"tx do_QDIO time"},
  4055. {"tx do_QDIO count"},
  4056. {"tx csum"},
  4057. {"tx lin"},
  4058. };
  4059. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  4060. {
  4061. switch (stringset) {
  4062. case ETH_SS_STATS:
  4063. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  4064. default:
  4065. return -EINVAL;
  4066. }
  4067. }
  4068. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  4069. void qeth_core_get_ethtool_stats(struct net_device *dev,
  4070. struct ethtool_stats *stats, u64 *data)
  4071. {
  4072. struct qeth_card *card = dev->ml_priv;
  4073. data[0] = card->stats.rx_packets -
  4074. card->perf_stats.initial_rx_packets;
  4075. data[1] = card->perf_stats.bufs_rec;
  4076. data[2] = card->stats.tx_packets -
  4077. card->perf_stats.initial_tx_packets;
  4078. data[3] = card->perf_stats.bufs_sent;
  4079. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4080. - card->perf_stats.skbs_sent_pack;
  4081. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4082. data[6] = card->perf_stats.skbs_sent_pack;
  4083. data[7] = card->perf_stats.bufs_sent_pack;
  4084. data[8] = card->perf_stats.sg_skbs_sent;
  4085. data[9] = card->perf_stats.sg_frags_sent;
  4086. data[10] = card->perf_stats.sg_skbs_rx;
  4087. data[11] = card->perf_stats.sg_frags_rx;
  4088. data[12] = card->perf_stats.sg_alloc_page_rx;
  4089. data[13] = (card->perf_stats.large_send_bytes >> 10);
  4090. data[14] = card->perf_stats.large_send_cnt;
  4091. data[15] = card->perf_stats.sc_dp_p;
  4092. data[16] = card->perf_stats.sc_p_dp;
  4093. data[17] = QETH_LOW_WATERMARK_PACK;
  4094. data[18] = QETH_HIGH_WATERMARK_PACK;
  4095. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  4096. data[20] = (card->qdio.no_out_queues > 1) ?
  4097. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4098. data[21] = (card->qdio.no_out_queues > 2) ?
  4099. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4100. data[22] = (card->qdio.no_out_queues > 3) ?
  4101. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4102. data[23] = card->perf_stats.inbound_time;
  4103. data[24] = card->perf_stats.inbound_cnt;
  4104. data[25] = card->perf_stats.inbound_do_qdio_time;
  4105. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4106. data[27] = card->perf_stats.outbound_handler_time;
  4107. data[28] = card->perf_stats.outbound_handler_cnt;
  4108. data[29] = card->perf_stats.outbound_time;
  4109. data[30] = card->perf_stats.outbound_cnt;
  4110. data[31] = card->perf_stats.outbound_do_qdio_time;
  4111. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4112. data[33] = card->perf_stats.tx_csum;
  4113. data[34] = card->perf_stats.tx_lin;
  4114. }
  4115. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4116. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4117. {
  4118. switch (stringset) {
  4119. case ETH_SS_STATS:
  4120. memcpy(data, &qeth_ethtool_stats_keys,
  4121. sizeof(qeth_ethtool_stats_keys));
  4122. break;
  4123. default:
  4124. WARN_ON(1);
  4125. break;
  4126. }
  4127. }
  4128. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4129. void qeth_core_get_drvinfo(struct net_device *dev,
  4130. struct ethtool_drvinfo *info)
  4131. {
  4132. struct qeth_card *card = dev->ml_priv;
  4133. if (card->options.layer2)
  4134. strcpy(info->driver, "qeth_l2");
  4135. else
  4136. strcpy(info->driver, "qeth_l3");
  4137. strcpy(info->version, "1.0");
  4138. strcpy(info->fw_version, card->info.mcl_level);
  4139. sprintf(info->bus_info, "%s/%s/%s",
  4140. CARD_RDEV_ID(card),
  4141. CARD_WDEV_ID(card),
  4142. CARD_DDEV_ID(card));
  4143. }
  4144. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4145. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  4146. struct ethtool_cmd *ecmd)
  4147. {
  4148. struct qeth_card *card = netdev->ml_priv;
  4149. enum qeth_link_types link_type;
  4150. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  4151. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  4152. else
  4153. link_type = card->info.link_type;
  4154. ecmd->transceiver = XCVR_INTERNAL;
  4155. ecmd->supported = SUPPORTED_Autoneg;
  4156. ecmd->advertising = ADVERTISED_Autoneg;
  4157. ecmd->duplex = DUPLEX_FULL;
  4158. ecmd->autoneg = AUTONEG_ENABLE;
  4159. switch (link_type) {
  4160. case QETH_LINK_TYPE_FAST_ETH:
  4161. case QETH_LINK_TYPE_LANE_ETH100:
  4162. ecmd->supported |= SUPPORTED_10baseT_Half |
  4163. SUPPORTED_10baseT_Full |
  4164. SUPPORTED_100baseT_Half |
  4165. SUPPORTED_100baseT_Full |
  4166. SUPPORTED_TP;
  4167. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4168. ADVERTISED_10baseT_Full |
  4169. ADVERTISED_100baseT_Half |
  4170. ADVERTISED_100baseT_Full |
  4171. ADVERTISED_TP;
  4172. ecmd->speed = SPEED_100;
  4173. ecmd->port = PORT_TP;
  4174. break;
  4175. case QETH_LINK_TYPE_GBIT_ETH:
  4176. case QETH_LINK_TYPE_LANE_ETH1000:
  4177. ecmd->supported |= SUPPORTED_10baseT_Half |
  4178. SUPPORTED_10baseT_Full |
  4179. SUPPORTED_100baseT_Half |
  4180. SUPPORTED_100baseT_Full |
  4181. SUPPORTED_1000baseT_Half |
  4182. SUPPORTED_1000baseT_Full |
  4183. SUPPORTED_FIBRE;
  4184. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4185. ADVERTISED_10baseT_Full |
  4186. ADVERTISED_100baseT_Half |
  4187. ADVERTISED_100baseT_Full |
  4188. ADVERTISED_1000baseT_Half |
  4189. ADVERTISED_1000baseT_Full |
  4190. ADVERTISED_FIBRE;
  4191. ecmd->speed = SPEED_1000;
  4192. ecmd->port = PORT_FIBRE;
  4193. break;
  4194. case QETH_LINK_TYPE_10GBIT_ETH:
  4195. ecmd->supported |= SUPPORTED_10baseT_Half |
  4196. SUPPORTED_10baseT_Full |
  4197. SUPPORTED_100baseT_Half |
  4198. SUPPORTED_100baseT_Full |
  4199. SUPPORTED_1000baseT_Half |
  4200. SUPPORTED_1000baseT_Full |
  4201. SUPPORTED_10000baseT_Full |
  4202. SUPPORTED_FIBRE;
  4203. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4204. ADVERTISED_10baseT_Full |
  4205. ADVERTISED_100baseT_Half |
  4206. ADVERTISED_100baseT_Full |
  4207. ADVERTISED_1000baseT_Half |
  4208. ADVERTISED_1000baseT_Full |
  4209. ADVERTISED_10000baseT_Full |
  4210. ADVERTISED_FIBRE;
  4211. ecmd->speed = SPEED_10000;
  4212. ecmd->port = PORT_FIBRE;
  4213. break;
  4214. default:
  4215. ecmd->supported |= SUPPORTED_10baseT_Half |
  4216. SUPPORTED_10baseT_Full |
  4217. SUPPORTED_TP;
  4218. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4219. ADVERTISED_10baseT_Full |
  4220. ADVERTISED_TP;
  4221. ecmd->speed = SPEED_10;
  4222. ecmd->port = PORT_TP;
  4223. }
  4224. return 0;
  4225. }
  4226. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4227. static int __init qeth_core_init(void)
  4228. {
  4229. int rc;
  4230. pr_info("loading core functions\n");
  4231. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4232. rwlock_init(&qeth_core_card_list.rwlock);
  4233. rc = qeth_register_dbf_views();
  4234. if (rc)
  4235. goto out_err;
  4236. rc = ccw_driver_register(&qeth_ccw_driver);
  4237. if (rc)
  4238. goto ccw_err;
  4239. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4240. if (rc)
  4241. goto ccwgroup_err;
  4242. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4243. &driver_attr_group);
  4244. if (rc)
  4245. goto driver_err;
  4246. qeth_core_root_dev = root_device_register("qeth");
  4247. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4248. if (rc)
  4249. goto register_err;
  4250. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4251. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4252. if (!qeth_core_header_cache) {
  4253. rc = -ENOMEM;
  4254. goto slab_err;
  4255. }
  4256. return 0;
  4257. slab_err:
  4258. root_device_unregister(qeth_core_root_dev);
  4259. register_err:
  4260. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4261. &driver_attr_group);
  4262. driver_err:
  4263. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4264. ccwgroup_err:
  4265. ccw_driver_unregister(&qeth_ccw_driver);
  4266. ccw_err:
  4267. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4268. qeth_unregister_dbf_views();
  4269. out_err:
  4270. pr_err("Initializing the qeth device driver failed\n");
  4271. return rc;
  4272. }
  4273. static void __exit qeth_core_exit(void)
  4274. {
  4275. root_device_unregister(qeth_core_root_dev);
  4276. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4277. &driver_attr_group);
  4278. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4279. ccw_driver_unregister(&qeth_ccw_driver);
  4280. kmem_cache_destroy(qeth_core_header_cache);
  4281. qeth_unregister_dbf_views();
  4282. pr_info("core functions removed\n");
  4283. }
  4284. module_init(qeth_core_init);
  4285. module_exit(qeth_core_exit);
  4286. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4287. MODULE_DESCRIPTION("qeth core functions");
  4288. MODULE_LICENSE("GPL");