ioasm.h 2.4 KB

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  1. #ifndef S390_CIO_IOASM_H
  2. #define S390_CIO_IOASM_H
  3. #include <asm/chpid.h>
  4. #include <asm/schid.h>
  5. /*
  6. * TPI info structure
  7. */
  8. struct tpi_info {
  9. struct subchannel_id schid;
  10. __u32 intparm; /* interruption parameter */
  11. __u32 adapter_IO : 1;
  12. __u32 reserved2 : 1;
  13. __u32 isc : 3;
  14. __u32 reserved3 : 12;
  15. __u32 int_type : 3;
  16. __u32 reserved4 : 12;
  17. } __attribute__ ((packed));
  18. /*
  19. * Some S390 specific IO instructions as inline
  20. */
  21. static inline int stsch_err(struct subchannel_id schid, struct schib *addr)
  22. {
  23. register struct subchannel_id reg1 asm ("1") = schid;
  24. int ccode = -EIO;
  25. asm volatile(
  26. " stsch 0(%3)\n"
  27. "0: ipm %0\n"
  28. " srl %0,28\n"
  29. "1:\n"
  30. EX_TABLE(0b,1b)
  31. : "+d" (ccode), "=m" (*addr)
  32. : "d" (reg1), "a" (addr)
  33. : "cc");
  34. return ccode;
  35. }
  36. static inline int msch(struct subchannel_id schid, struct schib *addr)
  37. {
  38. register struct subchannel_id reg1 asm ("1") = schid;
  39. int ccode;
  40. asm volatile(
  41. " msch 0(%2)\n"
  42. " ipm %0\n"
  43. " srl %0,28"
  44. : "=d" (ccode)
  45. : "d" (reg1), "a" (addr), "m" (*addr)
  46. : "cc");
  47. return ccode;
  48. }
  49. static inline int msch_err(struct subchannel_id schid, struct schib *addr)
  50. {
  51. register struct subchannel_id reg1 asm ("1") = schid;
  52. int ccode = -EIO;
  53. asm volatile(
  54. " msch 0(%2)\n"
  55. "0: ipm %0\n"
  56. " srl %0,28\n"
  57. "1:\n"
  58. EX_TABLE(0b,1b)
  59. : "+d" (ccode)
  60. : "d" (reg1), "a" (addr), "m" (*addr)
  61. : "cc");
  62. return ccode;
  63. }
  64. static inline int tsch(struct subchannel_id schid, struct irb *addr)
  65. {
  66. register struct subchannel_id reg1 asm ("1") = schid;
  67. int ccode;
  68. asm volatile(
  69. " tsch 0(%3)\n"
  70. " ipm %0\n"
  71. " srl %0,28"
  72. : "=d" (ccode), "=m" (*addr)
  73. : "d" (reg1), "a" (addr)
  74. : "cc");
  75. return ccode;
  76. }
  77. static inline int tpi(struct tpi_info *addr)
  78. {
  79. int ccode;
  80. asm volatile(
  81. " tpi 0(%2)\n"
  82. " ipm %0\n"
  83. " srl %0,28"
  84. : "=d" (ccode), "=m" (*addr)
  85. : "a" (addr)
  86. : "cc");
  87. return ccode;
  88. }
  89. static inline int chsc(void *chsc_area)
  90. {
  91. typedef struct { char _[4096]; } addr_type;
  92. int cc;
  93. asm volatile(
  94. " .insn rre,0xb25f0000,%2,0\n"
  95. " ipm %0\n"
  96. " srl %0,28\n"
  97. : "=d" (cc), "=m" (*(addr_type *) chsc_area)
  98. : "d" (chsc_area), "m" (*(addr_type *) chsc_area)
  99. : "cc");
  100. return cc;
  101. }
  102. static inline int rchp(struct chp_id chpid)
  103. {
  104. register struct chp_id reg1 asm ("1") = chpid;
  105. int ccode;
  106. asm volatile(
  107. " lr 1,%1\n"
  108. " rchp\n"
  109. " ipm %0\n"
  110. " srl %0,28"
  111. : "=d" (ccode) : "d" (reg1) : "cc");
  112. return ccode;
  113. }
  114. #endif