rtc-pl031.c 13 KB

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  1. /*
  2. * drivers/rtc/rtc-pl031.c
  3. *
  4. * Real Time Clock interface for ARM AMBA PrimeCell 031 RTC
  5. *
  6. * Author: Deepak Saxena <dsaxena@plexity.net>
  7. *
  8. * Copyright 2006 (c) MontaVista Software, Inc.
  9. *
  10. * Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
  11. * Copyright 2010 (c) ST-Ericsson AB
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License
  15. * as published by the Free Software Foundation; either version
  16. * 2 of the License, or (at your option) any later version.
  17. */
  18. #include <linux/module.h>
  19. #include <linux/rtc.h>
  20. #include <linux/init.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/amba/bus.h>
  23. #include <linux/io.h>
  24. #include <linux/bcd.h>
  25. #include <linux/delay.h>
  26. #include <linux/slab.h>
  27. /*
  28. * Register definitions
  29. */
  30. #define RTC_DR 0x00 /* Data read register */
  31. #define RTC_MR 0x04 /* Match register */
  32. #define RTC_LR 0x08 /* Data load register */
  33. #define RTC_CR 0x0c /* Control register */
  34. #define RTC_IMSC 0x10 /* Interrupt mask and set register */
  35. #define RTC_RIS 0x14 /* Raw interrupt status register */
  36. #define RTC_MIS 0x18 /* Masked interrupt status register */
  37. #define RTC_ICR 0x1c /* Interrupt clear register */
  38. /* ST variants have additional timer functionality */
  39. #define RTC_TDR 0x20 /* Timer data read register */
  40. #define RTC_TLR 0x24 /* Timer data load register */
  41. #define RTC_TCR 0x28 /* Timer control register */
  42. #define RTC_YDR 0x30 /* Year data read register */
  43. #define RTC_YMR 0x34 /* Year match register */
  44. #define RTC_YLR 0x38 /* Year data load register */
  45. #define RTC_CR_CWEN (1 << 26) /* Clockwatch enable bit */
  46. #define RTC_TCR_EN (1 << 1) /* Periodic timer enable bit */
  47. /* Common bit definitions for Interrupt status and control registers */
  48. #define RTC_BIT_AI (1 << 0) /* Alarm interrupt bit */
  49. #define RTC_BIT_PI (1 << 1) /* Periodic interrupt bit. ST variants only. */
  50. /* Common bit definations for ST v2 for reading/writing time */
  51. #define RTC_SEC_SHIFT 0
  52. #define RTC_SEC_MASK (0x3F << RTC_SEC_SHIFT) /* Second [0-59] */
  53. #define RTC_MIN_SHIFT 6
  54. #define RTC_MIN_MASK (0x3F << RTC_MIN_SHIFT) /* Minute [0-59] */
  55. #define RTC_HOUR_SHIFT 12
  56. #define RTC_HOUR_MASK (0x1F << RTC_HOUR_SHIFT) /* Hour [0-23] */
  57. #define RTC_WDAY_SHIFT 17
  58. #define RTC_WDAY_MASK (0x7 << RTC_WDAY_SHIFT) /* Day of Week [1-7] 1=Sunday */
  59. #define RTC_MDAY_SHIFT 20
  60. #define RTC_MDAY_MASK (0x1F << RTC_MDAY_SHIFT) /* Day of Month [1-31] */
  61. #define RTC_MON_SHIFT 25
  62. #define RTC_MON_MASK (0xF << RTC_MON_SHIFT) /* Month [1-12] 1=January */
  63. #define RTC_TIMER_FREQ 32768
  64. struct pl031_local {
  65. struct rtc_device *rtc;
  66. void __iomem *base;
  67. u8 hw_designer;
  68. u8 hw_revision:4;
  69. };
  70. static int pl031_alarm_irq_enable(struct device *dev,
  71. unsigned int enabled)
  72. {
  73. struct pl031_local *ldata = dev_get_drvdata(dev);
  74. unsigned long imsc;
  75. /* Clear any pending alarm interrupts. */
  76. writel(RTC_BIT_AI, ldata->base + RTC_ICR);
  77. imsc = readl(ldata->base + RTC_IMSC);
  78. if (enabled == 1)
  79. writel(imsc | RTC_BIT_AI, ldata->base + RTC_IMSC);
  80. else
  81. writel(imsc & ~RTC_BIT_AI, ldata->base + RTC_IMSC);
  82. return 0;
  83. }
  84. /*
  85. * Convert Gregorian date to ST v2 RTC format.
  86. */
  87. static int pl031_stv2_tm_to_time(struct device *dev,
  88. struct rtc_time *tm, unsigned long *st_time,
  89. unsigned long *bcd_year)
  90. {
  91. int year = tm->tm_year + 1900;
  92. int wday = tm->tm_wday;
  93. /* wday masking is not working in hardware so wday must be valid */
  94. if (wday < -1 || wday > 6) {
  95. dev_err(dev, "invalid wday value %d\n", tm->tm_wday);
  96. return -EINVAL;
  97. } else if (wday == -1) {
  98. /* wday is not provided, calculate it here */
  99. unsigned long time;
  100. struct rtc_time calc_tm;
  101. rtc_tm_to_time(tm, &time);
  102. rtc_time_to_tm(time, &calc_tm);
  103. wday = calc_tm.tm_wday;
  104. }
  105. *bcd_year = (bin2bcd(year % 100) | bin2bcd(year / 100) << 8);
  106. *st_time = ((tm->tm_mon + 1) << RTC_MON_SHIFT)
  107. | (tm->tm_mday << RTC_MDAY_SHIFT)
  108. | ((wday + 1) << RTC_WDAY_SHIFT)
  109. | (tm->tm_hour << RTC_HOUR_SHIFT)
  110. | (tm->tm_min << RTC_MIN_SHIFT)
  111. | (tm->tm_sec << RTC_SEC_SHIFT);
  112. return 0;
  113. }
  114. /*
  115. * Convert ST v2 RTC format to Gregorian date.
  116. */
  117. static int pl031_stv2_time_to_tm(unsigned long st_time, unsigned long bcd_year,
  118. struct rtc_time *tm)
  119. {
  120. tm->tm_year = bcd2bin(bcd_year) + (bcd2bin(bcd_year >> 8) * 100);
  121. tm->tm_mon = ((st_time & RTC_MON_MASK) >> RTC_MON_SHIFT) - 1;
  122. tm->tm_mday = ((st_time & RTC_MDAY_MASK) >> RTC_MDAY_SHIFT);
  123. tm->tm_wday = ((st_time & RTC_WDAY_MASK) >> RTC_WDAY_SHIFT) - 1;
  124. tm->tm_hour = ((st_time & RTC_HOUR_MASK) >> RTC_HOUR_SHIFT);
  125. tm->tm_min = ((st_time & RTC_MIN_MASK) >> RTC_MIN_SHIFT);
  126. tm->tm_sec = ((st_time & RTC_SEC_MASK) >> RTC_SEC_SHIFT);
  127. tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
  128. tm->tm_year -= 1900;
  129. return 0;
  130. }
  131. static int pl031_stv2_read_time(struct device *dev, struct rtc_time *tm)
  132. {
  133. struct pl031_local *ldata = dev_get_drvdata(dev);
  134. pl031_stv2_time_to_tm(readl(ldata->base + RTC_DR),
  135. readl(ldata->base + RTC_YDR), tm);
  136. return 0;
  137. }
  138. static int pl031_stv2_set_time(struct device *dev, struct rtc_time *tm)
  139. {
  140. unsigned long time;
  141. unsigned long bcd_year;
  142. struct pl031_local *ldata = dev_get_drvdata(dev);
  143. int ret;
  144. ret = pl031_stv2_tm_to_time(dev, tm, &time, &bcd_year);
  145. if (ret == 0) {
  146. writel(bcd_year, ldata->base + RTC_YLR);
  147. writel(time, ldata->base + RTC_LR);
  148. }
  149. return ret;
  150. }
  151. static int pl031_stv2_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  152. {
  153. struct pl031_local *ldata = dev_get_drvdata(dev);
  154. int ret;
  155. ret = pl031_stv2_time_to_tm(readl(ldata->base + RTC_MR),
  156. readl(ldata->base + RTC_YMR), &alarm->time);
  157. alarm->pending = readl(ldata->base + RTC_RIS) & RTC_BIT_AI;
  158. alarm->enabled = readl(ldata->base + RTC_IMSC) & RTC_BIT_AI;
  159. return ret;
  160. }
  161. static int pl031_stv2_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  162. {
  163. struct pl031_local *ldata = dev_get_drvdata(dev);
  164. unsigned long time;
  165. unsigned long bcd_year;
  166. int ret;
  167. /* At the moment, we can only deal with non-wildcarded alarm times. */
  168. ret = rtc_valid_tm(&alarm->time);
  169. if (ret == 0) {
  170. ret = pl031_stv2_tm_to_time(dev, &alarm->time,
  171. &time, &bcd_year);
  172. if (ret == 0) {
  173. writel(bcd_year, ldata->base + RTC_YMR);
  174. writel(time, ldata->base + RTC_MR);
  175. pl031_alarm_irq_enable(dev, alarm->enabled);
  176. }
  177. }
  178. return ret;
  179. }
  180. static irqreturn_t pl031_interrupt(int irq, void *dev_id)
  181. {
  182. struct pl031_local *ldata = dev_id;
  183. unsigned long rtcmis;
  184. unsigned long events = 0;
  185. rtcmis = readl(ldata->base + RTC_MIS);
  186. if (rtcmis) {
  187. writel(rtcmis, ldata->base + RTC_ICR);
  188. if (rtcmis & RTC_BIT_AI)
  189. events |= (RTC_AF | RTC_IRQF);
  190. /* Timer interrupt is only available in ST variants */
  191. if ((rtcmis & RTC_BIT_PI) &&
  192. (ldata->hw_designer == AMBA_VENDOR_ST))
  193. events |= (RTC_PF | RTC_IRQF);
  194. rtc_update_irq(ldata->rtc, 1, events);
  195. return IRQ_HANDLED;
  196. }
  197. return IRQ_NONE;
  198. }
  199. static int pl031_read_time(struct device *dev, struct rtc_time *tm)
  200. {
  201. struct pl031_local *ldata = dev_get_drvdata(dev);
  202. rtc_time_to_tm(readl(ldata->base + RTC_DR), tm);
  203. return 0;
  204. }
  205. static int pl031_set_time(struct device *dev, struct rtc_time *tm)
  206. {
  207. unsigned long time;
  208. struct pl031_local *ldata = dev_get_drvdata(dev);
  209. int ret;
  210. ret = rtc_tm_to_time(tm, &time);
  211. if (ret == 0)
  212. writel(time, ldata->base + RTC_LR);
  213. return ret;
  214. }
  215. static int pl031_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  216. {
  217. struct pl031_local *ldata = dev_get_drvdata(dev);
  218. rtc_time_to_tm(readl(ldata->base + RTC_MR), &alarm->time);
  219. alarm->pending = readl(ldata->base + RTC_RIS) & RTC_BIT_AI;
  220. alarm->enabled = readl(ldata->base + RTC_IMSC) & RTC_BIT_AI;
  221. return 0;
  222. }
  223. static int pl031_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  224. {
  225. struct pl031_local *ldata = dev_get_drvdata(dev);
  226. unsigned long time;
  227. int ret;
  228. /* At the moment, we can only deal with non-wildcarded alarm times. */
  229. ret = rtc_valid_tm(&alarm->time);
  230. if (ret == 0) {
  231. ret = rtc_tm_to_time(&alarm->time, &time);
  232. if (ret == 0) {
  233. writel(time, ldata->base + RTC_MR);
  234. pl031_alarm_irq_enable(dev, alarm->enabled);
  235. }
  236. }
  237. return ret;
  238. }
  239. /* Periodic interrupt is only available in ST variants. */
  240. static int pl031_irq_set_state(struct device *dev, int enabled)
  241. {
  242. struct pl031_local *ldata = dev_get_drvdata(dev);
  243. if (enabled == 1) {
  244. /* Clear any pending timer interrupt. */
  245. writel(RTC_BIT_PI, ldata->base + RTC_ICR);
  246. writel(readl(ldata->base + RTC_IMSC) | RTC_BIT_PI,
  247. ldata->base + RTC_IMSC);
  248. /* Now start the timer */
  249. writel(readl(ldata->base + RTC_TCR) | RTC_TCR_EN,
  250. ldata->base + RTC_TCR);
  251. } else {
  252. writel(readl(ldata->base + RTC_IMSC) & (~RTC_BIT_PI),
  253. ldata->base + RTC_IMSC);
  254. /* Also stop the timer */
  255. writel(readl(ldata->base + RTC_TCR) & (~RTC_TCR_EN),
  256. ldata->base + RTC_TCR);
  257. }
  258. /* Wait at least 1 RTC32 clock cycle to ensure next access
  259. * to RTC_TCR will succeed.
  260. */
  261. udelay(40);
  262. return 0;
  263. }
  264. static int pl031_irq_set_freq(struct device *dev, int freq)
  265. {
  266. struct pl031_local *ldata = dev_get_drvdata(dev);
  267. /* Cant set timer if it is already enabled */
  268. if (readl(ldata->base + RTC_TCR) & RTC_TCR_EN) {
  269. dev_err(dev, "can't change frequency while timer enabled\n");
  270. return -EINVAL;
  271. }
  272. /* If self start bit in RTC_TCR is set timer will start here,
  273. * but we never set that bit. Instead we start the timer when
  274. * set_state is called with enabled == 1.
  275. */
  276. writel(RTC_TIMER_FREQ / freq, ldata->base + RTC_TLR);
  277. return 0;
  278. }
  279. static int pl031_remove(struct amba_device *adev)
  280. {
  281. struct pl031_local *ldata = dev_get_drvdata(&adev->dev);
  282. amba_set_drvdata(adev, NULL);
  283. free_irq(adev->irq[0], ldata->rtc);
  284. rtc_device_unregister(ldata->rtc);
  285. iounmap(ldata->base);
  286. kfree(ldata);
  287. amba_release_regions(adev);
  288. return 0;
  289. }
  290. static int pl031_probe(struct amba_device *adev, struct amba_id *id)
  291. {
  292. int ret;
  293. struct pl031_local *ldata;
  294. struct rtc_class_ops *ops = id->data;
  295. ret = amba_request_regions(adev, NULL);
  296. if (ret)
  297. goto err_req;
  298. ldata = kzalloc(sizeof(struct pl031_local), GFP_KERNEL);
  299. if (!ldata) {
  300. ret = -ENOMEM;
  301. goto out;
  302. }
  303. ldata->base = ioremap(adev->res.start, resource_size(&adev->res));
  304. if (!ldata->base) {
  305. ret = -ENOMEM;
  306. goto out_no_remap;
  307. }
  308. amba_set_drvdata(adev, ldata);
  309. ldata->hw_designer = amba_manf(adev);
  310. ldata->hw_revision = amba_rev(adev);
  311. dev_dbg(&adev->dev, "designer ID = 0x%02x\n", ldata->hw_designer);
  312. dev_dbg(&adev->dev, "revision = 0x%01x\n", ldata->hw_revision);
  313. /* Enable the clockwatch on ST Variants */
  314. if ((ldata->hw_designer == AMBA_VENDOR_ST) &&
  315. (ldata->hw_revision > 1))
  316. writel(readl(ldata->base + RTC_CR) | RTC_CR_CWEN,
  317. ldata->base + RTC_CR);
  318. ldata->rtc = rtc_device_register("pl031", &adev->dev, ops,
  319. THIS_MODULE);
  320. if (IS_ERR(ldata->rtc)) {
  321. ret = PTR_ERR(ldata->rtc);
  322. goto out_no_rtc;
  323. }
  324. if (request_irq(adev->irq[0], pl031_interrupt,
  325. IRQF_DISABLED, "rtc-pl031", ldata)) {
  326. ret = -EIO;
  327. goto out_no_irq;
  328. }
  329. return 0;
  330. out_no_irq:
  331. rtc_device_unregister(ldata->rtc);
  332. out_no_rtc:
  333. iounmap(ldata->base);
  334. amba_set_drvdata(adev, NULL);
  335. out_no_remap:
  336. kfree(ldata);
  337. out:
  338. amba_release_regions(adev);
  339. err_req:
  340. return ret;
  341. }
  342. /* Operations for the original ARM version */
  343. static struct rtc_class_ops arm_pl031_ops = {
  344. .read_time = pl031_read_time,
  345. .set_time = pl031_set_time,
  346. .read_alarm = pl031_read_alarm,
  347. .set_alarm = pl031_set_alarm,
  348. .alarm_irq_enable = pl031_alarm_irq_enable,
  349. };
  350. /* The First ST derivative */
  351. static struct rtc_class_ops stv1_pl031_ops = {
  352. .read_time = pl031_read_time,
  353. .set_time = pl031_set_time,
  354. .read_alarm = pl031_read_alarm,
  355. .set_alarm = pl031_set_alarm,
  356. .alarm_irq_enable = pl031_alarm_irq_enable,
  357. .irq_set_state = pl031_irq_set_state,
  358. .irq_set_freq = pl031_irq_set_freq,
  359. };
  360. /* And the second ST derivative */
  361. static struct rtc_class_ops stv2_pl031_ops = {
  362. .read_time = pl031_stv2_read_time,
  363. .set_time = pl031_stv2_set_time,
  364. .read_alarm = pl031_stv2_read_alarm,
  365. .set_alarm = pl031_stv2_set_alarm,
  366. .alarm_irq_enable = pl031_alarm_irq_enable,
  367. .irq_set_state = pl031_irq_set_state,
  368. .irq_set_freq = pl031_irq_set_freq,
  369. };
  370. static struct amba_id pl031_ids[] = {
  371. {
  372. .id = 0x00041031,
  373. .mask = 0x000fffff,
  374. .data = &arm_pl031_ops,
  375. },
  376. /* ST Micro variants */
  377. {
  378. .id = 0x00180031,
  379. .mask = 0x00ffffff,
  380. .data = &stv1_pl031_ops,
  381. },
  382. {
  383. .id = 0x00280031,
  384. .mask = 0x00ffffff,
  385. .data = &stv2_pl031_ops,
  386. },
  387. {0, 0},
  388. };
  389. static struct amba_driver pl031_driver = {
  390. .drv = {
  391. .name = "rtc-pl031",
  392. },
  393. .id_table = pl031_ids,
  394. .probe = pl031_probe,
  395. .remove = pl031_remove,
  396. };
  397. static int __init pl031_init(void)
  398. {
  399. return amba_driver_register(&pl031_driver);
  400. }
  401. static void __exit pl031_exit(void)
  402. {
  403. amba_driver_unregister(&pl031_driver);
  404. }
  405. module_init(pl031_init);
  406. module_exit(pl031_exit);
  407. MODULE_AUTHOR("Deepak Saxena <dsaxena@plexity.net");
  408. MODULE_DESCRIPTION("ARM AMBA PL031 RTC Driver");
  409. MODULE_LICENSE("GPL");