ab8500-core.c 12 KB

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  1. /*
  2. * Copyright (C) ST-Ericsson SA 2010
  3. *
  4. * License Terms: GNU General Public License v2
  5. * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
  6. * Author: Rabin Vincent <rabin.vincent@stericsson.com>
  7. * Changes: Mattias Wallin <mattias.wallin@stericsson.com>
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/slab.h>
  11. #include <linux/init.h>
  12. #include <linux/irq.h>
  13. #include <linux/delay.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/module.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/mfd/core.h>
  18. #include <linux/mfd/abx500.h>
  19. #include <linux/mfd/ab8500.h>
  20. #include <linux/regulator/ab8500.h>
  21. /*
  22. * Interrupt register offsets
  23. * Bank : 0x0E
  24. */
  25. #define AB8500_IT_SOURCE1_REG 0x00
  26. #define AB8500_IT_SOURCE2_REG 0x01
  27. #define AB8500_IT_SOURCE3_REG 0x02
  28. #define AB8500_IT_SOURCE4_REG 0x03
  29. #define AB8500_IT_SOURCE5_REG 0x04
  30. #define AB8500_IT_SOURCE6_REG 0x05
  31. #define AB8500_IT_SOURCE7_REG 0x06
  32. #define AB8500_IT_SOURCE8_REG 0x07
  33. #define AB8500_IT_SOURCE19_REG 0x12
  34. #define AB8500_IT_SOURCE20_REG 0x13
  35. #define AB8500_IT_SOURCE21_REG 0x14
  36. #define AB8500_IT_SOURCE22_REG 0x15
  37. #define AB8500_IT_SOURCE23_REG 0x16
  38. #define AB8500_IT_SOURCE24_REG 0x17
  39. /*
  40. * latch registers
  41. */
  42. #define AB8500_IT_LATCH1_REG 0x20
  43. #define AB8500_IT_LATCH2_REG 0x21
  44. #define AB8500_IT_LATCH3_REG 0x22
  45. #define AB8500_IT_LATCH4_REG 0x23
  46. #define AB8500_IT_LATCH5_REG 0x24
  47. #define AB8500_IT_LATCH6_REG 0x25
  48. #define AB8500_IT_LATCH7_REG 0x26
  49. #define AB8500_IT_LATCH8_REG 0x27
  50. #define AB8500_IT_LATCH9_REG 0x28
  51. #define AB8500_IT_LATCH10_REG 0x29
  52. #define AB8500_IT_LATCH19_REG 0x32
  53. #define AB8500_IT_LATCH20_REG 0x33
  54. #define AB8500_IT_LATCH21_REG 0x34
  55. #define AB8500_IT_LATCH22_REG 0x35
  56. #define AB8500_IT_LATCH23_REG 0x36
  57. #define AB8500_IT_LATCH24_REG 0x37
  58. /*
  59. * mask registers
  60. */
  61. #define AB8500_IT_MASK1_REG 0x40
  62. #define AB8500_IT_MASK2_REG 0x41
  63. #define AB8500_IT_MASK3_REG 0x42
  64. #define AB8500_IT_MASK4_REG 0x43
  65. #define AB8500_IT_MASK5_REG 0x44
  66. #define AB8500_IT_MASK6_REG 0x45
  67. #define AB8500_IT_MASK7_REG 0x46
  68. #define AB8500_IT_MASK8_REG 0x47
  69. #define AB8500_IT_MASK9_REG 0x48
  70. #define AB8500_IT_MASK10_REG 0x49
  71. #define AB8500_IT_MASK11_REG 0x4A
  72. #define AB8500_IT_MASK12_REG 0x4B
  73. #define AB8500_IT_MASK13_REG 0x4C
  74. #define AB8500_IT_MASK14_REG 0x4D
  75. #define AB8500_IT_MASK15_REG 0x4E
  76. #define AB8500_IT_MASK16_REG 0x4F
  77. #define AB8500_IT_MASK17_REG 0x50
  78. #define AB8500_IT_MASK18_REG 0x51
  79. #define AB8500_IT_MASK19_REG 0x52
  80. #define AB8500_IT_MASK20_REG 0x53
  81. #define AB8500_IT_MASK21_REG 0x54
  82. #define AB8500_IT_MASK22_REG 0x55
  83. #define AB8500_IT_MASK23_REG 0x56
  84. #define AB8500_IT_MASK24_REG 0x57
  85. #define AB8500_REV_REG 0x80
  86. /*
  87. * Map interrupt numbers to the LATCH and MASK register offsets, Interrupt
  88. * numbers are indexed into this array with (num / 8).
  89. *
  90. * This is one off from the register names, i.e. AB8500_IT_MASK1_REG is at
  91. * offset 0.
  92. */
  93. static const int ab8500_irq_regoffset[AB8500_NUM_IRQ_REGS] = {
  94. 0, 1, 2, 3, 4, 6, 7, 8, 9, 18, 19, 20, 21,
  95. };
  96. static int ab8500_get_chip_id(struct device *dev)
  97. {
  98. struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
  99. return (int)ab8500->chip_id;
  100. }
  101. static int set_register_interruptible(struct ab8500 *ab8500, u8 bank,
  102. u8 reg, u8 data)
  103. {
  104. int ret;
  105. /*
  106. * Put the u8 bank and u8 register together into a an u16.
  107. * The bank on higher 8 bits and register in lower 8 bits.
  108. * */
  109. u16 addr = ((u16)bank) << 8 | reg;
  110. dev_vdbg(ab8500->dev, "wr: addr %#x <= %#x\n", addr, data);
  111. ret = mutex_lock_interruptible(&ab8500->lock);
  112. if (ret)
  113. return ret;
  114. ret = ab8500->write(ab8500, addr, data);
  115. if (ret < 0)
  116. dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
  117. addr, ret);
  118. mutex_unlock(&ab8500->lock);
  119. return ret;
  120. }
  121. static int ab8500_set_register(struct device *dev, u8 bank,
  122. u8 reg, u8 value)
  123. {
  124. struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
  125. return set_register_interruptible(ab8500, bank, reg, value);
  126. }
  127. static int get_register_interruptible(struct ab8500 *ab8500, u8 bank,
  128. u8 reg, u8 *value)
  129. {
  130. int ret;
  131. /* put the u8 bank and u8 reg together into a an u16.
  132. * bank on higher 8 bits and reg in lower */
  133. u16 addr = ((u16)bank) << 8 | reg;
  134. ret = mutex_lock_interruptible(&ab8500->lock);
  135. if (ret)
  136. return ret;
  137. ret = ab8500->read(ab8500, addr);
  138. if (ret < 0)
  139. dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
  140. addr, ret);
  141. else
  142. *value = ret;
  143. mutex_unlock(&ab8500->lock);
  144. dev_vdbg(ab8500->dev, "rd: addr %#x => data %#x\n", addr, ret);
  145. return ret;
  146. }
  147. static int ab8500_get_register(struct device *dev, u8 bank,
  148. u8 reg, u8 *value)
  149. {
  150. struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
  151. return get_register_interruptible(ab8500, bank, reg, value);
  152. }
  153. static int mask_and_set_register_interruptible(struct ab8500 *ab8500, u8 bank,
  154. u8 reg, u8 bitmask, u8 bitvalues)
  155. {
  156. int ret;
  157. u8 data;
  158. /* put the u8 bank and u8 reg together into a an u16.
  159. * bank on higher 8 bits and reg in lower */
  160. u16 addr = ((u16)bank) << 8 | reg;
  161. ret = mutex_lock_interruptible(&ab8500->lock);
  162. if (ret)
  163. return ret;
  164. ret = ab8500->read(ab8500, addr);
  165. if (ret < 0) {
  166. dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
  167. addr, ret);
  168. goto out;
  169. }
  170. data = (u8)ret;
  171. data = (~bitmask & data) | (bitmask & bitvalues);
  172. ret = ab8500->write(ab8500, addr, data);
  173. if (ret < 0)
  174. dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
  175. addr, ret);
  176. dev_vdbg(ab8500->dev, "mask: addr %#x => data %#x\n", addr, data);
  177. out:
  178. mutex_unlock(&ab8500->lock);
  179. return ret;
  180. }
  181. static int ab8500_mask_and_set_register(struct device *dev,
  182. u8 bank, u8 reg, u8 bitmask, u8 bitvalues)
  183. {
  184. struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
  185. return mask_and_set_register_interruptible(ab8500, bank, reg,
  186. bitmask, bitvalues);
  187. }
  188. static struct abx500_ops ab8500_ops = {
  189. .get_chip_id = ab8500_get_chip_id,
  190. .get_register = ab8500_get_register,
  191. .set_register = ab8500_set_register,
  192. .get_register_page = NULL,
  193. .set_register_page = NULL,
  194. .mask_and_set_register = ab8500_mask_and_set_register,
  195. .event_registers_startup_state_get = NULL,
  196. .startup_irq_enabled = NULL,
  197. };
  198. static void ab8500_irq_lock(unsigned int irq)
  199. {
  200. struct ab8500 *ab8500 = get_irq_chip_data(irq);
  201. mutex_lock(&ab8500->irq_lock);
  202. }
  203. static void ab8500_irq_sync_unlock(unsigned int irq)
  204. {
  205. struct ab8500 *ab8500 = get_irq_chip_data(irq);
  206. int i;
  207. for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) {
  208. u8 old = ab8500->oldmask[i];
  209. u8 new = ab8500->mask[i];
  210. int reg;
  211. if (new == old)
  212. continue;
  213. ab8500->oldmask[i] = new;
  214. reg = AB8500_IT_MASK1_REG + ab8500_irq_regoffset[i];
  215. set_register_interruptible(ab8500, AB8500_INTERRUPT, reg, new);
  216. }
  217. mutex_unlock(&ab8500->irq_lock);
  218. }
  219. static void ab8500_irq_mask(unsigned int irq)
  220. {
  221. struct ab8500 *ab8500 = get_irq_chip_data(irq);
  222. int offset = irq - ab8500->irq_base;
  223. int index = offset / 8;
  224. int mask = 1 << (offset % 8);
  225. ab8500->mask[index] |= mask;
  226. }
  227. static void ab8500_irq_unmask(unsigned int irq)
  228. {
  229. struct ab8500 *ab8500 = get_irq_chip_data(irq);
  230. int offset = irq - ab8500->irq_base;
  231. int index = offset / 8;
  232. int mask = 1 << (offset % 8);
  233. ab8500->mask[index] &= ~mask;
  234. }
  235. static struct irq_chip ab8500_irq_chip = {
  236. .name = "ab8500",
  237. .bus_lock = ab8500_irq_lock,
  238. .bus_sync_unlock = ab8500_irq_sync_unlock,
  239. .mask = ab8500_irq_mask,
  240. .unmask = ab8500_irq_unmask,
  241. };
  242. static irqreturn_t ab8500_irq(int irq, void *dev)
  243. {
  244. struct ab8500 *ab8500 = dev;
  245. int i;
  246. dev_vdbg(ab8500->dev, "interrupt\n");
  247. for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) {
  248. int regoffset = ab8500_irq_regoffset[i];
  249. int status;
  250. u8 value;
  251. status = get_register_interruptible(ab8500, AB8500_INTERRUPT,
  252. AB8500_IT_LATCH1_REG + regoffset, &value);
  253. if (status < 0 || value == 0)
  254. continue;
  255. do {
  256. int bit = __ffs(value);
  257. int line = i * 8 + bit;
  258. handle_nested_irq(ab8500->irq_base + line);
  259. value &= ~(1 << bit);
  260. } while (value);
  261. }
  262. return IRQ_HANDLED;
  263. }
  264. static int ab8500_irq_init(struct ab8500 *ab8500)
  265. {
  266. int base = ab8500->irq_base;
  267. int irq;
  268. for (irq = base; irq < base + AB8500_NR_IRQS; irq++) {
  269. set_irq_chip_data(irq, ab8500);
  270. set_irq_chip_and_handler(irq, &ab8500_irq_chip,
  271. handle_simple_irq);
  272. set_irq_nested_thread(irq, 1);
  273. #ifdef CONFIG_ARM
  274. set_irq_flags(irq, IRQF_VALID);
  275. #else
  276. set_irq_noprobe(irq);
  277. #endif
  278. }
  279. return 0;
  280. }
  281. static void ab8500_irq_remove(struct ab8500 *ab8500)
  282. {
  283. int base = ab8500->irq_base;
  284. int irq;
  285. for (irq = base; irq < base + AB8500_NR_IRQS; irq++) {
  286. #ifdef CONFIG_ARM
  287. set_irq_flags(irq, 0);
  288. #endif
  289. set_irq_chip_and_handler(irq, NULL, NULL);
  290. set_irq_chip_data(irq, NULL);
  291. }
  292. }
  293. static struct resource ab8500_gpadc_resources[] = {
  294. {
  295. .name = "HW_CONV_END",
  296. .start = AB8500_INT_GP_HW_ADC_CONV_END,
  297. .end = AB8500_INT_GP_HW_ADC_CONV_END,
  298. .flags = IORESOURCE_IRQ,
  299. },
  300. {
  301. .name = "SW_CONV_END",
  302. .start = AB8500_INT_GP_SW_ADC_CONV_END,
  303. .end = AB8500_INT_GP_SW_ADC_CONV_END,
  304. .flags = IORESOURCE_IRQ,
  305. },
  306. };
  307. static struct resource ab8500_rtc_resources[] = {
  308. {
  309. .name = "60S",
  310. .start = AB8500_INT_RTC_60S,
  311. .end = AB8500_INT_RTC_60S,
  312. .flags = IORESOURCE_IRQ,
  313. },
  314. {
  315. .name = "ALARM",
  316. .start = AB8500_INT_RTC_ALARM,
  317. .end = AB8500_INT_RTC_ALARM,
  318. .flags = IORESOURCE_IRQ,
  319. },
  320. };
  321. static struct resource ab8500_poweronkey_db_resources[] = {
  322. {
  323. .name = "ONKEY_DBF",
  324. .start = AB8500_INT_PON_KEY1DB_F,
  325. .end = AB8500_INT_PON_KEY1DB_F,
  326. .flags = IORESOURCE_IRQ,
  327. },
  328. {
  329. .name = "ONKEY_DBR",
  330. .start = AB8500_INT_PON_KEY1DB_R,
  331. .end = AB8500_INT_PON_KEY1DB_R,
  332. .flags = IORESOURCE_IRQ,
  333. },
  334. };
  335. static struct mfd_cell ab8500_devs[] = {
  336. #ifdef CONFIG_DEBUG_FS
  337. {
  338. .name = "ab8500-debug",
  339. },
  340. #endif
  341. {
  342. .name = "ab8500-gpadc",
  343. .num_resources = ARRAY_SIZE(ab8500_gpadc_resources),
  344. .resources = ab8500_gpadc_resources,
  345. },
  346. {
  347. .name = "ab8500-rtc",
  348. .num_resources = ARRAY_SIZE(ab8500_rtc_resources),
  349. .resources = ab8500_rtc_resources,
  350. },
  351. {
  352. .name = "ab8500-pwm",
  353. .id = 1,
  354. },
  355. {
  356. .name = "ab8500-pwm",
  357. .id = 2,
  358. },
  359. {
  360. .name = "ab8500-pwm",
  361. .id = 3,
  362. },
  363. { .name = "ab8500-charger", },
  364. { .name = "ab8500-audio", },
  365. { .name = "ab8500-usb", },
  366. { .name = "ab8500-regulator", },
  367. {
  368. .name = "ab8500-poweron-key",
  369. .num_resources = ARRAY_SIZE(ab8500_poweronkey_db_resources),
  370. .resources = ab8500_poweronkey_db_resources,
  371. },
  372. };
  373. int __devinit ab8500_init(struct ab8500 *ab8500)
  374. {
  375. struct ab8500_platform_data *plat = dev_get_platdata(ab8500->dev);
  376. int ret;
  377. int i;
  378. u8 value;
  379. if (plat)
  380. ab8500->irq_base = plat->irq_base;
  381. mutex_init(&ab8500->lock);
  382. mutex_init(&ab8500->irq_lock);
  383. ret = get_register_interruptible(ab8500, AB8500_MISC,
  384. AB8500_REV_REG, &value);
  385. if (ret < 0)
  386. return ret;
  387. /*
  388. * 0x0 - Early Drop
  389. * 0x10 - Cut 1.0
  390. * 0x11 - Cut 1.1
  391. */
  392. if (value == 0x0 || value == 0x10 || value == 0x11) {
  393. ab8500->revision = value;
  394. dev_info(ab8500->dev, "detected chip, revision: %#x\n", value);
  395. } else {
  396. dev_err(ab8500->dev, "unknown chip, revision: %#x\n", value);
  397. return -EINVAL;
  398. }
  399. ab8500->chip_id = value;
  400. if (plat && plat->init)
  401. plat->init(ab8500);
  402. /* Clear and mask all interrupts */
  403. for (i = 0; i < 10; i++) {
  404. get_register_interruptible(ab8500, AB8500_INTERRUPT,
  405. AB8500_IT_LATCH1_REG + i, &value);
  406. set_register_interruptible(ab8500, AB8500_INTERRUPT,
  407. AB8500_IT_MASK1_REG + i, 0xff);
  408. }
  409. for (i = 18; i < 24; i++) {
  410. get_register_interruptible(ab8500, AB8500_INTERRUPT,
  411. AB8500_IT_LATCH1_REG + i, &value);
  412. set_register_interruptible(ab8500, AB8500_INTERRUPT,
  413. AB8500_IT_MASK1_REG + i, 0xff);
  414. }
  415. ret = abx500_register_ops(ab8500->dev, &ab8500_ops);
  416. if (ret)
  417. return ret;
  418. for (i = 0; i < AB8500_NUM_IRQ_REGS; i++)
  419. ab8500->mask[i] = ab8500->oldmask[i] = 0xff;
  420. if (ab8500->irq_base) {
  421. ret = ab8500_irq_init(ab8500);
  422. if (ret)
  423. return ret;
  424. ret = request_threaded_irq(ab8500->irq, NULL, ab8500_irq,
  425. IRQF_ONESHOT, "ab8500", ab8500);
  426. if (ret)
  427. goto out_removeirq;
  428. }
  429. ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs,
  430. ARRAY_SIZE(ab8500_devs), NULL,
  431. ab8500->irq_base);
  432. if (ret)
  433. goto out_freeirq;
  434. return ret;
  435. out_freeirq:
  436. if (ab8500->irq_base) {
  437. free_irq(ab8500->irq, ab8500);
  438. out_removeirq:
  439. ab8500_irq_remove(ab8500);
  440. }
  441. return ret;
  442. }
  443. int __devexit ab8500_exit(struct ab8500 *ab8500)
  444. {
  445. mfd_remove_devices(ab8500->dev);
  446. if (ab8500->irq_base) {
  447. free_irq(ab8500->irq, ab8500);
  448. ab8500_irq_remove(ab8500);
  449. }
  450. return 0;
  451. }
  452. MODULE_AUTHOR("Srinidhi Kasagar, Rabin Vincent");
  453. MODULE_DESCRIPTION("AB8500 MFD core");
  454. MODULE_LICENSE("GPL v2");