qib_rc.c 61 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294
  1. /*
  2. * Copyright (c) 2006, 2007, 2008, 2009 QLogic Corporation. All rights reserved.
  3. * Copyright (c) 2005, 2006 PathScale, Inc. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/io.h>
  34. #include "qib.h"
  35. /* cut down ridiculously long IB macro names */
  36. #define OP(x) IB_OPCODE_RC_##x
  37. static void rc_timeout(unsigned long arg);
  38. static u32 restart_sge(struct qib_sge_state *ss, struct qib_swqe *wqe,
  39. u32 psn, u32 pmtu)
  40. {
  41. u32 len;
  42. len = ((psn - wqe->psn) & QIB_PSN_MASK) * pmtu;
  43. ss->sge = wqe->sg_list[0];
  44. ss->sg_list = wqe->sg_list + 1;
  45. ss->num_sge = wqe->wr.num_sge;
  46. ss->total_len = wqe->length;
  47. qib_skip_sge(ss, len, 0);
  48. return wqe->length - len;
  49. }
  50. static void start_timer(struct qib_qp *qp)
  51. {
  52. qp->s_flags |= QIB_S_TIMER;
  53. qp->s_timer.function = rc_timeout;
  54. /* 4.096 usec. * (1 << qp->timeout) */
  55. qp->s_timer.expires = jiffies +
  56. usecs_to_jiffies((4096UL * (1UL << qp->timeout)) / 1000UL);
  57. add_timer(&qp->s_timer);
  58. }
  59. /**
  60. * qib_make_rc_ack - construct a response packet (ACK, NAK, or RDMA read)
  61. * @dev: the device for this QP
  62. * @qp: a pointer to the QP
  63. * @ohdr: a pointer to the IB header being constructed
  64. * @pmtu: the path MTU
  65. *
  66. * Return 1 if constructed; otherwise, return 0.
  67. * Note that we are in the responder's side of the QP context.
  68. * Note the QP s_lock must be held.
  69. */
  70. static int qib_make_rc_ack(struct qib_ibdev *dev, struct qib_qp *qp,
  71. struct qib_other_headers *ohdr, u32 pmtu)
  72. {
  73. struct qib_ack_entry *e;
  74. u32 hwords;
  75. u32 len;
  76. u32 bth0;
  77. u32 bth2;
  78. /* Don't send an ACK if we aren't supposed to. */
  79. if (!(ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK))
  80. goto bail;
  81. /* header size in 32-bit words LRH+BTH = (8+12)/4. */
  82. hwords = 5;
  83. switch (qp->s_ack_state) {
  84. case OP(RDMA_READ_RESPONSE_LAST):
  85. case OP(RDMA_READ_RESPONSE_ONLY):
  86. e = &qp->s_ack_queue[qp->s_tail_ack_queue];
  87. if (e->rdma_sge.mr) {
  88. atomic_dec(&e->rdma_sge.mr->refcount);
  89. e->rdma_sge.mr = NULL;
  90. }
  91. /* FALLTHROUGH */
  92. case OP(ATOMIC_ACKNOWLEDGE):
  93. /*
  94. * We can increment the tail pointer now that the last
  95. * response has been sent instead of only being
  96. * constructed.
  97. */
  98. if (++qp->s_tail_ack_queue > QIB_MAX_RDMA_ATOMIC)
  99. qp->s_tail_ack_queue = 0;
  100. /* FALLTHROUGH */
  101. case OP(SEND_ONLY):
  102. case OP(ACKNOWLEDGE):
  103. /* Check for no next entry in the queue. */
  104. if (qp->r_head_ack_queue == qp->s_tail_ack_queue) {
  105. if (qp->s_flags & QIB_S_ACK_PENDING)
  106. goto normal;
  107. goto bail;
  108. }
  109. e = &qp->s_ack_queue[qp->s_tail_ack_queue];
  110. if (e->opcode == OP(RDMA_READ_REQUEST)) {
  111. /*
  112. * If a RDMA read response is being resent and
  113. * we haven't seen the duplicate request yet,
  114. * then stop sending the remaining responses the
  115. * responder has seen until the requester resends it.
  116. */
  117. len = e->rdma_sge.sge_length;
  118. if (len && !e->rdma_sge.mr) {
  119. qp->s_tail_ack_queue = qp->r_head_ack_queue;
  120. goto bail;
  121. }
  122. /* Copy SGE state in case we need to resend */
  123. qp->s_rdma_mr = e->rdma_sge.mr;
  124. if (qp->s_rdma_mr)
  125. atomic_inc(&qp->s_rdma_mr->refcount);
  126. qp->s_ack_rdma_sge.sge = e->rdma_sge;
  127. qp->s_ack_rdma_sge.num_sge = 1;
  128. qp->s_cur_sge = &qp->s_ack_rdma_sge;
  129. if (len > pmtu) {
  130. len = pmtu;
  131. qp->s_ack_state = OP(RDMA_READ_RESPONSE_FIRST);
  132. } else {
  133. qp->s_ack_state = OP(RDMA_READ_RESPONSE_ONLY);
  134. e->sent = 1;
  135. }
  136. ohdr->u.aeth = qib_compute_aeth(qp);
  137. hwords++;
  138. qp->s_ack_rdma_psn = e->psn;
  139. bth2 = qp->s_ack_rdma_psn++ & QIB_PSN_MASK;
  140. } else {
  141. /* COMPARE_SWAP or FETCH_ADD */
  142. qp->s_cur_sge = NULL;
  143. len = 0;
  144. qp->s_ack_state = OP(ATOMIC_ACKNOWLEDGE);
  145. ohdr->u.at.aeth = qib_compute_aeth(qp);
  146. ohdr->u.at.atomic_ack_eth[0] =
  147. cpu_to_be32(e->atomic_data >> 32);
  148. ohdr->u.at.atomic_ack_eth[1] =
  149. cpu_to_be32(e->atomic_data);
  150. hwords += sizeof(ohdr->u.at) / sizeof(u32);
  151. bth2 = e->psn & QIB_PSN_MASK;
  152. e->sent = 1;
  153. }
  154. bth0 = qp->s_ack_state << 24;
  155. break;
  156. case OP(RDMA_READ_RESPONSE_FIRST):
  157. qp->s_ack_state = OP(RDMA_READ_RESPONSE_MIDDLE);
  158. /* FALLTHROUGH */
  159. case OP(RDMA_READ_RESPONSE_MIDDLE):
  160. qp->s_cur_sge = &qp->s_ack_rdma_sge;
  161. qp->s_rdma_mr = qp->s_ack_rdma_sge.sge.mr;
  162. if (qp->s_rdma_mr)
  163. atomic_inc(&qp->s_rdma_mr->refcount);
  164. len = qp->s_ack_rdma_sge.sge.sge_length;
  165. if (len > pmtu)
  166. len = pmtu;
  167. else {
  168. ohdr->u.aeth = qib_compute_aeth(qp);
  169. hwords++;
  170. qp->s_ack_state = OP(RDMA_READ_RESPONSE_LAST);
  171. e = &qp->s_ack_queue[qp->s_tail_ack_queue];
  172. e->sent = 1;
  173. }
  174. bth0 = qp->s_ack_state << 24;
  175. bth2 = qp->s_ack_rdma_psn++ & QIB_PSN_MASK;
  176. break;
  177. default:
  178. normal:
  179. /*
  180. * Send a regular ACK.
  181. * Set the s_ack_state so we wait until after sending
  182. * the ACK before setting s_ack_state to ACKNOWLEDGE
  183. * (see above).
  184. */
  185. qp->s_ack_state = OP(SEND_ONLY);
  186. qp->s_flags &= ~QIB_S_ACK_PENDING;
  187. qp->s_cur_sge = NULL;
  188. if (qp->s_nak_state)
  189. ohdr->u.aeth =
  190. cpu_to_be32((qp->r_msn & QIB_MSN_MASK) |
  191. (qp->s_nak_state <<
  192. QIB_AETH_CREDIT_SHIFT));
  193. else
  194. ohdr->u.aeth = qib_compute_aeth(qp);
  195. hwords++;
  196. len = 0;
  197. bth0 = OP(ACKNOWLEDGE) << 24;
  198. bth2 = qp->s_ack_psn & QIB_PSN_MASK;
  199. }
  200. qp->s_rdma_ack_cnt++;
  201. qp->s_hdrwords = hwords;
  202. qp->s_cur_size = len;
  203. qib_make_ruc_header(qp, ohdr, bth0, bth2);
  204. return 1;
  205. bail:
  206. qp->s_ack_state = OP(ACKNOWLEDGE);
  207. qp->s_flags &= ~(QIB_S_RESP_PENDING | QIB_S_ACK_PENDING);
  208. return 0;
  209. }
  210. /**
  211. * qib_make_rc_req - construct a request packet (SEND, RDMA r/w, ATOMIC)
  212. * @qp: a pointer to the QP
  213. *
  214. * Return 1 if constructed; otherwise, return 0.
  215. */
  216. int qib_make_rc_req(struct qib_qp *qp)
  217. {
  218. struct qib_ibdev *dev = to_idev(qp->ibqp.device);
  219. struct qib_other_headers *ohdr;
  220. struct qib_sge_state *ss;
  221. struct qib_swqe *wqe;
  222. u32 hwords;
  223. u32 len;
  224. u32 bth0;
  225. u32 bth2;
  226. u32 pmtu = ib_mtu_enum_to_int(qp->path_mtu);
  227. char newreq;
  228. unsigned long flags;
  229. int ret = 0;
  230. int delta;
  231. ohdr = &qp->s_hdr.u.oth;
  232. if (qp->remote_ah_attr.ah_flags & IB_AH_GRH)
  233. ohdr = &qp->s_hdr.u.l.oth;
  234. /*
  235. * The lock is needed to synchronize between the sending tasklet,
  236. * the receive interrupt handler, and timeout resends.
  237. */
  238. spin_lock_irqsave(&qp->s_lock, flags);
  239. /* Sending responses has higher priority over sending requests. */
  240. if ((qp->s_flags & QIB_S_RESP_PENDING) &&
  241. qib_make_rc_ack(dev, qp, ohdr, pmtu))
  242. goto done;
  243. if (!(ib_qib_state_ops[qp->state] & QIB_PROCESS_SEND_OK)) {
  244. if (!(ib_qib_state_ops[qp->state] & QIB_FLUSH_SEND))
  245. goto bail;
  246. /* We are in the error state, flush the work request. */
  247. if (qp->s_last == qp->s_head)
  248. goto bail;
  249. /* If DMAs are in progress, we can't flush immediately. */
  250. if (atomic_read(&qp->s_dma_busy)) {
  251. qp->s_flags |= QIB_S_WAIT_DMA;
  252. goto bail;
  253. }
  254. wqe = get_swqe_ptr(qp, qp->s_last);
  255. while (qp->s_last != qp->s_acked) {
  256. qib_send_complete(qp, wqe, IB_WC_SUCCESS);
  257. if (++qp->s_last >= qp->s_size)
  258. qp->s_last = 0;
  259. wqe = get_swqe_ptr(qp, qp->s_last);
  260. }
  261. qib_send_complete(qp, wqe, IB_WC_WR_FLUSH_ERR);
  262. goto done;
  263. }
  264. if (qp->s_flags & (QIB_S_WAIT_RNR | QIB_S_WAIT_ACK))
  265. goto bail;
  266. if (qib_cmp24(qp->s_psn, qp->s_sending_hpsn) <= 0) {
  267. if (qib_cmp24(qp->s_sending_psn, qp->s_sending_hpsn) <= 0) {
  268. qp->s_flags |= QIB_S_WAIT_PSN;
  269. goto bail;
  270. }
  271. qp->s_sending_psn = qp->s_psn;
  272. qp->s_sending_hpsn = qp->s_psn - 1;
  273. }
  274. /* header size in 32-bit words LRH+BTH = (8+12)/4. */
  275. hwords = 5;
  276. bth0 = 0;
  277. /* Send a request. */
  278. wqe = get_swqe_ptr(qp, qp->s_cur);
  279. switch (qp->s_state) {
  280. default:
  281. if (!(ib_qib_state_ops[qp->state] & QIB_PROCESS_NEXT_SEND_OK))
  282. goto bail;
  283. /*
  284. * Resend an old request or start a new one.
  285. *
  286. * We keep track of the current SWQE so that
  287. * we don't reset the "furthest progress" state
  288. * if we need to back up.
  289. */
  290. newreq = 0;
  291. if (qp->s_cur == qp->s_tail) {
  292. /* Check if send work queue is empty. */
  293. if (qp->s_tail == qp->s_head)
  294. goto bail;
  295. /*
  296. * If a fence is requested, wait for previous
  297. * RDMA read and atomic operations to finish.
  298. */
  299. if ((wqe->wr.send_flags & IB_SEND_FENCE) &&
  300. qp->s_num_rd_atomic) {
  301. qp->s_flags |= QIB_S_WAIT_FENCE;
  302. goto bail;
  303. }
  304. wqe->psn = qp->s_next_psn;
  305. newreq = 1;
  306. }
  307. /*
  308. * Note that we have to be careful not to modify the
  309. * original work request since we may need to resend
  310. * it.
  311. */
  312. len = wqe->length;
  313. ss = &qp->s_sge;
  314. bth2 = qp->s_psn & QIB_PSN_MASK;
  315. switch (wqe->wr.opcode) {
  316. case IB_WR_SEND:
  317. case IB_WR_SEND_WITH_IMM:
  318. /* If no credit, return. */
  319. if (!(qp->s_flags & QIB_S_UNLIMITED_CREDIT) &&
  320. qib_cmp24(wqe->ssn, qp->s_lsn + 1) > 0) {
  321. qp->s_flags |= QIB_S_WAIT_SSN_CREDIT;
  322. goto bail;
  323. }
  324. wqe->lpsn = wqe->psn;
  325. if (len > pmtu) {
  326. wqe->lpsn += (len - 1) / pmtu;
  327. qp->s_state = OP(SEND_FIRST);
  328. len = pmtu;
  329. break;
  330. }
  331. if (wqe->wr.opcode == IB_WR_SEND)
  332. qp->s_state = OP(SEND_ONLY);
  333. else {
  334. qp->s_state = OP(SEND_ONLY_WITH_IMMEDIATE);
  335. /* Immediate data comes after the BTH */
  336. ohdr->u.imm_data = wqe->wr.ex.imm_data;
  337. hwords += 1;
  338. }
  339. if (wqe->wr.send_flags & IB_SEND_SOLICITED)
  340. bth0 |= IB_BTH_SOLICITED;
  341. bth2 |= IB_BTH_REQ_ACK;
  342. if (++qp->s_cur == qp->s_size)
  343. qp->s_cur = 0;
  344. break;
  345. case IB_WR_RDMA_WRITE:
  346. if (newreq && !(qp->s_flags & QIB_S_UNLIMITED_CREDIT))
  347. qp->s_lsn++;
  348. /* FALLTHROUGH */
  349. case IB_WR_RDMA_WRITE_WITH_IMM:
  350. /* If no credit, return. */
  351. if (!(qp->s_flags & QIB_S_UNLIMITED_CREDIT) &&
  352. qib_cmp24(wqe->ssn, qp->s_lsn + 1) > 0) {
  353. qp->s_flags |= QIB_S_WAIT_SSN_CREDIT;
  354. goto bail;
  355. }
  356. ohdr->u.rc.reth.vaddr =
  357. cpu_to_be64(wqe->wr.wr.rdma.remote_addr);
  358. ohdr->u.rc.reth.rkey =
  359. cpu_to_be32(wqe->wr.wr.rdma.rkey);
  360. ohdr->u.rc.reth.length = cpu_to_be32(len);
  361. hwords += sizeof(struct ib_reth) / sizeof(u32);
  362. wqe->lpsn = wqe->psn;
  363. if (len > pmtu) {
  364. wqe->lpsn += (len - 1) / pmtu;
  365. qp->s_state = OP(RDMA_WRITE_FIRST);
  366. len = pmtu;
  367. break;
  368. }
  369. if (wqe->wr.opcode == IB_WR_RDMA_WRITE)
  370. qp->s_state = OP(RDMA_WRITE_ONLY);
  371. else {
  372. qp->s_state =
  373. OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE);
  374. /* Immediate data comes after RETH */
  375. ohdr->u.rc.imm_data = wqe->wr.ex.imm_data;
  376. hwords += 1;
  377. if (wqe->wr.send_flags & IB_SEND_SOLICITED)
  378. bth0 |= IB_BTH_SOLICITED;
  379. }
  380. bth2 |= IB_BTH_REQ_ACK;
  381. if (++qp->s_cur == qp->s_size)
  382. qp->s_cur = 0;
  383. break;
  384. case IB_WR_RDMA_READ:
  385. /*
  386. * Don't allow more operations to be started
  387. * than the QP limits allow.
  388. */
  389. if (newreq) {
  390. if (qp->s_num_rd_atomic >=
  391. qp->s_max_rd_atomic) {
  392. qp->s_flags |= QIB_S_WAIT_RDMAR;
  393. goto bail;
  394. }
  395. qp->s_num_rd_atomic++;
  396. if (!(qp->s_flags & QIB_S_UNLIMITED_CREDIT))
  397. qp->s_lsn++;
  398. /*
  399. * Adjust s_next_psn to count the
  400. * expected number of responses.
  401. */
  402. if (len > pmtu)
  403. qp->s_next_psn += (len - 1) / pmtu;
  404. wqe->lpsn = qp->s_next_psn++;
  405. }
  406. ohdr->u.rc.reth.vaddr =
  407. cpu_to_be64(wqe->wr.wr.rdma.remote_addr);
  408. ohdr->u.rc.reth.rkey =
  409. cpu_to_be32(wqe->wr.wr.rdma.rkey);
  410. ohdr->u.rc.reth.length = cpu_to_be32(len);
  411. qp->s_state = OP(RDMA_READ_REQUEST);
  412. hwords += sizeof(ohdr->u.rc.reth) / sizeof(u32);
  413. ss = NULL;
  414. len = 0;
  415. bth2 |= IB_BTH_REQ_ACK;
  416. if (++qp->s_cur == qp->s_size)
  417. qp->s_cur = 0;
  418. break;
  419. case IB_WR_ATOMIC_CMP_AND_SWP:
  420. case IB_WR_ATOMIC_FETCH_AND_ADD:
  421. /*
  422. * Don't allow more operations to be started
  423. * than the QP limits allow.
  424. */
  425. if (newreq) {
  426. if (qp->s_num_rd_atomic >=
  427. qp->s_max_rd_atomic) {
  428. qp->s_flags |= QIB_S_WAIT_RDMAR;
  429. goto bail;
  430. }
  431. qp->s_num_rd_atomic++;
  432. if (!(qp->s_flags & QIB_S_UNLIMITED_CREDIT))
  433. qp->s_lsn++;
  434. wqe->lpsn = wqe->psn;
  435. }
  436. if (wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
  437. qp->s_state = OP(COMPARE_SWAP);
  438. ohdr->u.atomic_eth.swap_data = cpu_to_be64(
  439. wqe->wr.wr.atomic.swap);
  440. ohdr->u.atomic_eth.compare_data = cpu_to_be64(
  441. wqe->wr.wr.atomic.compare_add);
  442. } else {
  443. qp->s_state = OP(FETCH_ADD);
  444. ohdr->u.atomic_eth.swap_data = cpu_to_be64(
  445. wqe->wr.wr.atomic.compare_add);
  446. ohdr->u.atomic_eth.compare_data = 0;
  447. }
  448. ohdr->u.atomic_eth.vaddr[0] = cpu_to_be32(
  449. wqe->wr.wr.atomic.remote_addr >> 32);
  450. ohdr->u.atomic_eth.vaddr[1] = cpu_to_be32(
  451. wqe->wr.wr.atomic.remote_addr);
  452. ohdr->u.atomic_eth.rkey = cpu_to_be32(
  453. wqe->wr.wr.atomic.rkey);
  454. hwords += sizeof(struct ib_atomic_eth) / sizeof(u32);
  455. ss = NULL;
  456. len = 0;
  457. bth2 |= IB_BTH_REQ_ACK;
  458. if (++qp->s_cur == qp->s_size)
  459. qp->s_cur = 0;
  460. break;
  461. default:
  462. goto bail;
  463. }
  464. qp->s_sge.sge = wqe->sg_list[0];
  465. qp->s_sge.sg_list = wqe->sg_list + 1;
  466. qp->s_sge.num_sge = wqe->wr.num_sge;
  467. qp->s_sge.total_len = wqe->length;
  468. qp->s_len = wqe->length;
  469. if (newreq) {
  470. qp->s_tail++;
  471. if (qp->s_tail >= qp->s_size)
  472. qp->s_tail = 0;
  473. }
  474. if (wqe->wr.opcode == IB_WR_RDMA_READ)
  475. qp->s_psn = wqe->lpsn + 1;
  476. else {
  477. qp->s_psn++;
  478. if (qib_cmp24(qp->s_psn, qp->s_next_psn) > 0)
  479. qp->s_next_psn = qp->s_psn;
  480. }
  481. break;
  482. case OP(RDMA_READ_RESPONSE_FIRST):
  483. /*
  484. * qp->s_state is normally set to the opcode of the
  485. * last packet constructed for new requests and therefore
  486. * is never set to RDMA read response.
  487. * RDMA_READ_RESPONSE_FIRST is used by the ACK processing
  488. * thread to indicate a SEND needs to be restarted from an
  489. * earlier PSN without interferring with the sending thread.
  490. * See qib_restart_rc().
  491. */
  492. qp->s_len = restart_sge(&qp->s_sge, wqe, qp->s_psn, pmtu);
  493. /* FALLTHROUGH */
  494. case OP(SEND_FIRST):
  495. qp->s_state = OP(SEND_MIDDLE);
  496. /* FALLTHROUGH */
  497. case OP(SEND_MIDDLE):
  498. bth2 = qp->s_psn++ & QIB_PSN_MASK;
  499. if (qib_cmp24(qp->s_psn, qp->s_next_psn) > 0)
  500. qp->s_next_psn = qp->s_psn;
  501. ss = &qp->s_sge;
  502. len = qp->s_len;
  503. if (len > pmtu) {
  504. len = pmtu;
  505. break;
  506. }
  507. if (wqe->wr.opcode == IB_WR_SEND)
  508. qp->s_state = OP(SEND_LAST);
  509. else {
  510. qp->s_state = OP(SEND_LAST_WITH_IMMEDIATE);
  511. /* Immediate data comes after the BTH */
  512. ohdr->u.imm_data = wqe->wr.ex.imm_data;
  513. hwords += 1;
  514. }
  515. if (wqe->wr.send_flags & IB_SEND_SOLICITED)
  516. bth0 |= IB_BTH_SOLICITED;
  517. bth2 |= IB_BTH_REQ_ACK;
  518. qp->s_cur++;
  519. if (qp->s_cur >= qp->s_size)
  520. qp->s_cur = 0;
  521. break;
  522. case OP(RDMA_READ_RESPONSE_LAST):
  523. /*
  524. * qp->s_state is normally set to the opcode of the
  525. * last packet constructed for new requests and therefore
  526. * is never set to RDMA read response.
  527. * RDMA_READ_RESPONSE_LAST is used by the ACK processing
  528. * thread to indicate a RDMA write needs to be restarted from
  529. * an earlier PSN without interferring with the sending thread.
  530. * See qib_restart_rc().
  531. */
  532. qp->s_len = restart_sge(&qp->s_sge, wqe, qp->s_psn, pmtu);
  533. /* FALLTHROUGH */
  534. case OP(RDMA_WRITE_FIRST):
  535. qp->s_state = OP(RDMA_WRITE_MIDDLE);
  536. /* FALLTHROUGH */
  537. case OP(RDMA_WRITE_MIDDLE):
  538. bth2 = qp->s_psn++ & QIB_PSN_MASK;
  539. if (qib_cmp24(qp->s_psn, qp->s_next_psn) > 0)
  540. qp->s_next_psn = qp->s_psn;
  541. ss = &qp->s_sge;
  542. len = qp->s_len;
  543. if (len > pmtu) {
  544. len = pmtu;
  545. break;
  546. }
  547. if (wqe->wr.opcode == IB_WR_RDMA_WRITE)
  548. qp->s_state = OP(RDMA_WRITE_LAST);
  549. else {
  550. qp->s_state = OP(RDMA_WRITE_LAST_WITH_IMMEDIATE);
  551. /* Immediate data comes after the BTH */
  552. ohdr->u.imm_data = wqe->wr.ex.imm_data;
  553. hwords += 1;
  554. if (wqe->wr.send_flags & IB_SEND_SOLICITED)
  555. bth0 |= IB_BTH_SOLICITED;
  556. }
  557. bth2 |= IB_BTH_REQ_ACK;
  558. qp->s_cur++;
  559. if (qp->s_cur >= qp->s_size)
  560. qp->s_cur = 0;
  561. break;
  562. case OP(RDMA_READ_RESPONSE_MIDDLE):
  563. /*
  564. * qp->s_state is normally set to the opcode of the
  565. * last packet constructed for new requests and therefore
  566. * is never set to RDMA read response.
  567. * RDMA_READ_RESPONSE_MIDDLE is used by the ACK processing
  568. * thread to indicate a RDMA read needs to be restarted from
  569. * an earlier PSN without interferring with the sending thread.
  570. * See qib_restart_rc().
  571. */
  572. len = ((qp->s_psn - wqe->psn) & QIB_PSN_MASK) * pmtu;
  573. ohdr->u.rc.reth.vaddr =
  574. cpu_to_be64(wqe->wr.wr.rdma.remote_addr + len);
  575. ohdr->u.rc.reth.rkey =
  576. cpu_to_be32(wqe->wr.wr.rdma.rkey);
  577. ohdr->u.rc.reth.length = cpu_to_be32(wqe->length - len);
  578. qp->s_state = OP(RDMA_READ_REQUEST);
  579. hwords += sizeof(ohdr->u.rc.reth) / sizeof(u32);
  580. bth2 = (qp->s_psn & QIB_PSN_MASK) | IB_BTH_REQ_ACK;
  581. qp->s_psn = wqe->lpsn + 1;
  582. ss = NULL;
  583. len = 0;
  584. qp->s_cur++;
  585. if (qp->s_cur == qp->s_size)
  586. qp->s_cur = 0;
  587. break;
  588. }
  589. qp->s_sending_hpsn = bth2;
  590. delta = (((int) bth2 - (int) wqe->psn) << 8) >> 8;
  591. if (delta && delta % QIB_PSN_CREDIT == 0)
  592. bth2 |= IB_BTH_REQ_ACK;
  593. if (qp->s_flags & QIB_S_SEND_ONE) {
  594. qp->s_flags &= ~QIB_S_SEND_ONE;
  595. qp->s_flags |= QIB_S_WAIT_ACK;
  596. bth2 |= IB_BTH_REQ_ACK;
  597. }
  598. qp->s_len -= len;
  599. qp->s_hdrwords = hwords;
  600. qp->s_cur_sge = ss;
  601. qp->s_cur_size = len;
  602. qib_make_ruc_header(qp, ohdr, bth0 | (qp->s_state << 24), bth2);
  603. done:
  604. ret = 1;
  605. goto unlock;
  606. bail:
  607. qp->s_flags &= ~QIB_S_BUSY;
  608. unlock:
  609. spin_unlock_irqrestore(&qp->s_lock, flags);
  610. return ret;
  611. }
  612. /**
  613. * qib_send_rc_ack - Construct an ACK packet and send it
  614. * @qp: a pointer to the QP
  615. *
  616. * This is called from qib_rc_rcv() and qib_kreceive().
  617. * Note that RDMA reads and atomics are handled in the
  618. * send side QP state and tasklet.
  619. */
  620. void qib_send_rc_ack(struct qib_qp *qp)
  621. {
  622. struct qib_devdata *dd = dd_from_ibdev(qp->ibqp.device);
  623. struct qib_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
  624. struct qib_pportdata *ppd = ppd_from_ibp(ibp);
  625. u64 pbc;
  626. u16 lrh0;
  627. u32 bth0;
  628. u32 hwords;
  629. u32 pbufn;
  630. u32 __iomem *piobuf;
  631. struct qib_ib_header hdr;
  632. struct qib_other_headers *ohdr;
  633. u32 control;
  634. unsigned long flags;
  635. spin_lock_irqsave(&qp->s_lock, flags);
  636. if (!(ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK))
  637. goto unlock;
  638. /* Don't send ACK or NAK if a RDMA read or atomic is pending. */
  639. if ((qp->s_flags & QIB_S_RESP_PENDING) || qp->s_rdma_ack_cnt)
  640. goto queue_ack;
  641. /* Construct the header with s_lock held so APM doesn't change it. */
  642. ohdr = &hdr.u.oth;
  643. lrh0 = QIB_LRH_BTH;
  644. /* header size in 32-bit words LRH+BTH+AETH = (8+12+4)/4. */
  645. hwords = 6;
  646. if (unlikely(qp->remote_ah_attr.ah_flags & IB_AH_GRH)) {
  647. hwords += qib_make_grh(ibp, &hdr.u.l.grh,
  648. &qp->remote_ah_attr.grh, hwords, 0);
  649. ohdr = &hdr.u.l.oth;
  650. lrh0 = QIB_LRH_GRH;
  651. }
  652. /* read pkey_index w/o lock (its atomic) */
  653. bth0 = qib_get_pkey(ibp, qp->s_pkey_index) | (OP(ACKNOWLEDGE) << 24);
  654. if (qp->s_mig_state == IB_MIG_MIGRATED)
  655. bth0 |= IB_BTH_MIG_REQ;
  656. if (qp->r_nak_state)
  657. ohdr->u.aeth = cpu_to_be32((qp->r_msn & QIB_MSN_MASK) |
  658. (qp->r_nak_state <<
  659. QIB_AETH_CREDIT_SHIFT));
  660. else
  661. ohdr->u.aeth = qib_compute_aeth(qp);
  662. lrh0 |= ibp->sl_to_vl[qp->remote_ah_attr.sl] << 12 |
  663. qp->remote_ah_attr.sl << 4;
  664. hdr.lrh[0] = cpu_to_be16(lrh0);
  665. hdr.lrh[1] = cpu_to_be16(qp->remote_ah_attr.dlid);
  666. hdr.lrh[2] = cpu_to_be16(hwords + SIZE_OF_CRC);
  667. hdr.lrh[3] = cpu_to_be16(ppd->lid | qp->remote_ah_attr.src_path_bits);
  668. ohdr->bth[0] = cpu_to_be32(bth0);
  669. ohdr->bth[1] = cpu_to_be32(qp->remote_qpn);
  670. ohdr->bth[2] = cpu_to_be32(qp->r_ack_psn & QIB_PSN_MASK);
  671. spin_unlock_irqrestore(&qp->s_lock, flags);
  672. /* Don't try to send ACKs if the link isn't ACTIVE */
  673. if (!(ppd->lflags & QIBL_LINKACTIVE))
  674. goto done;
  675. control = dd->f_setpbc_control(ppd, hwords + SIZE_OF_CRC,
  676. qp->s_srate, lrh0 >> 12);
  677. /* length is + 1 for the control dword */
  678. pbc = ((u64) control << 32) | (hwords + 1);
  679. piobuf = dd->f_getsendbuf(ppd, pbc, &pbufn);
  680. if (!piobuf) {
  681. /*
  682. * We are out of PIO buffers at the moment.
  683. * Pass responsibility for sending the ACK to the
  684. * send tasklet so that when a PIO buffer becomes
  685. * available, the ACK is sent ahead of other outgoing
  686. * packets.
  687. */
  688. spin_lock_irqsave(&qp->s_lock, flags);
  689. goto queue_ack;
  690. }
  691. /*
  692. * Write the pbc.
  693. * We have to flush after the PBC for correctness
  694. * on some cpus or WC buffer can be written out of order.
  695. */
  696. writeq(pbc, piobuf);
  697. if (dd->flags & QIB_PIO_FLUSH_WC) {
  698. u32 *hdrp = (u32 *) &hdr;
  699. qib_flush_wc();
  700. qib_pio_copy(piobuf + 2, hdrp, hwords - 1);
  701. qib_flush_wc();
  702. __raw_writel(hdrp[hwords - 1], piobuf + hwords + 1);
  703. } else
  704. qib_pio_copy(piobuf + 2, (u32 *) &hdr, hwords);
  705. if (dd->flags & QIB_USE_SPCL_TRIG) {
  706. u32 spcl_off = (pbufn >= dd->piobcnt2k) ? 2047 : 1023;
  707. qib_flush_wc();
  708. __raw_writel(0xaebecede, piobuf + spcl_off);
  709. }
  710. qib_flush_wc();
  711. qib_sendbuf_done(dd, pbufn);
  712. ibp->n_unicast_xmit++;
  713. goto done;
  714. queue_ack:
  715. if (ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK) {
  716. ibp->n_rc_qacks++;
  717. qp->s_flags |= QIB_S_ACK_PENDING | QIB_S_RESP_PENDING;
  718. qp->s_nak_state = qp->r_nak_state;
  719. qp->s_ack_psn = qp->r_ack_psn;
  720. /* Schedule the send tasklet. */
  721. qib_schedule_send(qp);
  722. }
  723. unlock:
  724. spin_unlock_irqrestore(&qp->s_lock, flags);
  725. done:
  726. return;
  727. }
  728. /**
  729. * reset_psn - reset the QP state to send starting from PSN
  730. * @qp: the QP
  731. * @psn: the packet sequence number to restart at
  732. *
  733. * This is called from qib_rc_rcv() to process an incoming RC ACK
  734. * for the given QP.
  735. * Called at interrupt level with the QP s_lock held.
  736. */
  737. static void reset_psn(struct qib_qp *qp, u32 psn)
  738. {
  739. u32 n = qp->s_acked;
  740. struct qib_swqe *wqe = get_swqe_ptr(qp, n);
  741. u32 opcode;
  742. qp->s_cur = n;
  743. /*
  744. * If we are starting the request from the beginning,
  745. * let the normal send code handle initialization.
  746. */
  747. if (qib_cmp24(psn, wqe->psn) <= 0) {
  748. qp->s_state = OP(SEND_LAST);
  749. goto done;
  750. }
  751. /* Find the work request opcode corresponding to the given PSN. */
  752. opcode = wqe->wr.opcode;
  753. for (;;) {
  754. int diff;
  755. if (++n == qp->s_size)
  756. n = 0;
  757. if (n == qp->s_tail)
  758. break;
  759. wqe = get_swqe_ptr(qp, n);
  760. diff = qib_cmp24(psn, wqe->psn);
  761. if (diff < 0)
  762. break;
  763. qp->s_cur = n;
  764. /*
  765. * If we are starting the request from the beginning,
  766. * let the normal send code handle initialization.
  767. */
  768. if (diff == 0) {
  769. qp->s_state = OP(SEND_LAST);
  770. goto done;
  771. }
  772. opcode = wqe->wr.opcode;
  773. }
  774. /*
  775. * Set the state to restart in the middle of a request.
  776. * Don't change the s_sge, s_cur_sge, or s_cur_size.
  777. * See qib_make_rc_req().
  778. */
  779. switch (opcode) {
  780. case IB_WR_SEND:
  781. case IB_WR_SEND_WITH_IMM:
  782. qp->s_state = OP(RDMA_READ_RESPONSE_FIRST);
  783. break;
  784. case IB_WR_RDMA_WRITE:
  785. case IB_WR_RDMA_WRITE_WITH_IMM:
  786. qp->s_state = OP(RDMA_READ_RESPONSE_LAST);
  787. break;
  788. case IB_WR_RDMA_READ:
  789. qp->s_state = OP(RDMA_READ_RESPONSE_MIDDLE);
  790. break;
  791. default:
  792. /*
  793. * This case shouldn't happen since its only
  794. * one PSN per req.
  795. */
  796. qp->s_state = OP(SEND_LAST);
  797. }
  798. done:
  799. qp->s_psn = psn;
  800. /*
  801. * Set QIB_S_WAIT_PSN as qib_rc_complete() may start the timer
  802. * asynchronously before the send tasklet can get scheduled.
  803. * Doing it in qib_make_rc_req() is too late.
  804. */
  805. if ((qib_cmp24(qp->s_psn, qp->s_sending_hpsn) <= 0) &&
  806. (qib_cmp24(qp->s_sending_psn, qp->s_sending_hpsn) <= 0))
  807. qp->s_flags |= QIB_S_WAIT_PSN;
  808. }
  809. /*
  810. * Back up requester to resend the last un-ACKed request.
  811. * The QP r_lock and s_lock should be held and interrupts disabled.
  812. */
  813. static void qib_restart_rc(struct qib_qp *qp, u32 psn, int wait)
  814. {
  815. struct qib_swqe *wqe = get_swqe_ptr(qp, qp->s_acked);
  816. struct qib_ibport *ibp;
  817. if (qp->s_retry == 0) {
  818. if (qp->s_mig_state == IB_MIG_ARMED) {
  819. qib_migrate_qp(qp);
  820. qp->s_retry = qp->s_retry_cnt;
  821. } else if (qp->s_last == qp->s_acked) {
  822. qib_send_complete(qp, wqe, IB_WC_RETRY_EXC_ERR);
  823. qib_error_qp(qp, IB_WC_WR_FLUSH_ERR);
  824. return;
  825. } else /* XXX need to handle delayed completion */
  826. return;
  827. } else
  828. qp->s_retry--;
  829. ibp = to_iport(qp->ibqp.device, qp->port_num);
  830. if (wqe->wr.opcode == IB_WR_RDMA_READ)
  831. ibp->n_rc_resends++;
  832. else
  833. ibp->n_rc_resends += (qp->s_psn - psn) & QIB_PSN_MASK;
  834. qp->s_flags &= ~(QIB_S_WAIT_FENCE | QIB_S_WAIT_RDMAR |
  835. QIB_S_WAIT_SSN_CREDIT | QIB_S_WAIT_PSN |
  836. QIB_S_WAIT_ACK);
  837. if (wait)
  838. qp->s_flags |= QIB_S_SEND_ONE;
  839. reset_psn(qp, psn);
  840. }
  841. /*
  842. * This is called from s_timer for missing responses.
  843. */
  844. static void rc_timeout(unsigned long arg)
  845. {
  846. struct qib_qp *qp = (struct qib_qp *)arg;
  847. struct qib_ibport *ibp;
  848. unsigned long flags;
  849. spin_lock_irqsave(&qp->r_lock, flags);
  850. spin_lock(&qp->s_lock);
  851. if (qp->s_flags & QIB_S_TIMER) {
  852. ibp = to_iport(qp->ibqp.device, qp->port_num);
  853. ibp->n_rc_timeouts++;
  854. qp->s_flags &= ~QIB_S_TIMER;
  855. del_timer(&qp->s_timer);
  856. qib_restart_rc(qp, qp->s_last_psn + 1, 1);
  857. qib_schedule_send(qp);
  858. }
  859. spin_unlock(&qp->s_lock);
  860. spin_unlock_irqrestore(&qp->r_lock, flags);
  861. }
  862. /*
  863. * This is called from s_timer for RNR timeouts.
  864. */
  865. void qib_rc_rnr_retry(unsigned long arg)
  866. {
  867. struct qib_qp *qp = (struct qib_qp *)arg;
  868. unsigned long flags;
  869. spin_lock_irqsave(&qp->s_lock, flags);
  870. if (qp->s_flags & QIB_S_WAIT_RNR) {
  871. qp->s_flags &= ~QIB_S_WAIT_RNR;
  872. del_timer(&qp->s_timer);
  873. qib_schedule_send(qp);
  874. }
  875. spin_unlock_irqrestore(&qp->s_lock, flags);
  876. }
  877. /*
  878. * Set qp->s_sending_psn to the next PSN after the given one.
  879. * This would be psn+1 except when RDMA reads are present.
  880. */
  881. static void reset_sending_psn(struct qib_qp *qp, u32 psn)
  882. {
  883. struct qib_swqe *wqe;
  884. u32 n = qp->s_last;
  885. /* Find the work request corresponding to the given PSN. */
  886. for (;;) {
  887. wqe = get_swqe_ptr(qp, n);
  888. if (qib_cmp24(psn, wqe->lpsn) <= 0) {
  889. if (wqe->wr.opcode == IB_WR_RDMA_READ)
  890. qp->s_sending_psn = wqe->lpsn + 1;
  891. else
  892. qp->s_sending_psn = psn + 1;
  893. break;
  894. }
  895. if (++n == qp->s_size)
  896. n = 0;
  897. if (n == qp->s_tail)
  898. break;
  899. }
  900. }
  901. /*
  902. * This should be called with the QP s_lock held and interrupts disabled.
  903. */
  904. void qib_rc_send_complete(struct qib_qp *qp, struct qib_ib_header *hdr)
  905. {
  906. struct qib_other_headers *ohdr;
  907. struct qib_swqe *wqe;
  908. struct ib_wc wc;
  909. unsigned i;
  910. u32 opcode;
  911. u32 psn;
  912. if (!(ib_qib_state_ops[qp->state] & QIB_PROCESS_OR_FLUSH_SEND))
  913. return;
  914. /* Find out where the BTH is */
  915. if ((be16_to_cpu(hdr->lrh[0]) & 3) == QIB_LRH_BTH)
  916. ohdr = &hdr->u.oth;
  917. else
  918. ohdr = &hdr->u.l.oth;
  919. opcode = be32_to_cpu(ohdr->bth[0]) >> 24;
  920. if (opcode >= OP(RDMA_READ_RESPONSE_FIRST) &&
  921. opcode <= OP(ATOMIC_ACKNOWLEDGE)) {
  922. WARN_ON(!qp->s_rdma_ack_cnt);
  923. qp->s_rdma_ack_cnt--;
  924. return;
  925. }
  926. psn = be32_to_cpu(ohdr->bth[2]);
  927. reset_sending_psn(qp, psn);
  928. /*
  929. * Start timer after a packet requesting an ACK has been sent and
  930. * there are still requests that haven't been acked.
  931. */
  932. if ((psn & IB_BTH_REQ_ACK) && qp->s_acked != qp->s_tail &&
  933. !(qp->s_flags & (QIB_S_TIMER | QIB_S_WAIT_RNR | QIB_S_WAIT_PSN)))
  934. start_timer(qp);
  935. while (qp->s_last != qp->s_acked) {
  936. wqe = get_swqe_ptr(qp, qp->s_last);
  937. if (qib_cmp24(wqe->lpsn, qp->s_sending_psn) >= 0 &&
  938. qib_cmp24(qp->s_sending_psn, qp->s_sending_hpsn) <= 0)
  939. break;
  940. for (i = 0; i < wqe->wr.num_sge; i++) {
  941. struct qib_sge *sge = &wqe->sg_list[i];
  942. atomic_dec(&sge->mr->refcount);
  943. }
  944. /* Post a send completion queue entry if requested. */
  945. if (!(qp->s_flags & QIB_S_SIGNAL_REQ_WR) ||
  946. (wqe->wr.send_flags & IB_SEND_SIGNALED)) {
  947. memset(&wc, 0, sizeof wc);
  948. wc.wr_id = wqe->wr.wr_id;
  949. wc.status = IB_WC_SUCCESS;
  950. wc.opcode = ib_qib_wc_opcode[wqe->wr.opcode];
  951. wc.byte_len = wqe->length;
  952. wc.qp = &qp->ibqp;
  953. qib_cq_enter(to_icq(qp->ibqp.send_cq), &wc, 0);
  954. }
  955. if (++qp->s_last >= qp->s_size)
  956. qp->s_last = 0;
  957. }
  958. /*
  959. * If we were waiting for sends to complete before resending,
  960. * and they are now complete, restart sending.
  961. */
  962. if (qp->s_flags & QIB_S_WAIT_PSN &&
  963. qib_cmp24(qp->s_sending_psn, qp->s_sending_hpsn) > 0) {
  964. qp->s_flags &= ~QIB_S_WAIT_PSN;
  965. qp->s_sending_psn = qp->s_psn;
  966. qp->s_sending_hpsn = qp->s_psn - 1;
  967. qib_schedule_send(qp);
  968. }
  969. }
  970. static inline void update_last_psn(struct qib_qp *qp, u32 psn)
  971. {
  972. qp->s_last_psn = psn;
  973. }
  974. /*
  975. * Generate a SWQE completion.
  976. * This is similar to qib_send_complete but has to check to be sure
  977. * that the SGEs are not being referenced if the SWQE is being resent.
  978. */
  979. static struct qib_swqe *do_rc_completion(struct qib_qp *qp,
  980. struct qib_swqe *wqe,
  981. struct qib_ibport *ibp)
  982. {
  983. struct ib_wc wc;
  984. unsigned i;
  985. /*
  986. * Don't decrement refcount and don't generate a
  987. * completion if the SWQE is being resent until the send
  988. * is finished.
  989. */
  990. if (qib_cmp24(wqe->lpsn, qp->s_sending_psn) < 0 ||
  991. qib_cmp24(qp->s_sending_psn, qp->s_sending_hpsn) > 0) {
  992. for (i = 0; i < wqe->wr.num_sge; i++) {
  993. struct qib_sge *sge = &wqe->sg_list[i];
  994. atomic_dec(&sge->mr->refcount);
  995. }
  996. /* Post a send completion queue entry if requested. */
  997. if (!(qp->s_flags & QIB_S_SIGNAL_REQ_WR) ||
  998. (wqe->wr.send_flags & IB_SEND_SIGNALED)) {
  999. memset(&wc, 0, sizeof wc);
  1000. wc.wr_id = wqe->wr.wr_id;
  1001. wc.status = IB_WC_SUCCESS;
  1002. wc.opcode = ib_qib_wc_opcode[wqe->wr.opcode];
  1003. wc.byte_len = wqe->length;
  1004. wc.qp = &qp->ibqp;
  1005. qib_cq_enter(to_icq(qp->ibqp.send_cq), &wc, 0);
  1006. }
  1007. if (++qp->s_last >= qp->s_size)
  1008. qp->s_last = 0;
  1009. } else
  1010. ibp->n_rc_delayed_comp++;
  1011. qp->s_retry = qp->s_retry_cnt;
  1012. update_last_psn(qp, wqe->lpsn);
  1013. /*
  1014. * If we are completing a request which is in the process of
  1015. * being resent, we can stop resending it since we know the
  1016. * responder has already seen it.
  1017. */
  1018. if (qp->s_acked == qp->s_cur) {
  1019. if (++qp->s_cur >= qp->s_size)
  1020. qp->s_cur = 0;
  1021. qp->s_acked = qp->s_cur;
  1022. wqe = get_swqe_ptr(qp, qp->s_cur);
  1023. if (qp->s_acked != qp->s_tail) {
  1024. qp->s_state = OP(SEND_LAST);
  1025. qp->s_psn = wqe->psn;
  1026. }
  1027. } else {
  1028. if (++qp->s_acked >= qp->s_size)
  1029. qp->s_acked = 0;
  1030. if (qp->state == IB_QPS_SQD && qp->s_acked == qp->s_cur)
  1031. qp->s_draining = 0;
  1032. wqe = get_swqe_ptr(qp, qp->s_acked);
  1033. }
  1034. return wqe;
  1035. }
  1036. /**
  1037. * do_rc_ack - process an incoming RC ACK
  1038. * @qp: the QP the ACK came in on
  1039. * @psn: the packet sequence number of the ACK
  1040. * @opcode: the opcode of the request that resulted in the ACK
  1041. *
  1042. * This is called from qib_rc_rcv_resp() to process an incoming RC ACK
  1043. * for the given QP.
  1044. * Called at interrupt level with the QP s_lock held.
  1045. * Returns 1 if OK, 0 if current operation should be aborted (NAK).
  1046. */
  1047. static int do_rc_ack(struct qib_qp *qp, u32 aeth, u32 psn, int opcode,
  1048. u64 val, struct qib_ctxtdata *rcd)
  1049. {
  1050. struct qib_ibport *ibp;
  1051. enum ib_wc_status status;
  1052. struct qib_swqe *wqe;
  1053. int ret = 0;
  1054. u32 ack_psn;
  1055. int diff;
  1056. /* Remove QP from retry timer */
  1057. if (qp->s_flags & (QIB_S_TIMER | QIB_S_WAIT_RNR)) {
  1058. qp->s_flags &= ~(QIB_S_TIMER | QIB_S_WAIT_RNR);
  1059. del_timer(&qp->s_timer);
  1060. }
  1061. /*
  1062. * Note that NAKs implicitly ACK outstanding SEND and RDMA write
  1063. * requests and implicitly NAK RDMA read and atomic requests issued
  1064. * before the NAK'ed request. The MSN won't include the NAK'ed
  1065. * request but will include an ACK'ed request(s).
  1066. */
  1067. ack_psn = psn;
  1068. if (aeth >> 29)
  1069. ack_psn--;
  1070. wqe = get_swqe_ptr(qp, qp->s_acked);
  1071. ibp = to_iport(qp->ibqp.device, qp->port_num);
  1072. /*
  1073. * The MSN might be for a later WQE than the PSN indicates so
  1074. * only complete WQEs that the PSN finishes.
  1075. */
  1076. while ((diff = qib_cmp24(ack_psn, wqe->lpsn)) >= 0) {
  1077. /*
  1078. * RDMA_READ_RESPONSE_ONLY is a special case since
  1079. * we want to generate completion events for everything
  1080. * before the RDMA read, copy the data, then generate
  1081. * the completion for the read.
  1082. */
  1083. if (wqe->wr.opcode == IB_WR_RDMA_READ &&
  1084. opcode == OP(RDMA_READ_RESPONSE_ONLY) &&
  1085. diff == 0) {
  1086. ret = 1;
  1087. goto bail;
  1088. }
  1089. /*
  1090. * If this request is a RDMA read or atomic, and the ACK is
  1091. * for a later operation, this ACK NAKs the RDMA read or
  1092. * atomic. In other words, only a RDMA_READ_LAST or ONLY
  1093. * can ACK a RDMA read and likewise for atomic ops. Note
  1094. * that the NAK case can only happen if relaxed ordering is
  1095. * used and requests are sent after an RDMA read or atomic
  1096. * is sent but before the response is received.
  1097. */
  1098. if ((wqe->wr.opcode == IB_WR_RDMA_READ &&
  1099. (opcode != OP(RDMA_READ_RESPONSE_LAST) || diff != 0)) ||
  1100. ((wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
  1101. wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD) &&
  1102. (opcode != OP(ATOMIC_ACKNOWLEDGE) || diff != 0))) {
  1103. /* Retry this request. */
  1104. if (!(qp->r_flags & QIB_R_RDMAR_SEQ)) {
  1105. qp->r_flags |= QIB_R_RDMAR_SEQ;
  1106. qib_restart_rc(qp, qp->s_last_psn + 1, 0);
  1107. if (list_empty(&qp->rspwait)) {
  1108. qp->r_flags |= QIB_R_RSP_SEND;
  1109. atomic_inc(&qp->refcount);
  1110. list_add_tail(&qp->rspwait,
  1111. &rcd->qp_wait_list);
  1112. }
  1113. }
  1114. /*
  1115. * No need to process the ACK/NAK since we are
  1116. * restarting an earlier request.
  1117. */
  1118. goto bail;
  1119. }
  1120. if (wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
  1121. wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD) {
  1122. u64 *vaddr = wqe->sg_list[0].vaddr;
  1123. *vaddr = val;
  1124. }
  1125. if (qp->s_num_rd_atomic &&
  1126. (wqe->wr.opcode == IB_WR_RDMA_READ ||
  1127. wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
  1128. wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD)) {
  1129. qp->s_num_rd_atomic--;
  1130. /* Restart sending task if fence is complete */
  1131. if ((qp->s_flags & QIB_S_WAIT_FENCE) &&
  1132. !qp->s_num_rd_atomic) {
  1133. qp->s_flags &= ~(QIB_S_WAIT_FENCE |
  1134. QIB_S_WAIT_ACK);
  1135. qib_schedule_send(qp);
  1136. } else if (qp->s_flags & QIB_S_WAIT_RDMAR) {
  1137. qp->s_flags &= ~(QIB_S_WAIT_RDMAR |
  1138. QIB_S_WAIT_ACK);
  1139. qib_schedule_send(qp);
  1140. }
  1141. }
  1142. wqe = do_rc_completion(qp, wqe, ibp);
  1143. if (qp->s_acked == qp->s_tail)
  1144. break;
  1145. }
  1146. switch (aeth >> 29) {
  1147. case 0: /* ACK */
  1148. ibp->n_rc_acks++;
  1149. if (qp->s_acked != qp->s_tail) {
  1150. /*
  1151. * We are expecting more ACKs so
  1152. * reset the retransmit timer.
  1153. */
  1154. start_timer(qp);
  1155. /*
  1156. * We can stop resending the earlier packets and
  1157. * continue with the next packet the receiver wants.
  1158. */
  1159. if (qib_cmp24(qp->s_psn, psn) <= 0)
  1160. reset_psn(qp, psn + 1);
  1161. } else if (qib_cmp24(qp->s_psn, psn) <= 0) {
  1162. qp->s_state = OP(SEND_LAST);
  1163. qp->s_psn = psn + 1;
  1164. }
  1165. if (qp->s_flags & QIB_S_WAIT_ACK) {
  1166. qp->s_flags &= ~QIB_S_WAIT_ACK;
  1167. qib_schedule_send(qp);
  1168. }
  1169. qib_get_credit(qp, aeth);
  1170. qp->s_rnr_retry = qp->s_rnr_retry_cnt;
  1171. qp->s_retry = qp->s_retry_cnt;
  1172. update_last_psn(qp, psn);
  1173. ret = 1;
  1174. goto bail;
  1175. case 1: /* RNR NAK */
  1176. ibp->n_rnr_naks++;
  1177. if (qp->s_acked == qp->s_tail)
  1178. goto bail;
  1179. if (qp->s_flags & QIB_S_WAIT_RNR)
  1180. goto bail;
  1181. if (qp->s_rnr_retry == 0) {
  1182. status = IB_WC_RNR_RETRY_EXC_ERR;
  1183. goto class_b;
  1184. }
  1185. if (qp->s_rnr_retry_cnt < 7)
  1186. qp->s_rnr_retry--;
  1187. /* The last valid PSN is the previous PSN. */
  1188. update_last_psn(qp, psn - 1);
  1189. ibp->n_rc_resends += (qp->s_psn - psn) & QIB_PSN_MASK;
  1190. reset_psn(qp, psn);
  1191. qp->s_flags &= ~(QIB_S_WAIT_SSN_CREDIT | QIB_S_WAIT_ACK);
  1192. qp->s_flags |= QIB_S_WAIT_RNR;
  1193. qp->s_timer.function = qib_rc_rnr_retry;
  1194. qp->s_timer.expires = jiffies + usecs_to_jiffies(
  1195. ib_qib_rnr_table[(aeth >> QIB_AETH_CREDIT_SHIFT) &
  1196. QIB_AETH_CREDIT_MASK]);
  1197. add_timer(&qp->s_timer);
  1198. goto bail;
  1199. case 3: /* NAK */
  1200. if (qp->s_acked == qp->s_tail)
  1201. goto bail;
  1202. /* The last valid PSN is the previous PSN. */
  1203. update_last_psn(qp, psn - 1);
  1204. switch ((aeth >> QIB_AETH_CREDIT_SHIFT) &
  1205. QIB_AETH_CREDIT_MASK) {
  1206. case 0: /* PSN sequence error */
  1207. ibp->n_seq_naks++;
  1208. /*
  1209. * Back up to the responder's expected PSN.
  1210. * Note that we might get a NAK in the middle of an
  1211. * RDMA READ response which terminates the RDMA
  1212. * READ.
  1213. */
  1214. qib_restart_rc(qp, psn, 0);
  1215. qib_schedule_send(qp);
  1216. break;
  1217. case 1: /* Invalid Request */
  1218. status = IB_WC_REM_INV_REQ_ERR;
  1219. ibp->n_other_naks++;
  1220. goto class_b;
  1221. case 2: /* Remote Access Error */
  1222. status = IB_WC_REM_ACCESS_ERR;
  1223. ibp->n_other_naks++;
  1224. goto class_b;
  1225. case 3: /* Remote Operation Error */
  1226. status = IB_WC_REM_OP_ERR;
  1227. ibp->n_other_naks++;
  1228. class_b:
  1229. if (qp->s_last == qp->s_acked) {
  1230. qib_send_complete(qp, wqe, status);
  1231. qib_error_qp(qp, IB_WC_WR_FLUSH_ERR);
  1232. }
  1233. break;
  1234. default:
  1235. /* Ignore other reserved NAK error codes */
  1236. goto reserved;
  1237. }
  1238. qp->s_retry = qp->s_retry_cnt;
  1239. qp->s_rnr_retry = qp->s_rnr_retry_cnt;
  1240. goto bail;
  1241. default: /* 2: reserved */
  1242. reserved:
  1243. /* Ignore reserved NAK codes. */
  1244. goto bail;
  1245. }
  1246. bail:
  1247. return ret;
  1248. }
  1249. /*
  1250. * We have seen an out of sequence RDMA read middle or last packet.
  1251. * This ACKs SENDs and RDMA writes up to the first RDMA read or atomic SWQE.
  1252. */
  1253. static void rdma_seq_err(struct qib_qp *qp, struct qib_ibport *ibp, u32 psn,
  1254. struct qib_ctxtdata *rcd)
  1255. {
  1256. struct qib_swqe *wqe;
  1257. /* Remove QP from retry timer */
  1258. if (qp->s_flags & (QIB_S_TIMER | QIB_S_WAIT_RNR)) {
  1259. qp->s_flags &= ~(QIB_S_TIMER | QIB_S_WAIT_RNR);
  1260. del_timer(&qp->s_timer);
  1261. }
  1262. wqe = get_swqe_ptr(qp, qp->s_acked);
  1263. while (qib_cmp24(psn, wqe->lpsn) > 0) {
  1264. if (wqe->wr.opcode == IB_WR_RDMA_READ ||
  1265. wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
  1266. wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
  1267. break;
  1268. wqe = do_rc_completion(qp, wqe, ibp);
  1269. }
  1270. ibp->n_rdma_seq++;
  1271. qp->r_flags |= QIB_R_RDMAR_SEQ;
  1272. qib_restart_rc(qp, qp->s_last_psn + 1, 0);
  1273. if (list_empty(&qp->rspwait)) {
  1274. qp->r_flags |= QIB_R_RSP_SEND;
  1275. atomic_inc(&qp->refcount);
  1276. list_add_tail(&qp->rspwait, &rcd->qp_wait_list);
  1277. }
  1278. }
  1279. /**
  1280. * qib_rc_rcv_resp - process an incoming RC response packet
  1281. * @ibp: the port this packet came in on
  1282. * @ohdr: the other headers for this packet
  1283. * @data: the packet data
  1284. * @tlen: the packet length
  1285. * @qp: the QP for this packet
  1286. * @opcode: the opcode for this packet
  1287. * @psn: the packet sequence number for this packet
  1288. * @hdrsize: the header length
  1289. * @pmtu: the path MTU
  1290. *
  1291. * This is called from qib_rc_rcv() to process an incoming RC response
  1292. * packet for the given QP.
  1293. * Called at interrupt level.
  1294. */
  1295. static void qib_rc_rcv_resp(struct qib_ibport *ibp,
  1296. struct qib_other_headers *ohdr,
  1297. void *data, u32 tlen,
  1298. struct qib_qp *qp,
  1299. u32 opcode,
  1300. u32 psn, u32 hdrsize, u32 pmtu,
  1301. struct qib_ctxtdata *rcd)
  1302. {
  1303. struct qib_swqe *wqe;
  1304. struct qib_pportdata *ppd = ppd_from_ibp(ibp);
  1305. enum ib_wc_status status;
  1306. unsigned long flags;
  1307. int diff;
  1308. u32 pad;
  1309. u32 aeth;
  1310. u64 val;
  1311. if (opcode != OP(RDMA_READ_RESPONSE_MIDDLE)) {
  1312. /*
  1313. * If ACK'd PSN on SDMA busy list try to make progress to
  1314. * reclaim SDMA credits.
  1315. */
  1316. if ((qib_cmp24(psn, qp->s_sending_psn) >= 0) &&
  1317. (qib_cmp24(qp->s_sending_psn, qp->s_sending_hpsn) <= 0)) {
  1318. /*
  1319. * If send tasklet not running attempt to progress
  1320. * SDMA queue.
  1321. */
  1322. if (!(qp->s_flags & QIB_S_BUSY)) {
  1323. /* Acquire SDMA Lock */
  1324. spin_lock_irqsave(&ppd->sdma_lock, flags);
  1325. /* Invoke sdma make progress */
  1326. qib_sdma_make_progress(ppd);
  1327. /* Release SDMA Lock */
  1328. spin_unlock_irqrestore(&ppd->sdma_lock, flags);
  1329. }
  1330. }
  1331. }
  1332. spin_lock_irqsave(&qp->s_lock, flags);
  1333. /* Ignore invalid responses. */
  1334. if (qib_cmp24(psn, qp->s_next_psn) >= 0)
  1335. goto ack_done;
  1336. /* Ignore duplicate responses. */
  1337. diff = qib_cmp24(psn, qp->s_last_psn);
  1338. if (unlikely(diff <= 0)) {
  1339. /* Update credits for "ghost" ACKs */
  1340. if (diff == 0 && opcode == OP(ACKNOWLEDGE)) {
  1341. aeth = be32_to_cpu(ohdr->u.aeth);
  1342. if ((aeth >> 29) == 0)
  1343. qib_get_credit(qp, aeth);
  1344. }
  1345. goto ack_done;
  1346. }
  1347. /*
  1348. * Skip everything other than the PSN we expect, if we are waiting
  1349. * for a reply to a restarted RDMA read or atomic op.
  1350. */
  1351. if (qp->r_flags & QIB_R_RDMAR_SEQ) {
  1352. if (qib_cmp24(psn, qp->s_last_psn + 1) != 0)
  1353. goto ack_done;
  1354. qp->r_flags &= ~QIB_R_RDMAR_SEQ;
  1355. }
  1356. if (unlikely(qp->s_acked == qp->s_tail))
  1357. goto ack_done;
  1358. wqe = get_swqe_ptr(qp, qp->s_acked);
  1359. status = IB_WC_SUCCESS;
  1360. switch (opcode) {
  1361. case OP(ACKNOWLEDGE):
  1362. case OP(ATOMIC_ACKNOWLEDGE):
  1363. case OP(RDMA_READ_RESPONSE_FIRST):
  1364. aeth = be32_to_cpu(ohdr->u.aeth);
  1365. if (opcode == OP(ATOMIC_ACKNOWLEDGE)) {
  1366. __be32 *p = ohdr->u.at.atomic_ack_eth;
  1367. val = ((u64) be32_to_cpu(p[0]) << 32) |
  1368. be32_to_cpu(p[1]);
  1369. } else
  1370. val = 0;
  1371. if (!do_rc_ack(qp, aeth, psn, opcode, val, rcd) ||
  1372. opcode != OP(RDMA_READ_RESPONSE_FIRST))
  1373. goto ack_done;
  1374. hdrsize += 4;
  1375. wqe = get_swqe_ptr(qp, qp->s_acked);
  1376. if (unlikely(wqe->wr.opcode != IB_WR_RDMA_READ))
  1377. goto ack_op_err;
  1378. /*
  1379. * If this is a response to a resent RDMA read, we
  1380. * have to be careful to copy the data to the right
  1381. * location.
  1382. */
  1383. qp->s_rdma_read_len = restart_sge(&qp->s_rdma_read_sge,
  1384. wqe, psn, pmtu);
  1385. goto read_middle;
  1386. case OP(RDMA_READ_RESPONSE_MIDDLE):
  1387. /* no AETH, no ACK */
  1388. if (unlikely(qib_cmp24(psn, qp->s_last_psn + 1)))
  1389. goto ack_seq_err;
  1390. if (unlikely(wqe->wr.opcode != IB_WR_RDMA_READ))
  1391. goto ack_op_err;
  1392. read_middle:
  1393. if (unlikely(tlen != (hdrsize + pmtu + 4)))
  1394. goto ack_len_err;
  1395. if (unlikely(pmtu >= qp->s_rdma_read_len))
  1396. goto ack_len_err;
  1397. /*
  1398. * We got a response so update the timeout.
  1399. * 4.096 usec. * (1 << qp->timeout)
  1400. */
  1401. qp->s_flags |= QIB_S_TIMER;
  1402. mod_timer(&qp->s_timer, jiffies +
  1403. usecs_to_jiffies((4096UL * (1UL << qp->timeout)) /
  1404. 1000UL));
  1405. if (qp->s_flags & QIB_S_WAIT_ACK) {
  1406. qp->s_flags &= ~QIB_S_WAIT_ACK;
  1407. qib_schedule_send(qp);
  1408. }
  1409. if (opcode == OP(RDMA_READ_RESPONSE_MIDDLE))
  1410. qp->s_retry = qp->s_retry_cnt;
  1411. /*
  1412. * Update the RDMA receive state but do the copy w/o
  1413. * holding the locks and blocking interrupts.
  1414. */
  1415. qp->s_rdma_read_len -= pmtu;
  1416. update_last_psn(qp, psn);
  1417. spin_unlock_irqrestore(&qp->s_lock, flags);
  1418. qib_copy_sge(&qp->s_rdma_read_sge, data, pmtu, 0);
  1419. goto bail;
  1420. case OP(RDMA_READ_RESPONSE_ONLY):
  1421. aeth = be32_to_cpu(ohdr->u.aeth);
  1422. if (!do_rc_ack(qp, aeth, psn, opcode, 0, rcd))
  1423. goto ack_done;
  1424. /* Get the number of bytes the message was padded by. */
  1425. pad = (be32_to_cpu(ohdr->bth[0]) >> 20) & 3;
  1426. /*
  1427. * Check that the data size is >= 0 && <= pmtu.
  1428. * Remember to account for the AETH header (4) and
  1429. * ICRC (4).
  1430. */
  1431. if (unlikely(tlen < (hdrsize + pad + 8)))
  1432. goto ack_len_err;
  1433. /*
  1434. * If this is a response to a resent RDMA read, we
  1435. * have to be careful to copy the data to the right
  1436. * location.
  1437. */
  1438. wqe = get_swqe_ptr(qp, qp->s_acked);
  1439. qp->s_rdma_read_len = restart_sge(&qp->s_rdma_read_sge,
  1440. wqe, psn, pmtu);
  1441. goto read_last;
  1442. case OP(RDMA_READ_RESPONSE_LAST):
  1443. /* ACKs READ req. */
  1444. if (unlikely(qib_cmp24(psn, qp->s_last_psn + 1)))
  1445. goto ack_seq_err;
  1446. if (unlikely(wqe->wr.opcode != IB_WR_RDMA_READ))
  1447. goto ack_op_err;
  1448. /* Get the number of bytes the message was padded by. */
  1449. pad = (be32_to_cpu(ohdr->bth[0]) >> 20) & 3;
  1450. /*
  1451. * Check that the data size is >= 1 && <= pmtu.
  1452. * Remember to account for the AETH header (4) and
  1453. * ICRC (4).
  1454. */
  1455. if (unlikely(tlen <= (hdrsize + pad + 8)))
  1456. goto ack_len_err;
  1457. read_last:
  1458. tlen -= hdrsize + pad + 8;
  1459. if (unlikely(tlen != qp->s_rdma_read_len))
  1460. goto ack_len_err;
  1461. aeth = be32_to_cpu(ohdr->u.aeth);
  1462. qib_copy_sge(&qp->s_rdma_read_sge, data, tlen, 0);
  1463. WARN_ON(qp->s_rdma_read_sge.num_sge);
  1464. (void) do_rc_ack(qp, aeth, psn,
  1465. OP(RDMA_READ_RESPONSE_LAST), 0, rcd);
  1466. goto ack_done;
  1467. }
  1468. ack_op_err:
  1469. status = IB_WC_LOC_QP_OP_ERR;
  1470. goto ack_err;
  1471. ack_seq_err:
  1472. rdma_seq_err(qp, ibp, psn, rcd);
  1473. goto ack_done;
  1474. ack_len_err:
  1475. status = IB_WC_LOC_LEN_ERR;
  1476. ack_err:
  1477. if (qp->s_last == qp->s_acked) {
  1478. qib_send_complete(qp, wqe, status);
  1479. qib_error_qp(qp, IB_WC_WR_FLUSH_ERR);
  1480. }
  1481. ack_done:
  1482. spin_unlock_irqrestore(&qp->s_lock, flags);
  1483. bail:
  1484. return;
  1485. }
  1486. /**
  1487. * qib_rc_rcv_error - process an incoming duplicate or error RC packet
  1488. * @ohdr: the other headers for this packet
  1489. * @data: the packet data
  1490. * @qp: the QP for this packet
  1491. * @opcode: the opcode for this packet
  1492. * @psn: the packet sequence number for this packet
  1493. * @diff: the difference between the PSN and the expected PSN
  1494. *
  1495. * This is called from qib_rc_rcv() to process an unexpected
  1496. * incoming RC packet for the given QP.
  1497. * Called at interrupt level.
  1498. * Return 1 if no more processing is needed; otherwise return 0 to
  1499. * schedule a response to be sent.
  1500. */
  1501. static int qib_rc_rcv_error(struct qib_other_headers *ohdr,
  1502. void *data,
  1503. struct qib_qp *qp,
  1504. u32 opcode,
  1505. u32 psn,
  1506. int diff,
  1507. struct qib_ctxtdata *rcd)
  1508. {
  1509. struct qib_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
  1510. struct qib_ack_entry *e;
  1511. unsigned long flags;
  1512. u8 i, prev;
  1513. int old_req;
  1514. if (diff > 0) {
  1515. /*
  1516. * Packet sequence error.
  1517. * A NAK will ACK earlier sends and RDMA writes.
  1518. * Don't queue the NAK if we already sent one.
  1519. */
  1520. if (!qp->r_nak_state) {
  1521. ibp->n_rc_seqnak++;
  1522. qp->r_nak_state = IB_NAK_PSN_ERROR;
  1523. /* Use the expected PSN. */
  1524. qp->r_ack_psn = qp->r_psn;
  1525. /*
  1526. * Wait to send the sequence NAK until all packets
  1527. * in the receive queue have been processed.
  1528. * Otherwise, we end up propagating congestion.
  1529. */
  1530. if (list_empty(&qp->rspwait)) {
  1531. qp->r_flags |= QIB_R_RSP_NAK;
  1532. atomic_inc(&qp->refcount);
  1533. list_add_tail(&qp->rspwait, &rcd->qp_wait_list);
  1534. }
  1535. }
  1536. goto done;
  1537. }
  1538. /*
  1539. * Handle a duplicate request. Don't re-execute SEND, RDMA
  1540. * write or atomic op. Don't NAK errors, just silently drop
  1541. * the duplicate request. Note that r_sge, r_len, and
  1542. * r_rcv_len may be in use so don't modify them.
  1543. *
  1544. * We are supposed to ACK the earliest duplicate PSN but we
  1545. * can coalesce an outstanding duplicate ACK. We have to
  1546. * send the earliest so that RDMA reads can be restarted at
  1547. * the requester's expected PSN.
  1548. *
  1549. * First, find where this duplicate PSN falls within the
  1550. * ACKs previously sent.
  1551. * old_req is true if there is an older response that is scheduled
  1552. * to be sent before sending this one.
  1553. */
  1554. e = NULL;
  1555. old_req = 1;
  1556. ibp->n_rc_dupreq++;
  1557. spin_lock_irqsave(&qp->s_lock, flags);
  1558. for (i = qp->r_head_ack_queue; ; i = prev) {
  1559. if (i == qp->s_tail_ack_queue)
  1560. old_req = 0;
  1561. if (i)
  1562. prev = i - 1;
  1563. else
  1564. prev = QIB_MAX_RDMA_ATOMIC;
  1565. if (prev == qp->r_head_ack_queue) {
  1566. e = NULL;
  1567. break;
  1568. }
  1569. e = &qp->s_ack_queue[prev];
  1570. if (!e->opcode) {
  1571. e = NULL;
  1572. break;
  1573. }
  1574. if (qib_cmp24(psn, e->psn) >= 0) {
  1575. if (prev == qp->s_tail_ack_queue &&
  1576. qib_cmp24(psn, e->lpsn) <= 0)
  1577. old_req = 0;
  1578. break;
  1579. }
  1580. }
  1581. switch (opcode) {
  1582. case OP(RDMA_READ_REQUEST): {
  1583. struct ib_reth *reth;
  1584. u32 offset;
  1585. u32 len;
  1586. /*
  1587. * If we didn't find the RDMA read request in the ack queue,
  1588. * we can ignore this request.
  1589. */
  1590. if (!e || e->opcode != OP(RDMA_READ_REQUEST))
  1591. goto unlock_done;
  1592. /* RETH comes after BTH */
  1593. reth = &ohdr->u.rc.reth;
  1594. /*
  1595. * Address range must be a subset of the original
  1596. * request and start on pmtu boundaries.
  1597. * We reuse the old ack_queue slot since the requester
  1598. * should not back up and request an earlier PSN for the
  1599. * same request.
  1600. */
  1601. offset = ((psn - e->psn) & QIB_PSN_MASK) *
  1602. ib_mtu_enum_to_int(qp->path_mtu);
  1603. len = be32_to_cpu(reth->length);
  1604. if (unlikely(offset + len != e->rdma_sge.sge_length))
  1605. goto unlock_done;
  1606. if (e->rdma_sge.mr) {
  1607. atomic_dec(&e->rdma_sge.mr->refcount);
  1608. e->rdma_sge.mr = NULL;
  1609. }
  1610. if (len != 0) {
  1611. u32 rkey = be32_to_cpu(reth->rkey);
  1612. u64 vaddr = be64_to_cpu(reth->vaddr);
  1613. int ok;
  1614. ok = qib_rkey_ok(qp, &e->rdma_sge, len, vaddr, rkey,
  1615. IB_ACCESS_REMOTE_READ);
  1616. if (unlikely(!ok))
  1617. goto unlock_done;
  1618. } else {
  1619. e->rdma_sge.vaddr = NULL;
  1620. e->rdma_sge.length = 0;
  1621. e->rdma_sge.sge_length = 0;
  1622. }
  1623. e->psn = psn;
  1624. if (old_req)
  1625. goto unlock_done;
  1626. qp->s_tail_ack_queue = prev;
  1627. break;
  1628. }
  1629. case OP(COMPARE_SWAP):
  1630. case OP(FETCH_ADD): {
  1631. /*
  1632. * If we didn't find the atomic request in the ack queue
  1633. * or the send tasklet is already backed up to send an
  1634. * earlier entry, we can ignore this request.
  1635. */
  1636. if (!e || e->opcode != (u8) opcode || old_req)
  1637. goto unlock_done;
  1638. qp->s_tail_ack_queue = prev;
  1639. break;
  1640. }
  1641. default:
  1642. /*
  1643. * Ignore this operation if it doesn't request an ACK
  1644. * or an earlier RDMA read or atomic is going to be resent.
  1645. */
  1646. if (!(psn & IB_BTH_REQ_ACK) || old_req)
  1647. goto unlock_done;
  1648. /*
  1649. * Resend the most recent ACK if this request is
  1650. * after all the previous RDMA reads and atomics.
  1651. */
  1652. if (i == qp->r_head_ack_queue) {
  1653. spin_unlock_irqrestore(&qp->s_lock, flags);
  1654. qp->r_nak_state = 0;
  1655. qp->r_ack_psn = qp->r_psn - 1;
  1656. goto send_ack;
  1657. }
  1658. /*
  1659. * Try to send a simple ACK to work around a Mellanox bug
  1660. * which doesn't accept a RDMA read response or atomic
  1661. * response as an ACK for earlier SENDs or RDMA writes.
  1662. */
  1663. if (!(qp->s_flags & QIB_S_RESP_PENDING)) {
  1664. spin_unlock_irqrestore(&qp->s_lock, flags);
  1665. qp->r_nak_state = 0;
  1666. qp->r_ack_psn = qp->s_ack_queue[i].psn - 1;
  1667. goto send_ack;
  1668. }
  1669. /*
  1670. * Resend the RDMA read or atomic op which
  1671. * ACKs this duplicate request.
  1672. */
  1673. qp->s_tail_ack_queue = i;
  1674. break;
  1675. }
  1676. qp->s_ack_state = OP(ACKNOWLEDGE);
  1677. qp->s_flags |= QIB_S_RESP_PENDING;
  1678. qp->r_nak_state = 0;
  1679. qib_schedule_send(qp);
  1680. unlock_done:
  1681. spin_unlock_irqrestore(&qp->s_lock, flags);
  1682. done:
  1683. return 1;
  1684. send_ack:
  1685. return 0;
  1686. }
  1687. void qib_rc_error(struct qib_qp *qp, enum ib_wc_status err)
  1688. {
  1689. unsigned long flags;
  1690. int lastwqe;
  1691. spin_lock_irqsave(&qp->s_lock, flags);
  1692. lastwqe = qib_error_qp(qp, err);
  1693. spin_unlock_irqrestore(&qp->s_lock, flags);
  1694. if (lastwqe) {
  1695. struct ib_event ev;
  1696. ev.device = qp->ibqp.device;
  1697. ev.element.qp = &qp->ibqp;
  1698. ev.event = IB_EVENT_QP_LAST_WQE_REACHED;
  1699. qp->ibqp.event_handler(&ev, qp->ibqp.qp_context);
  1700. }
  1701. }
  1702. static inline void qib_update_ack_queue(struct qib_qp *qp, unsigned n)
  1703. {
  1704. unsigned next;
  1705. next = n + 1;
  1706. if (next > QIB_MAX_RDMA_ATOMIC)
  1707. next = 0;
  1708. qp->s_tail_ack_queue = next;
  1709. qp->s_ack_state = OP(ACKNOWLEDGE);
  1710. }
  1711. /**
  1712. * qib_rc_rcv - process an incoming RC packet
  1713. * @rcd: the context pointer
  1714. * @hdr: the header of this packet
  1715. * @has_grh: true if the header has a GRH
  1716. * @data: the packet data
  1717. * @tlen: the packet length
  1718. * @qp: the QP for this packet
  1719. *
  1720. * This is called from qib_qp_rcv() to process an incoming RC packet
  1721. * for the given QP.
  1722. * Called at interrupt level.
  1723. */
  1724. void qib_rc_rcv(struct qib_ctxtdata *rcd, struct qib_ib_header *hdr,
  1725. int has_grh, void *data, u32 tlen, struct qib_qp *qp)
  1726. {
  1727. struct qib_ibport *ibp = &rcd->ppd->ibport_data;
  1728. struct qib_other_headers *ohdr;
  1729. u32 opcode;
  1730. u32 hdrsize;
  1731. u32 psn;
  1732. u32 pad;
  1733. struct ib_wc wc;
  1734. u32 pmtu = ib_mtu_enum_to_int(qp->path_mtu);
  1735. int diff;
  1736. struct ib_reth *reth;
  1737. unsigned long flags;
  1738. int ret;
  1739. /* Check for GRH */
  1740. if (!has_grh) {
  1741. ohdr = &hdr->u.oth;
  1742. hdrsize = 8 + 12; /* LRH + BTH */
  1743. } else {
  1744. ohdr = &hdr->u.l.oth;
  1745. hdrsize = 8 + 40 + 12; /* LRH + GRH + BTH */
  1746. }
  1747. opcode = be32_to_cpu(ohdr->bth[0]);
  1748. spin_lock_irqsave(&qp->s_lock, flags);
  1749. if (qib_ruc_check_hdr(ibp, hdr, has_grh, qp, opcode))
  1750. goto sunlock;
  1751. spin_unlock_irqrestore(&qp->s_lock, flags);
  1752. psn = be32_to_cpu(ohdr->bth[2]);
  1753. opcode >>= 24;
  1754. /*
  1755. * Process responses (ACKs) before anything else. Note that the
  1756. * packet sequence number will be for something in the send work
  1757. * queue rather than the expected receive packet sequence number.
  1758. * In other words, this QP is the requester.
  1759. */
  1760. if (opcode >= OP(RDMA_READ_RESPONSE_FIRST) &&
  1761. opcode <= OP(ATOMIC_ACKNOWLEDGE)) {
  1762. qib_rc_rcv_resp(ibp, ohdr, data, tlen, qp, opcode, psn,
  1763. hdrsize, pmtu, rcd);
  1764. return;
  1765. }
  1766. /* Compute 24 bits worth of difference. */
  1767. diff = qib_cmp24(psn, qp->r_psn);
  1768. if (unlikely(diff)) {
  1769. if (qib_rc_rcv_error(ohdr, data, qp, opcode, psn, diff, rcd))
  1770. return;
  1771. goto send_ack;
  1772. }
  1773. /* Check for opcode sequence errors. */
  1774. switch (qp->r_state) {
  1775. case OP(SEND_FIRST):
  1776. case OP(SEND_MIDDLE):
  1777. if (opcode == OP(SEND_MIDDLE) ||
  1778. opcode == OP(SEND_LAST) ||
  1779. opcode == OP(SEND_LAST_WITH_IMMEDIATE))
  1780. break;
  1781. goto nack_inv;
  1782. case OP(RDMA_WRITE_FIRST):
  1783. case OP(RDMA_WRITE_MIDDLE):
  1784. if (opcode == OP(RDMA_WRITE_MIDDLE) ||
  1785. opcode == OP(RDMA_WRITE_LAST) ||
  1786. opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE))
  1787. break;
  1788. goto nack_inv;
  1789. default:
  1790. if (opcode == OP(SEND_MIDDLE) ||
  1791. opcode == OP(SEND_LAST) ||
  1792. opcode == OP(SEND_LAST_WITH_IMMEDIATE) ||
  1793. opcode == OP(RDMA_WRITE_MIDDLE) ||
  1794. opcode == OP(RDMA_WRITE_LAST) ||
  1795. opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE))
  1796. goto nack_inv;
  1797. /*
  1798. * Note that it is up to the requester to not send a new
  1799. * RDMA read or atomic operation before receiving an ACK
  1800. * for the previous operation.
  1801. */
  1802. break;
  1803. }
  1804. memset(&wc, 0, sizeof wc);
  1805. if (qp->state == IB_QPS_RTR && !(qp->r_flags & QIB_R_COMM_EST)) {
  1806. qp->r_flags |= QIB_R_COMM_EST;
  1807. if (qp->ibqp.event_handler) {
  1808. struct ib_event ev;
  1809. ev.device = qp->ibqp.device;
  1810. ev.element.qp = &qp->ibqp;
  1811. ev.event = IB_EVENT_COMM_EST;
  1812. qp->ibqp.event_handler(&ev, qp->ibqp.qp_context);
  1813. }
  1814. }
  1815. /* OK, process the packet. */
  1816. switch (opcode) {
  1817. case OP(SEND_FIRST):
  1818. ret = qib_get_rwqe(qp, 0);
  1819. if (ret < 0)
  1820. goto nack_op_err;
  1821. if (!ret)
  1822. goto rnr_nak;
  1823. qp->r_rcv_len = 0;
  1824. /* FALLTHROUGH */
  1825. case OP(SEND_MIDDLE):
  1826. case OP(RDMA_WRITE_MIDDLE):
  1827. send_middle:
  1828. /* Check for invalid length PMTU or posted rwqe len. */
  1829. if (unlikely(tlen != (hdrsize + pmtu + 4)))
  1830. goto nack_inv;
  1831. qp->r_rcv_len += pmtu;
  1832. if (unlikely(qp->r_rcv_len > qp->r_len))
  1833. goto nack_inv;
  1834. qib_copy_sge(&qp->r_sge, data, pmtu, 1);
  1835. break;
  1836. case OP(RDMA_WRITE_LAST_WITH_IMMEDIATE):
  1837. /* consume RWQE */
  1838. ret = qib_get_rwqe(qp, 1);
  1839. if (ret < 0)
  1840. goto nack_op_err;
  1841. if (!ret)
  1842. goto rnr_nak;
  1843. goto send_last_imm;
  1844. case OP(SEND_ONLY):
  1845. case OP(SEND_ONLY_WITH_IMMEDIATE):
  1846. ret = qib_get_rwqe(qp, 0);
  1847. if (ret < 0)
  1848. goto nack_op_err;
  1849. if (!ret)
  1850. goto rnr_nak;
  1851. qp->r_rcv_len = 0;
  1852. if (opcode == OP(SEND_ONLY))
  1853. goto send_last;
  1854. /* FALLTHROUGH */
  1855. case OP(SEND_LAST_WITH_IMMEDIATE):
  1856. send_last_imm:
  1857. wc.ex.imm_data = ohdr->u.imm_data;
  1858. hdrsize += 4;
  1859. wc.wc_flags = IB_WC_WITH_IMM;
  1860. /* FALLTHROUGH */
  1861. case OP(SEND_LAST):
  1862. case OP(RDMA_WRITE_LAST):
  1863. send_last:
  1864. /* Get the number of bytes the message was padded by. */
  1865. pad = (be32_to_cpu(ohdr->bth[0]) >> 20) & 3;
  1866. /* Check for invalid length. */
  1867. /* XXX LAST len should be >= 1 */
  1868. if (unlikely(tlen < (hdrsize + pad + 4)))
  1869. goto nack_inv;
  1870. /* Don't count the CRC. */
  1871. tlen -= (hdrsize + pad + 4);
  1872. wc.byte_len = tlen + qp->r_rcv_len;
  1873. if (unlikely(wc.byte_len > qp->r_len))
  1874. goto nack_inv;
  1875. qib_copy_sge(&qp->r_sge, data, tlen, 1);
  1876. while (qp->r_sge.num_sge) {
  1877. atomic_dec(&qp->r_sge.sge.mr->refcount);
  1878. if (--qp->r_sge.num_sge)
  1879. qp->r_sge.sge = *qp->r_sge.sg_list++;
  1880. }
  1881. qp->r_msn++;
  1882. if (!test_and_clear_bit(QIB_R_WRID_VALID, &qp->r_aflags))
  1883. break;
  1884. wc.wr_id = qp->r_wr_id;
  1885. wc.status = IB_WC_SUCCESS;
  1886. if (opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE) ||
  1887. opcode == OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE))
  1888. wc.opcode = IB_WC_RECV_RDMA_WITH_IMM;
  1889. else
  1890. wc.opcode = IB_WC_RECV;
  1891. wc.qp = &qp->ibqp;
  1892. wc.src_qp = qp->remote_qpn;
  1893. wc.slid = qp->remote_ah_attr.dlid;
  1894. wc.sl = qp->remote_ah_attr.sl;
  1895. /* Signal completion event if the solicited bit is set. */
  1896. qib_cq_enter(to_icq(qp->ibqp.recv_cq), &wc,
  1897. (ohdr->bth[0] &
  1898. cpu_to_be32(IB_BTH_SOLICITED)) != 0);
  1899. break;
  1900. case OP(RDMA_WRITE_FIRST):
  1901. case OP(RDMA_WRITE_ONLY):
  1902. case OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE):
  1903. if (unlikely(!(qp->qp_access_flags & IB_ACCESS_REMOTE_WRITE)))
  1904. goto nack_inv;
  1905. /* consume RWQE */
  1906. reth = &ohdr->u.rc.reth;
  1907. hdrsize += sizeof(*reth);
  1908. qp->r_len = be32_to_cpu(reth->length);
  1909. qp->r_rcv_len = 0;
  1910. qp->r_sge.sg_list = NULL;
  1911. if (qp->r_len != 0) {
  1912. u32 rkey = be32_to_cpu(reth->rkey);
  1913. u64 vaddr = be64_to_cpu(reth->vaddr);
  1914. int ok;
  1915. /* Check rkey & NAK */
  1916. ok = qib_rkey_ok(qp, &qp->r_sge.sge, qp->r_len, vaddr,
  1917. rkey, IB_ACCESS_REMOTE_WRITE);
  1918. if (unlikely(!ok))
  1919. goto nack_acc;
  1920. qp->r_sge.num_sge = 1;
  1921. } else {
  1922. qp->r_sge.num_sge = 0;
  1923. qp->r_sge.sge.mr = NULL;
  1924. qp->r_sge.sge.vaddr = NULL;
  1925. qp->r_sge.sge.length = 0;
  1926. qp->r_sge.sge.sge_length = 0;
  1927. }
  1928. if (opcode == OP(RDMA_WRITE_FIRST))
  1929. goto send_middle;
  1930. else if (opcode == OP(RDMA_WRITE_ONLY))
  1931. goto send_last;
  1932. ret = qib_get_rwqe(qp, 1);
  1933. if (ret < 0)
  1934. goto nack_op_err;
  1935. if (!ret)
  1936. goto rnr_nak;
  1937. wc.ex.imm_data = ohdr->u.rc.imm_data;
  1938. hdrsize += 4;
  1939. wc.wc_flags = IB_WC_WITH_IMM;
  1940. goto send_last;
  1941. case OP(RDMA_READ_REQUEST): {
  1942. struct qib_ack_entry *e;
  1943. u32 len;
  1944. u8 next;
  1945. if (unlikely(!(qp->qp_access_flags & IB_ACCESS_REMOTE_READ)))
  1946. goto nack_inv;
  1947. next = qp->r_head_ack_queue + 1;
  1948. /* s_ack_queue is size QIB_MAX_RDMA_ATOMIC+1 so use > not >= */
  1949. if (next > QIB_MAX_RDMA_ATOMIC)
  1950. next = 0;
  1951. spin_lock_irqsave(&qp->s_lock, flags);
  1952. if (unlikely(next == qp->s_tail_ack_queue)) {
  1953. if (!qp->s_ack_queue[next].sent)
  1954. goto nack_inv_unlck;
  1955. qib_update_ack_queue(qp, next);
  1956. }
  1957. e = &qp->s_ack_queue[qp->r_head_ack_queue];
  1958. if (e->opcode == OP(RDMA_READ_REQUEST) && e->rdma_sge.mr) {
  1959. atomic_dec(&e->rdma_sge.mr->refcount);
  1960. e->rdma_sge.mr = NULL;
  1961. }
  1962. reth = &ohdr->u.rc.reth;
  1963. len = be32_to_cpu(reth->length);
  1964. if (len) {
  1965. u32 rkey = be32_to_cpu(reth->rkey);
  1966. u64 vaddr = be64_to_cpu(reth->vaddr);
  1967. int ok;
  1968. /* Check rkey & NAK */
  1969. ok = qib_rkey_ok(qp, &e->rdma_sge, len, vaddr,
  1970. rkey, IB_ACCESS_REMOTE_READ);
  1971. if (unlikely(!ok))
  1972. goto nack_acc_unlck;
  1973. /*
  1974. * Update the next expected PSN. We add 1 later
  1975. * below, so only add the remainder here.
  1976. */
  1977. if (len > pmtu)
  1978. qp->r_psn += (len - 1) / pmtu;
  1979. } else {
  1980. e->rdma_sge.mr = NULL;
  1981. e->rdma_sge.vaddr = NULL;
  1982. e->rdma_sge.length = 0;
  1983. e->rdma_sge.sge_length = 0;
  1984. }
  1985. e->opcode = opcode;
  1986. e->sent = 0;
  1987. e->psn = psn;
  1988. e->lpsn = qp->r_psn;
  1989. /*
  1990. * We need to increment the MSN here instead of when we
  1991. * finish sending the result since a duplicate request would
  1992. * increment it more than once.
  1993. */
  1994. qp->r_msn++;
  1995. qp->r_psn++;
  1996. qp->r_state = opcode;
  1997. qp->r_nak_state = 0;
  1998. qp->r_head_ack_queue = next;
  1999. /* Schedule the send tasklet. */
  2000. qp->s_flags |= QIB_S_RESP_PENDING;
  2001. qib_schedule_send(qp);
  2002. goto sunlock;
  2003. }
  2004. case OP(COMPARE_SWAP):
  2005. case OP(FETCH_ADD): {
  2006. struct ib_atomic_eth *ateth;
  2007. struct qib_ack_entry *e;
  2008. u64 vaddr;
  2009. atomic64_t *maddr;
  2010. u64 sdata;
  2011. u32 rkey;
  2012. u8 next;
  2013. if (unlikely(!(qp->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)))
  2014. goto nack_inv;
  2015. next = qp->r_head_ack_queue + 1;
  2016. if (next > QIB_MAX_RDMA_ATOMIC)
  2017. next = 0;
  2018. spin_lock_irqsave(&qp->s_lock, flags);
  2019. if (unlikely(next == qp->s_tail_ack_queue)) {
  2020. if (!qp->s_ack_queue[next].sent)
  2021. goto nack_inv_unlck;
  2022. qib_update_ack_queue(qp, next);
  2023. }
  2024. e = &qp->s_ack_queue[qp->r_head_ack_queue];
  2025. if (e->opcode == OP(RDMA_READ_REQUEST) && e->rdma_sge.mr) {
  2026. atomic_dec(&e->rdma_sge.mr->refcount);
  2027. e->rdma_sge.mr = NULL;
  2028. }
  2029. ateth = &ohdr->u.atomic_eth;
  2030. vaddr = ((u64) be32_to_cpu(ateth->vaddr[0]) << 32) |
  2031. be32_to_cpu(ateth->vaddr[1]);
  2032. if (unlikely(vaddr & (sizeof(u64) - 1)))
  2033. goto nack_inv_unlck;
  2034. rkey = be32_to_cpu(ateth->rkey);
  2035. /* Check rkey & NAK */
  2036. if (unlikely(!qib_rkey_ok(qp, &qp->r_sge.sge, sizeof(u64),
  2037. vaddr, rkey,
  2038. IB_ACCESS_REMOTE_ATOMIC)))
  2039. goto nack_acc_unlck;
  2040. /* Perform atomic OP and save result. */
  2041. maddr = (atomic64_t *) qp->r_sge.sge.vaddr;
  2042. sdata = be64_to_cpu(ateth->swap_data);
  2043. e->atomic_data = (opcode == OP(FETCH_ADD)) ?
  2044. (u64) atomic64_add_return(sdata, maddr) - sdata :
  2045. (u64) cmpxchg((u64 *) qp->r_sge.sge.vaddr,
  2046. be64_to_cpu(ateth->compare_data),
  2047. sdata);
  2048. atomic_dec(&qp->r_sge.sge.mr->refcount);
  2049. qp->r_sge.num_sge = 0;
  2050. e->opcode = opcode;
  2051. e->sent = 0;
  2052. e->psn = psn;
  2053. e->lpsn = psn;
  2054. qp->r_msn++;
  2055. qp->r_psn++;
  2056. qp->r_state = opcode;
  2057. qp->r_nak_state = 0;
  2058. qp->r_head_ack_queue = next;
  2059. /* Schedule the send tasklet. */
  2060. qp->s_flags |= QIB_S_RESP_PENDING;
  2061. qib_schedule_send(qp);
  2062. goto sunlock;
  2063. }
  2064. default:
  2065. /* NAK unknown opcodes. */
  2066. goto nack_inv;
  2067. }
  2068. qp->r_psn++;
  2069. qp->r_state = opcode;
  2070. qp->r_ack_psn = psn;
  2071. qp->r_nak_state = 0;
  2072. /* Send an ACK if requested or required. */
  2073. if (psn & (1 << 31))
  2074. goto send_ack;
  2075. return;
  2076. rnr_nak:
  2077. qp->r_nak_state = IB_RNR_NAK | qp->r_min_rnr_timer;
  2078. qp->r_ack_psn = qp->r_psn;
  2079. /* Queue RNR NAK for later */
  2080. if (list_empty(&qp->rspwait)) {
  2081. qp->r_flags |= QIB_R_RSP_NAK;
  2082. atomic_inc(&qp->refcount);
  2083. list_add_tail(&qp->rspwait, &rcd->qp_wait_list);
  2084. }
  2085. return;
  2086. nack_op_err:
  2087. qib_rc_error(qp, IB_WC_LOC_QP_OP_ERR);
  2088. qp->r_nak_state = IB_NAK_REMOTE_OPERATIONAL_ERROR;
  2089. qp->r_ack_psn = qp->r_psn;
  2090. /* Queue NAK for later */
  2091. if (list_empty(&qp->rspwait)) {
  2092. qp->r_flags |= QIB_R_RSP_NAK;
  2093. atomic_inc(&qp->refcount);
  2094. list_add_tail(&qp->rspwait, &rcd->qp_wait_list);
  2095. }
  2096. return;
  2097. nack_inv_unlck:
  2098. spin_unlock_irqrestore(&qp->s_lock, flags);
  2099. nack_inv:
  2100. qib_rc_error(qp, IB_WC_LOC_QP_OP_ERR);
  2101. qp->r_nak_state = IB_NAK_INVALID_REQUEST;
  2102. qp->r_ack_psn = qp->r_psn;
  2103. /* Queue NAK for later */
  2104. if (list_empty(&qp->rspwait)) {
  2105. qp->r_flags |= QIB_R_RSP_NAK;
  2106. atomic_inc(&qp->refcount);
  2107. list_add_tail(&qp->rspwait, &rcd->qp_wait_list);
  2108. }
  2109. return;
  2110. nack_acc_unlck:
  2111. spin_unlock_irqrestore(&qp->s_lock, flags);
  2112. nack_acc:
  2113. qib_rc_error(qp, IB_WC_LOC_PROT_ERR);
  2114. qp->r_nak_state = IB_NAK_REMOTE_ACCESS_ERROR;
  2115. qp->r_ack_psn = qp->r_psn;
  2116. send_ack:
  2117. qib_send_rc_ack(qp);
  2118. return;
  2119. sunlock:
  2120. spin_unlock_irqrestore(&qp->s_lock, flags);
  2121. }