mthca_memfree.c 18 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Cisco Systems. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. */
  34. #include <linux/mm.h>
  35. #include <linux/scatterlist.h>
  36. #include <linux/sched.h>
  37. #include <linux/slab.h>
  38. #include <asm/page.h>
  39. #include "mthca_memfree.h"
  40. #include "mthca_dev.h"
  41. #include "mthca_cmd.h"
  42. /*
  43. * We allocate in as big chunks as we can, up to a maximum of 256 KB
  44. * per chunk.
  45. */
  46. enum {
  47. MTHCA_ICM_ALLOC_SIZE = 1 << 18,
  48. MTHCA_TABLE_CHUNK_SIZE = 1 << 18
  49. };
  50. struct mthca_user_db_table {
  51. struct mutex mutex;
  52. struct {
  53. u64 uvirt;
  54. struct scatterlist mem;
  55. int refcount;
  56. } page[0];
  57. };
  58. static void mthca_free_icm_pages(struct mthca_dev *dev, struct mthca_icm_chunk *chunk)
  59. {
  60. int i;
  61. if (chunk->nsg > 0)
  62. pci_unmap_sg(dev->pdev, chunk->mem, chunk->npages,
  63. PCI_DMA_BIDIRECTIONAL);
  64. for (i = 0; i < chunk->npages; ++i)
  65. __free_pages(sg_page(&chunk->mem[i]),
  66. get_order(chunk->mem[i].length));
  67. }
  68. static void mthca_free_icm_coherent(struct mthca_dev *dev, struct mthca_icm_chunk *chunk)
  69. {
  70. int i;
  71. for (i = 0; i < chunk->npages; ++i) {
  72. dma_free_coherent(&dev->pdev->dev, chunk->mem[i].length,
  73. lowmem_page_address(sg_page(&chunk->mem[i])),
  74. sg_dma_address(&chunk->mem[i]));
  75. }
  76. }
  77. void mthca_free_icm(struct mthca_dev *dev, struct mthca_icm *icm, int coherent)
  78. {
  79. struct mthca_icm_chunk *chunk, *tmp;
  80. if (!icm)
  81. return;
  82. list_for_each_entry_safe(chunk, tmp, &icm->chunk_list, list) {
  83. if (coherent)
  84. mthca_free_icm_coherent(dev, chunk);
  85. else
  86. mthca_free_icm_pages(dev, chunk);
  87. kfree(chunk);
  88. }
  89. kfree(icm);
  90. }
  91. static int mthca_alloc_icm_pages(struct scatterlist *mem, int order, gfp_t gfp_mask)
  92. {
  93. struct page *page;
  94. /*
  95. * Use __GFP_ZERO because buggy firmware assumes ICM pages are
  96. * cleared, and subtle failures are seen if they aren't.
  97. */
  98. page = alloc_pages(gfp_mask | __GFP_ZERO, order);
  99. if (!page)
  100. return -ENOMEM;
  101. sg_set_page(mem, page, PAGE_SIZE << order, 0);
  102. return 0;
  103. }
  104. static int mthca_alloc_icm_coherent(struct device *dev, struct scatterlist *mem,
  105. int order, gfp_t gfp_mask)
  106. {
  107. void *buf = dma_alloc_coherent(dev, PAGE_SIZE << order, &sg_dma_address(mem),
  108. gfp_mask);
  109. if (!buf)
  110. return -ENOMEM;
  111. sg_set_buf(mem, buf, PAGE_SIZE << order);
  112. BUG_ON(mem->offset);
  113. sg_dma_len(mem) = PAGE_SIZE << order;
  114. return 0;
  115. }
  116. struct mthca_icm *mthca_alloc_icm(struct mthca_dev *dev, int npages,
  117. gfp_t gfp_mask, int coherent)
  118. {
  119. struct mthca_icm *icm;
  120. struct mthca_icm_chunk *chunk = NULL;
  121. int cur_order;
  122. int ret;
  123. /* We use sg_set_buf for coherent allocs, which assumes low memory */
  124. BUG_ON(coherent && (gfp_mask & __GFP_HIGHMEM));
  125. icm = kmalloc(sizeof *icm, gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
  126. if (!icm)
  127. return icm;
  128. icm->refcount = 0;
  129. INIT_LIST_HEAD(&icm->chunk_list);
  130. cur_order = get_order(MTHCA_ICM_ALLOC_SIZE);
  131. while (npages > 0) {
  132. if (!chunk) {
  133. chunk = kmalloc(sizeof *chunk,
  134. gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
  135. if (!chunk)
  136. goto fail;
  137. sg_init_table(chunk->mem, MTHCA_ICM_CHUNK_LEN);
  138. chunk->npages = 0;
  139. chunk->nsg = 0;
  140. list_add_tail(&chunk->list, &icm->chunk_list);
  141. }
  142. while (1 << cur_order > npages)
  143. --cur_order;
  144. if (coherent)
  145. ret = mthca_alloc_icm_coherent(&dev->pdev->dev,
  146. &chunk->mem[chunk->npages],
  147. cur_order, gfp_mask);
  148. else
  149. ret = mthca_alloc_icm_pages(&chunk->mem[chunk->npages],
  150. cur_order, gfp_mask);
  151. if (!ret) {
  152. ++chunk->npages;
  153. if (coherent)
  154. ++chunk->nsg;
  155. else if (chunk->npages == MTHCA_ICM_CHUNK_LEN) {
  156. chunk->nsg = pci_map_sg(dev->pdev, chunk->mem,
  157. chunk->npages,
  158. PCI_DMA_BIDIRECTIONAL);
  159. if (chunk->nsg <= 0)
  160. goto fail;
  161. }
  162. if (chunk->npages == MTHCA_ICM_CHUNK_LEN)
  163. chunk = NULL;
  164. npages -= 1 << cur_order;
  165. } else {
  166. --cur_order;
  167. if (cur_order < 0)
  168. goto fail;
  169. }
  170. }
  171. if (!coherent && chunk) {
  172. chunk->nsg = pci_map_sg(dev->pdev, chunk->mem,
  173. chunk->npages,
  174. PCI_DMA_BIDIRECTIONAL);
  175. if (chunk->nsg <= 0)
  176. goto fail;
  177. }
  178. return icm;
  179. fail:
  180. mthca_free_icm(dev, icm, coherent);
  181. return NULL;
  182. }
  183. int mthca_table_get(struct mthca_dev *dev, struct mthca_icm_table *table, int obj)
  184. {
  185. int i = (obj & (table->num_obj - 1)) * table->obj_size / MTHCA_TABLE_CHUNK_SIZE;
  186. int ret = 0;
  187. u8 status;
  188. mutex_lock(&table->mutex);
  189. if (table->icm[i]) {
  190. ++table->icm[i]->refcount;
  191. goto out;
  192. }
  193. table->icm[i] = mthca_alloc_icm(dev, MTHCA_TABLE_CHUNK_SIZE >> PAGE_SHIFT,
  194. (table->lowmem ? GFP_KERNEL : GFP_HIGHUSER) |
  195. __GFP_NOWARN, table->coherent);
  196. if (!table->icm[i]) {
  197. ret = -ENOMEM;
  198. goto out;
  199. }
  200. if (mthca_MAP_ICM(dev, table->icm[i], table->virt + i * MTHCA_TABLE_CHUNK_SIZE,
  201. &status) || status) {
  202. mthca_free_icm(dev, table->icm[i], table->coherent);
  203. table->icm[i] = NULL;
  204. ret = -ENOMEM;
  205. goto out;
  206. }
  207. ++table->icm[i]->refcount;
  208. out:
  209. mutex_unlock(&table->mutex);
  210. return ret;
  211. }
  212. void mthca_table_put(struct mthca_dev *dev, struct mthca_icm_table *table, int obj)
  213. {
  214. int i;
  215. u8 status;
  216. if (!mthca_is_memfree(dev))
  217. return;
  218. i = (obj & (table->num_obj - 1)) * table->obj_size / MTHCA_TABLE_CHUNK_SIZE;
  219. mutex_lock(&table->mutex);
  220. if (--table->icm[i]->refcount == 0) {
  221. mthca_UNMAP_ICM(dev, table->virt + i * MTHCA_TABLE_CHUNK_SIZE,
  222. MTHCA_TABLE_CHUNK_SIZE / MTHCA_ICM_PAGE_SIZE,
  223. &status);
  224. mthca_free_icm(dev, table->icm[i], table->coherent);
  225. table->icm[i] = NULL;
  226. }
  227. mutex_unlock(&table->mutex);
  228. }
  229. void *mthca_table_find(struct mthca_icm_table *table, int obj, dma_addr_t *dma_handle)
  230. {
  231. int idx, offset, dma_offset, i;
  232. struct mthca_icm_chunk *chunk;
  233. struct mthca_icm *icm;
  234. struct page *page = NULL;
  235. if (!table->lowmem)
  236. return NULL;
  237. mutex_lock(&table->mutex);
  238. idx = (obj & (table->num_obj - 1)) * table->obj_size;
  239. icm = table->icm[idx / MTHCA_TABLE_CHUNK_SIZE];
  240. dma_offset = offset = idx % MTHCA_TABLE_CHUNK_SIZE;
  241. if (!icm)
  242. goto out;
  243. list_for_each_entry(chunk, &icm->chunk_list, list) {
  244. for (i = 0; i < chunk->npages; ++i) {
  245. if (dma_handle && dma_offset >= 0) {
  246. if (sg_dma_len(&chunk->mem[i]) > dma_offset)
  247. *dma_handle = sg_dma_address(&chunk->mem[i]) +
  248. dma_offset;
  249. dma_offset -= sg_dma_len(&chunk->mem[i]);
  250. }
  251. /* DMA mapping can merge pages but not split them,
  252. * so if we found the page, dma_handle has already
  253. * been assigned to. */
  254. if (chunk->mem[i].length > offset) {
  255. page = sg_page(&chunk->mem[i]);
  256. goto out;
  257. }
  258. offset -= chunk->mem[i].length;
  259. }
  260. }
  261. out:
  262. mutex_unlock(&table->mutex);
  263. return page ? lowmem_page_address(page) + offset : NULL;
  264. }
  265. int mthca_table_get_range(struct mthca_dev *dev, struct mthca_icm_table *table,
  266. int start, int end)
  267. {
  268. int inc = MTHCA_TABLE_CHUNK_SIZE / table->obj_size;
  269. int i, err;
  270. for (i = start; i <= end; i += inc) {
  271. err = mthca_table_get(dev, table, i);
  272. if (err)
  273. goto fail;
  274. }
  275. return 0;
  276. fail:
  277. while (i > start) {
  278. i -= inc;
  279. mthca_table_put(dev, table, i);
  280. }
  281. return err;
  282. }
  283. void mthca_table_put_range(struct mthca_dev *dev, struct mthca_icm_table *table,
  284. int start, int end)
  285. {
  286. int i;
  287. if (!mthca_is_memfree(dev))
  288. return;
  289. for (i = start; i <= end; i += MTHCA_TABLE_CHUNK_SIZE / table->obj_size)
  290. mthca_table_put(dev, table, i);
  291. }
  292. struct mthca_icm_table *mthca_alloc_icm_table(struct mthca_dev *dev,
  293. u64 virt, int obj_size,
  294. int nobj, int reserved,
  295. int use_lowmem, int use_coherent)
  296. {
  297. struct mthca_icm_table *table;
  298. int obj_per_chunk;
  299. int num_icm;
  300. unsigned chunk_size;
  301. int i;
  302. u8 status;
  303. obj_per_chunk = MTHCA_TABLE_CHUNK_SIZE / obj_size;
  304. num_icm = DIV_ROUND_UP(nobj, obj_per_chunk);
  305. table = kmalloc(sizeof *table + num_icm * sizeof *table->icm, GFP_KERNEL);
  306. if (!table)
  307. return NULL;
  308. table->virt = virt;
  309. table->num_icm = num_icm;
  310. table->num_obj = nobj;
  311. table->obj_size = obj_size;
  312. table->lowmem = use_lowmem;
  313. table->coherent = use_coherent;
  314. mutex_init(&table->mutex);
  315. for (i = 0; i < num_icm; ++i)
  316. table->icm[i] = NULL;
  317. for (i = 0; i * MTHCA_TABLE_CHUNK_SIZE < reserved * obj_size; ++i) {
  318. chunk_size = MTHCA_TABLE_CHUNK_SIZE;
  319. if ((i + 1) * MTHCA_TABLE_CHUNK_SIZE > nobj * obj_size)
  320. chunk_size = nobj * obj_size - i * MTHCA_TABLE_CHUNK_SIZE;
  321. table->icm[i] = mthca_alloc_icm(dev, chunk_size >> PAGE_SHIFT,
  322. (use_lowmem ? GFP_KERNEL : GFP_HIGHUSER) |
  323. __GFP_NOWARN, use_coherent);
  324. if (!table->icm[i])
  325. goto err;
  326. if (mthca_MAP_ICM(dev, table->icm[i], virt + i * MTHCA_TABLE_CHUNK_SIZE,
  327. &status) || status) {
  328. mthca_free_icm(dev, table->icm[i], table->coherent);
  329. table->icm[i] = NULL;
  330. goto err;
  331. }
  332. /*
  333. * Add a reference to this ICM chunk so that it never
  334. * gets freed (since it contains reserved firmware objects).
  335. */
  336. ++table->icm[i]->refcount;
  337. }
  338. return table;
  339. err:
  340. for (i = 0; i < num_icm; ++i)
  341. if (table->icm[i]) {
  342. mthca_UNMAP_ICM(dev, virt + i * MTHCA_TABLE_CHUNK_SIZE,
  343. MTHCA_TABLE_CHUNK_SIZE / MTHCA_ICM_PAGE_SIZE,
  344. &status);
  345. mthca_free_icm(dev, table->icm[i], table->coherent);
  346. }
  347. kfree(table);
  348. return NULL;
  349. }
  350. void mthca_free_icm_table(struct mthca_dev *dev, struct mthca_icm_table *table)
  351. {
  352. int i;
  353. u8 status;
  354. for (i = 0; i < table->num_icm; ++i)
  355. if (table->icm[i]) {
  356. mthca_UNMAP_ICM(dev, table->virt + i * MTHCA_TABLE_CHUNK_SIZE,
  357. MTHCA_TABLE_CHUNK_SIZE / MTHCA_ICM_PAGE_SIZE,
  358. &status);
  359. mthca_free_icm(dev, table->icm[i], table->coherent);
  360. }
  361. kfree(table);
  362. }
  363. static u64 mthca_uarc_virt(struct mthca_dev *dev, struct mthca_uar *uar, int page)
  364. {
  365. return dev->uar_table.uarc_base +
  366. uar->index * dev->uar_table.uarc_size +
  367. page * MTHCA_ICM_PAGE_SIZE;
  368. }
  369. int mthca_map_user_db(struct mthca_dev *dev, struct mthca_uar *uar,
  370. struct mthca_user_db_table *db_tab, int index, u64 uaddr)
  371. {
  372. struct page *pages[1];
  373. int ret = 0;
  374. u8 status;
  375. int i;
  376. if (!mthca_is_memfree(dev))
  377. return 0;
  378. if (index < 0 || index > dev->uar_table.uarc_size / 8)
  379. return -EINVAL;
  380. mutex_lock(&db_tab->mutex);
  381. i = index / MTHCA_DB_REC_PER_PAGE;
  382. if ((db_tab->page[i].refcount >= MTHCA_DB_REC_PER_PAGE) ||
  383. (db_tab->page[i].uvirt && db_tab->page[i].uvirt != uaddr) ||
  384. (uaddr & 4095)) {
  385. ret = -EINVAL;
  386. goto out;
  387. }
  388. if (db_tab->page[i].refcount) {
  389. ++db_tab->page[i].refcount;
  390. goto out;
  391. }
  392. ret = get_user_pages(current, current->mm, uaddr & PAGE_MASK, 1, 1, 0,
  393. pages, NULL);
  394. if (ret < 0)
  395. goto out;
  396. sg_set_page(&db_tab->page[i].mem, pages[0], MTHCA_ICM_PAGE_SIZE,
  397. uaddr & ~PAGE_MASK);
  398. ret = pci_map_sg(dev->pdev, &db_tab->page[i].mem, 1, PCI_DMA_TODEVICE);
  399. if (ret < 0) {
  400. put_page(pages[0]);
  401. goto out;
  402. }
  403. ret = mthca_MAP_ICM_page(dev, sg_dma_address(&db_tab->page[i].mem),
  404. mthca_uarc_virt(dev, uar, i), &status);
  405. if (!ret && status)
  406. ret = -EINVAL;
  407. if (ret) {
  408. pci_unmap_sg(dev->pdev, &db_tab->page[i].mem, 1, PCI_DMA_TODEVICE);
  409. put_page(sg_page(&db_tab->page[i].mem));
  410. goto out;
  411. }
  412. db_tab->page[i].uvirt = uaddr;
  413. db_tab->page[i].refcount = 1;
  414. out:
  415. mutex_unlock(&db_tab->mutex);
  416. return ret;
  417. }
  418. void mthca_unmap_user_db(struct mthca_dev *dev, struct mthca_uar *uar,
  419. struct mthca_user_db_table *db_tab, int index)
  420. {
  421. if (!mthca_is_memfree(dev))
  422. return;
  423. /*
  424. * To make our bookkeeping simpler, we don't unmap DB
  425. * pages until we clean up the whole db table.
  426. */
  427. mutex_lock(&db_tab->mutex);
  428. --db_tab->page[index / MTHCA_DB_REC_PER_PAGE].refcount;
  429. mutex_unlock(&db_tab->mutex);
  430. }
  431. struct mthca_user_db_table *mthca_init_user_db_tab(struct mthca_dev *dev)
  432. {
  433. struct mthca_user_db_table *db_tab;
  434. int npages;
  435. int i;
  436. if (!mthca_is_memfree(dev))
  437. return NULL;
  438. npages = dev->uar_table.uarc_size / MTHCA_ICM_PAGE_SIZE;
  439. db_tab = kmalloc(sizeof *db_tab + npages * sizeof *db_tab->page, GFP_KERNEL);
  440. if (!db_tab)
  441. return ERR_PTR(-ENOMEM);
  442. mutex_init(&db_tab->mutex);
  443. for (i = 0; i < npages; ++i) {
  444. db_tab->page[i].refcount = 0;
  445. db_tab->page[i].uvirt = 0;
  446. sg_init_table(&db_tab->page[i].mem, 1);
  447. }
  448. return db_tab;
  449. }
  450. void mthca_cleanup_user_db_tab(struct mthca_dev *dev, struct mthca_uar *uar,
  451. struct mthca_user_db_table *db_tab)
  452. {
  453. int i;
  454. u8 status;
  455. if (!mthca_is_memfree(dev))
  456. return;
  457. for (i = 0; i < dev->uar_table.uarc_size / MTHCA_ICM_PAGE_SIZE; ++i) {
  458. if (db_tab->page[i].uvirt) {
  459. mthca_UNMAP_ICM(dev, mthca_uarc_virt(dev, uar, i), 1, &status);
  460. pci_unmap_sg(dev->pdev, &db_tab->page[i].mem, 1, PCI_DMA_TODEVICE);
  461. put_page(sg_page(&db_tab->page[i].mem));
  462. }
  463. }
  464. kfree(db_tab);
  465. }
  466. int mthca_alloc_db(struct mthca_dev *dev, enum mthca_db_type type,
  467. u32 qn, __be32 **db)
  468. {
  469. int group;
  470. int start, end, dir;
  471. int i, j;
  472. struct mthca_db_page *page;
  473. int ret = 0;
  474. u8 status;
  475. mutex_lock(&dev->db_tab->mutex);
  476. switch (type) {
  477. case MTHCA_DB_TYPE_CQ_ARM:
  478. case MTHCA_DB_TYPE_SQ:
  479. group = 0;
  480. start = 0;
  481. end = dev->db_tab->max_group1;
  482. dir = 1;
  483. break;
  484. case MTHCA_DB_TYPE_CQ_SET_CI:
  485. case MTHCA_DB_TYPE_RQ:
  486. case MTHCA_DB_TYPE_SRQ:
  487. group = 1;
  488. start = dev->db_tab->npages - 1;
  489. end = dev->db_tab->min_group2;
  490. dir = -1;
  491. break;
  492. default:
  493. ret = -EINVAL;
  494. goto out;
  495. }
  496. for (i = start; i != end; i += dir)
  497. if (dev->db_tab->page[i].db_rec &&
  498. !bitmap_full(dev->db_tab->page[i].used,
  499. MTHCA_DB_REC_PER_PAGE)) {
  500. page = dev->db_tab->page + i;
  501. goto found;
  502. }
  503. for (i = start; i != end; i += dir)
  504. if (!dev->db_tab->page[i].db_rec) {
  505. page = dev->db_tab->page + i;
  506. goto alloc;
  507. }
  508. if (dev->db_tab->max_group1 >= dev->db_tab->min_group2 - 1) {
  509. ret = -ENOMEM;
  510. goto out;
  511. }
  512. if (group == 0)
  513. ++dev->db_tab->max_group1;
  514. else
  515. --dev->db_tab->min_group2;
  516. page = dev->db_tab->page + end;
  517. alloc:
  518. page->db_rec = dma_alloc_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
  519. &page->mapping, GFP_KERNEL);
  520. if (!page->db_rec) {
  521. ret = -ENOMEM;
  522. goto out;
  523. }
  524. memset(page->db_rec, 0, MTHCA_ICM_PAGE_SIZE);
  525. ret = mthca_MAP_ICM_page(dev, page->mapping,
  526. mthca_uarc_virt(dev, &dev->driver_uar, i), &status);
  527. if (!ret && status)
  528. ret = -EINVAL;
  529. if (ret) {
  530. dma_free_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
  531. page->db_rec, page->mapping);
  532. goto out;
  533. }
  534. bitmap_zero(page->used, MTHCA_DB_REC_PER_PAGE);
  535. found:
  536. j = find_first_zero_bit(page->used, MTHCA_DB_REC_PER_PAGE);
  537. set_bit(j, page->used);
  538. if (group == 1)
  539. j = MTHCA_DB_REC_PER_PAGE - 1 - j;
  540. ret = i * MTHCA_DB_REC_PER_PAGE + j;
  541. page->db_rec[j] = cpu_to_be64((qn << 8) | (type << 5));
  542. *db = (__be32 *) &page->db_rec[j];
  543. out:
  544. mutex_unlock(&dev->db_tab->mutex);
  545. return ret;
  546. }
  547. void mthca_free_db(struct mthca_dev *dev, int type, int db_index)
  548. {
  549. int i, j;
  550. struct mthca_db_page *page;
  551. u8 status;
  552. i = db_index / MTHCA_DB_REC_PER_PAGE;
  553. j = db_index % MTHCA_DB_REC_PER_PAGE;
  554. page = dev->db_tab->page + i;
  555. mutex_lock(&dev->db_tab->mutex);
  556. page->db_rec[j] = 0;
  557. if (i >= dev->db_tab->min_group2)
  558. j = MTHCA_DB_REC_PER_PAGE - 1 - j;
  559. clear_bit(j, page->used);
  560. if (bitmap_empty(page->used, MTHCA_DB_REC_PER_PAGE) &&
  561. i >= dev->db_tab->max_group1 - 1) {
  562. mthca_UNMAP_ICM(dev, mthca_uarc_virt(dev, &dev->driver_uar, i), 1, &status);
  563. dma_free_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
  564. page->db_rec, page->mapping);
  565. page->db_rec = NULL;
  566. if (i == dev->db_tab->max_group1) {
  567. --dev->db_tab->max_group1;
  568. /* XXX may be able to unmap more pages now */
  569. }
  570. if (i == dev->db_tab->min_group2)
  571. ++dev->db_tab->min_group2;
  572. }
  573. mutex_unlock(&dev->db_tab->mutex);
  574. }
  575. int mthca_init_db_tab(struct mthca_dev *dev)
  576. {
  577. int i;
  578. if (!mthca_is_memfree(dev))
  579. return 0;
  580. dev->db_tab = kmalloc(sizeof *dev->db_tab, GFP_KERNEL);
  581. if (!dev->db_tab)
  582. return -ENOMEM;
  583. mutex_init(&dev->db_tab->mutex);
  584. dev->db_tab->npages = dev->uar_table.uarc_size / MTHCA_ICM_PAGE_SIZE;
  585. dev->db_tab->max_group1 = 0;
  586. dev->db_tab->min_group2 = dev->db_tab->npages - 1;
  587. dev->db_tab->page = kmalloc(dev->db_tab->npages *
  588. sizeof *dev->db_tab->page,
  589. GFP_KERNEL);
  590. if (!dev->db_tab->page) {
  591. kfree(dev->db_tab);
  592. return -ENOMEM;
  593. }
  594. for (i = 0; i < dev->db_tab->npages; ++i)
  595. dev->db_tab->page[i].db_rec = NULL;
  596. return 0;
  597. }
  598. void mthca_cleanup_db_tab(struct mthca_dev *dev)
  599. {
  600. int i;
  601. u8 status;
  602. if (!mthca_is_memfree(dev))
  603. return;
  604. /*
  605. * Because we don't always free our UARC pages when they
  606. * become empty to make mthca_free_db() simpler we need to
  607. * make a sweep through the doorbell pages and free any
  608. * leftover pages now.
  609. */
  610. for (i = 0; i < dev->db_tab->npages; ++i) {
  611. if (!dev->db_tab->page[i].db_rec)
  612. continue;
  613. if (!bitmap_empty(dev->db_tab->page[i].used, MTHCA_DB_REC_PER_PAGE))
  614. mthca_warn(dev, "Kernel UARC page %d not empty\n", i);
  615. mthca_UNMAP_ICM(dev, mthca_uarc_virt(dev, &dev->driver_uar, i), 1, &status);
  616. dma_free_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
  617. dev->db_tab->page[i].db_rec,
  618. dev->db_tab->page[i].mapping);
  619. }
  620. kfree(dev->db_tab->page);
  621. kfree(dev->db_tab);
  622. }