mthca_main.c 36 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. */
  34. #include <linux/module.h>
  35. #include <linux/init.h>
  36. #include <linux/errno.h>
  37. #include <linux/pci.h>
  38. #include <linux/interrupt.h>
  39. #include <linux/gfp.h>
  40. #include "mthca_dev.h"
  41. #include "mthca_config_reg.h"
  42. #include "mthca_cmd.h"
  43. #include "mthca_profile.h"
  44. #include "mthca_memfree.h"
  45. #include "mthca_wqe.h"
  46. MODULE_AUTHOR("Roland Dreier");
  47. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  48. MODULE_LICENSE("Dual BSD/GPL");
  49. MODULE_VERSION(DRV_VERSION);
  50. #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
  51. int mthca_debug_level = 0;
  52. module_param_named(debug_level, mthca_debug_level, int, 0644);
  53. MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  54. #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
  55. #ifdef CONFIG_PCI_MSI
  56. static int msi_x = 1;
  57. module_param(msi_x, int, 0444);
  58. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  59. #else /* CONFIG_PCI_MSI */
  60. #define msi_x (0)
  61. #endif /* CONFIG_PCI_MSI */
  62. static int tune_pci = 0;
  63. module_param(tune_pci, int, 0444);
  64. MODULE_PARM_DESC(tune_pci, "increase PCI burst from the default set by BIOS if nonzero");
  65. DEFINE_MUTEX(mthca_device_mutex);
  66. #define MTHCA_DEFAULT_NUM_QP (1 << 16)
  67. #define MTHCA_DEFAULT_RDB_PER_QP (1 << 2)
  68. #define MTHCA_DEFAULT_NUM_CQ (1 << 16)
  69. #define MTHCA_DEFAULT_NUM_MCG (1 << 13)
  70. #define MTHCA_DEFAULT_NUM_MPT (1 << 17)
  71. #define MTHCA_DEFAULT_NUM_MTT (1 << 20)
  72. #define MTHCA_DEFAULT_NUM_UDAV (1 << 15)
  73. #define MTHCA_DEFAULT_NUM_RESERVED_MTTS (1 << 18)
  74. #define MTHCA_DEFAULT_NUM_UARC_SIZE (1 << 18)
  75. static struct mthca_profile hca_profile = {
  76. .num_qp = MTHCA_DEFAULT_NUM_QP,
  77. .rdb_per_qp = MTHCA_DEFAULT_RDB_PER_QP,
  78. .num_cq = MTHCA_DEFAULT_NUM_CQ,
  79. .num_mcg = MTHCA_DEFAULT_NUM_MCG,
  80. .num_mpt = MTHCA_DEFAULT_NUM_MPT,
  81. .num_mtt = MTHCA_DEFAULT_NUM_MTT,
  82. .num_udav = MTHCA_DEFAULT_NUM_UDAV, /* Tavor only */
  83. .fmr_reserved_mtts = MTHCA_DEFAULT_NUM_RESERVED_MTTS, /* Tavor only */
  84. .uarc_size = MTHCA_DEFAULT_NUM_UARC_SIZE, /* Arbel only */
  85. };
  86. module_param_named(num_qp, hca_profile.num_qp, int, 0444);
  87. MODULE_PARM_DESC(num_qp, "maximum number of QPs per HCA");
  88. module_param_named(rdb_per_qp, hca_profile.rdb_per_qp, int, 0444);
  89. MODULE_PARM_DESC(rdb_per_qp, "number of RDB buffers per QP");
  90. module_param_named(num_cq, hca_profile.num_cq, int, 0444);
  91. MODULE_PARM_DESC(num_cq, "maximum number of CQs per HCA");
  92. module_param_named(num_mcg, hca_profile.num_mcg, int, 0444);
  93. MODULE_PARM_DESC(num_mcg, "maximum number of multicast groups per HCA");
  94. module_param_named(num_mpt, hca_profile.num_mpt, int, 0444);
  95. MODULE_PARM_DESC(num_mpt,
  96. "maximum number of memory protection table entries per HCA");
  97. module_param_named(num_mtt, hca_profile.num_mtt, int, 0444);
  98. MODULE_PARM_DESC(num_mtt,
  99. "maximum number of memory translation table segments per HCA");
  100. module_param_named(num_udav, hca_profile.num_udav, int, 0444);
  101. MODULE_PARM_DESC(num_udav, "maximum number of UD address vectors per HCA");
  102. module_param_named(fmr_reserved_mtts, hca_profile.fmr_reserved_mtts, int, 0444);
  103. MODULE_PARM_DESC(fmr_reserved_mtts,
  104. "number of memory translation table segments reserved for FMR");
  105. static int log_mtts_per_seg = ilog2(MTHCA_MTT_SEG_SIZE / 8);
  106. module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
  107. MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-5)");
  108. static char mthca_version[] __devinitdata =
  109. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  110. DRV_VERSION " (" DRV_RELDATE ")\n";
  111. static int mthca_tune_pci(struct mthca_dev *mdev)
  112. {
  113. if (!tune_pci)
  114. return 0;
  115. /* First try to max out Read Byte Count */
  116. if (pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX)) {
  117. if (pcix_set_mmrbc(mdev->pdev, pcix_get_max_mmrbc(mdev->pdev))) {
  118. mthca_err(mdev, "Couldn't set PCI-X max read count, "
  119. "aborting.\n");
  120. return -ENODEV;
  121. }
  122. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  123. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  124. if (pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP)) {
  125. if (pcie_set_readrq(mdev->pdev, 4096)) {
  126. mthca_err(mdev, "Couldn't write PCI Express read request, "
  127. "aborting.\n");
  128. return -ENODEV;
  129. }
  130. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  131. mthca_info(mdev, "No PCI Express capability, "
  132. "not setting Max Read Request Size.\n");
  133. return 0;
  134. }
  135. static int mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  136. {
  137. int err;
  138. u8 status;
  139. mdev->limits.mtt_seg_size = (1 << log_mtts_per_seg) * 8;
  140. err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
  141. if (err) {
  142. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  143. return err;
  144. }
  145. if (status) {
  146. mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
  147. "aborting.\n", status);
  148. return -EINVAL;
  149. }
  150. if (dev_lim->min_page_sz > PAGE_SIZE) {
  151. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  152. "kernel PAGE_SIZE of %ld, aborting.\n",
  153. dev_lim->min_page_sz, PAGE_SIZE);
  154. return -ENODEV;
  155. }
  156. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  157. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  158. "aborting.\n",
  159. dev_lim->num_ports, MTHCA_MAX_PORTS);
  160. return -ENODEV;
  161. }
  162. if (dev_lim->uar_size > pci_resource_len(mdev->pdev, 2)) {
  163. mthca_err(mdev, "HCA reported UAR size of 0x%x bigger than "
  164. "PCI resource 2 size of 0x%llx, aborting.\n",
  165. dev_lim->uar_size,
  166. (unsigned long long)pci_resource_len(mdev->pdev, 2));
  167. return -ENODEV;
  168. }
  169. mdev->limits.num_ports = dev_lim->num_ports;
  170. mdev->limits.vl_cap = dev_lim->max_vl;
  171. mdev->limits.mtu_cap = dev_lim->max_mtu;
  172. mdev->limits.gid_table_len = dev_lim->max_gids;
  173. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  174. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  175. /*
  176. * Need to allow for worst case send WQE overhead and check
  177. * whether max_desc_sz imposes a lower limit than max_sg; UD
  178. * send has the biggest overhead.
  179. */
  180. mdev->limits.max_sg = min_t(int, dev_lim->max_sg,
  181. (dev_lim->max_desc_sz -
  182. sizeof (struct mthca_next_seg) -
  183. (mthca_is_memfree(mdev) ?
  184. sizeof (struct mthca_arbel_ud_seg) :
  185. sizeof (struct mthca_tavor_ud_seg))) /
  186. sizeof (struct mthca_data_seg));
  187. mdev->limits.max_wqes = dev_lim->max_qp_sz;
  188. mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
  189. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  190. mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
  191. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  192. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  193. mdev->limits.max_desc_sz = dev_lim->max_desc_sz;
  194. mdev->limits.max_srq_sge = mthca_max_srq_sge(mdev);
  195. /*
  196. * Subtract 1 from the limit because we need to allocate a
  197. * spare CQE so the HCA HW can tell the difference between an
  198. * empty CQ and a full CQ.
  199. */
  200. mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
  201. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  202. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  203. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  204. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  205. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  206. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  207. mdev->limits.port_width_cap = dev_lim->max_port_width;
  208. mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1);
  209. mdev->limits.flags = dev_lim->flags;
  210. /*
  211. * For old FW that doesn't return static rate support, use a
  212. * value of 0x3 (only static rate values of 0 or 1 are handled),
  213. * except on Sinai, where even old FW can handle static rate
  214. * values of 2 and 3.
  215. */
  216. if (dev_lim->stat_rate_support)
  217. mdev->limits.stat_rate_support = dev_lim->stat_rate_support;
  218. else if (mdev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
  219. mdev->limits.stat_rate_support = 0xf;
  220. else
  221. mdev->limits.stat_rate_support = 0x3;
  222. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  223. May be doable since hardware supports it for SRQ.
  224. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  225. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  226. supported by driver. */
  227. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  228. IB_DEVICE_PORT_ACTIVE_EVENT |
  229. IB_DEVICE_SYS_IMAGE_GUID |
  230. IB_DEVICE_RC_RNR_NAK_GEN;
  231. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  232. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  233. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  234. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  235. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  236. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  237. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  238. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  239. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  240. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  241. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  242. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  243. if (mthca_is_memfree(mdev))
  244. if (dev_lim->flags & DEV_LIM_FLAG_IPOIB_CSUM)
  245. mdev->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
  246. return 0;
  247. }
  248. static int mthca_init_tavor(struct mthca_dev *mdev)
  249. {
  250. s64 size;
  251. u8 status;
  252. int err;
  253. struct mthca_dev_lim dev_lim;
  254. struct mthca_profile profile;
  255. struct mthca_init_hca_param init_hca;
  256. err = mthca_SYS_EN(mdev, &status);
  257. if (err) {
  258. mthca_err(mdev, "SYS_EN command failed, aborting.\n");
  259. return err;
  260. }
  261. if (status) {
  262. mthca_err(mdev, "SYS_EN returned status 0x%02x, "
  263. "aborting.\n", status);
  264. return -EINVAL;
  265. }
  266. err = mthca_QUERY_FW(mdev, &status);
  267. if (err) {
  268. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  269. goto err_disable;
  270. }
  271. if (status) {
  272. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  273. "aborting.\n", status);
  274. err = -EINVAL;
  275. goto err_disable;
  276. }
  277. err = mthca_QUERY_DDR(mdev, &status);
  278. if (err) {
  279. mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
  280. goto err_disable;
  281. }
  282. if (status) {
  283. mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
  284. "aborting.\n", status);
  285. err = -EINVAL;
  286. goto err_disable;
  287. }
  288. err = mthca_dev_lim(mdev, &dev_lim);
  289. if (err) {
  290. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  291. goto err_disable;
  292. }
  293. profile = hca_profile;
  294. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  295. profile.uarc_size = 0;
  296. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  297. profile.num_srq = dev_lim.max_srqs;
  298. size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  299. if (size < 0) {
  300. err = size;
  301. goto err_disable;
  302. }
  303. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  304. if (err) {
  305. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  306. goto err_disable;
  307. }
  308. if (status) {
  309. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  310. "aborting.\n", status);
  311. err = -EINVAL;
  312. goto err_disable;
  313. }
  314. return 0;
  315. err_disable:
  316. mthca_SYS_DIS(mdev, &status);
  317. return err;
  318. }
  319. static int mthca_load_fw(struct mthca_dev *mdev)
  320. {
  321. u8 status;
  322. int err;
  323. /* FIXME: use HCA-attached memory for FW if present */
  324. mdev->fw.arbel.fw_icm =
  325. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  326. GFP_HIGHUSER | __GFP_NOWARN, 0);
  327. if (!mdev->fw.arbel.fw_icm) {
  328. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  329. return -ENOMEM;
  330. }
  331. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
  332. if (err) {
  333. mthca_err(mdev, "MAP_FA command failed, aborting.\n");
  334. goto err_free;
  335. }
  336. if (status) {
  337. mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
  338. err = -EINVAL;
  339. goto err_free;
  340. }
  341. err = mthca_RUN_FW(mdev, &status);
  342. if (err) {
  343. mthca_err(mdev, "RUN_FW command failed, aborting.\n");
  344. goto err_unmap_fa;
  345. }
  346. if (status) {
  347. mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
  348. err = -EINVAL;
  349. goto err_unmap_fa;
  350. }
  351. return 0;
  352. err_unmap_fa:
  353. mthca_UNMAP_FA(mdev, &status);
  354. err_free:
  355. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  356. return err;
  357. }
  358. static int mthca_init_icm(struct mthca_dev *mdev,
  359. struct mthca_dev_lim *dev_lim,
  360. struct mthca_init_hca_param *init_hca,
  361. u64 icm_size)
  362. {
  363. u64 aux_pages;
  364. u8 status;
  365. int err;
  366. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
  367. if (err) {
  368. mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
  369. return err;
  370. }
  371. if (status) {
  372. mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
  373. "aborting.\n", status);
  374. return -EINVAL;
  375. }
  376. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  377. (unsigned long long) icm_size >> 10,
  378. (unsigned long long) aux_pages << 2);
  379. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  380. GFP_HIGHUSER | __GFP_NOWARN, 0);
  381. if (!mdev->fw.arbel.aux_icm) {
  382. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  383. return -ENOMEM;
  384. }
  385. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
  386. if (err) {
  387. mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
  388. goto err_free_aux;
  389. }
  390. if (status) {
  391. mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
  392. err = -EINVAL;
  393. goto err_free_aux;
  394. }
  395. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  396. if (err) {
  397. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  398. goto err_unmap_aux;
  399. }
  400. /* CPU writes to non-reserved MTTs, while HCA might DMA to reserved mtts */
  401. mdev->limits.reserved_mtts = ALIGN(mdev->limits.reserved_mtts * mdev->limits.mtt_seg_size,
  402. dma_get_cache_alignment()) / mdev->limits.mtt_seg_size;
  403. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  404. mdev->limits.mtt_seg_size,
  405. mdev->limits.num_mtt_segs,
  406. mdev->limits.reserved_mtts,
  407. 1, 0);
  408. if (!mdev->mr_table.mtt_table) {
  409. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  410. err = -ENOMEM;
  411. goto err_unmap_eq;
  412. }
  413. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  414. dev_lim->mpt_entry_sz,
  415. mdev->limits.num_mpts,
  416. mdev->limits.reserved_mrws,
  417. 1, 1);
  418. if (!mdev->mr_table.mpt_table) {
  419. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  420. err = -ENOMEM;
  421. goto err_unmap_mtt;
  422. }
  423. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  424. dev_lim->qpc_entry_sz,
  425. mdev->limits.num_qps,
  426. mdev->limits.reserved_qps,
  427. 0, 0);
  428. if (!mdev->qp_table.qp_table) {
  429. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  430. err = -ENOMEM;
  431. goto err_unmap_mpt;
  432. }
  433. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  434. dev_lim->eqpc_entry_sz,
  435. mdev->limits.num_qps,
  436. mdev->limits.reserved_qps,
  437. 0, 0);
  438. if (!mdev->qp_table.eqp_table) {
  439. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  440. err = -ENOMEM;
  441. goto err_unmap_qp;
  442. }
  443. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  444. MTHCA_RDB_ENTRY_SIZE,
  445. mdev->limits.num_qps <<
  446. mdev->qp_table.rdb_shift, 0,
  447. 0, 0);
  448. if (!mdev->qp_table.rdb_table) {
  449. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  450. err = -ENOMEM;
  451. goto err_unmap_eqp;
  452. }
  453. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  454. dev_lim->cqc_entry_sz,
  455. mdev->limits.num_cqs,
  456. mdev->limits.reserved_cqs,
  457. 0, 0);
  458. if (!mdev->cq_table.table) {
  459. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  460. err = -ENOMEM;
  461. goto err_unmap_rdb;
  462. }
  463. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  464. mdev->srq_table.table =
  465. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  466. dev_lim->srq_entry_sz,
  467. mdev->limits.num_srqs,
  468. mdev->limits.reserved_srqs,
  469. 0, 0);
  470. if (!mdev->srq_table.table) {
  471. mthca_err(mdev, "Failed to map SRQ context memory, "
  472. "aborting.\n");
  473. err = -ENOMEM;
  474. goto err_unmap_cq;
  475. }
  476. }
  477. /*
  478. * It's not strictly required, but for simplicity just map the
  479. * whole multicast group table now. The table isn't very big
  480. * and it's a lot easier than trying to track ref counts.
  481. */
  482. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  483. MTHCA_MGM_ENTRY_SIZE,
  484. mdev->limits.num_mgms +
  485. mdev->limits.num_amgms,
  486. mdev->limits.num_mgms +
  487. mdev->limits.num_amgms,
  488. 0, 0);
  489. if (!mdev->mcg_table.table) {
  490. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  491. err = -ENOMEM;
  492. goto err_unmap_srq;
  493. }
  494. return 0;
  495. err_unmap_srq:
  496. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  497. mthca_free_icm_table(mdev, mdev->srq_table.table);
  498. err_unmap_cq:
  499. mthca_free_icm_table(mdev, mdev->cq_table.table);
  500. err_unmap_rdb:
  501. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  502. err_unmap_eqp:
  503. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  504. err_unmap_qp:
  505. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  506. err_unmap_mpt:
  507. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  508. err_unmap_mtt:
  509. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  510. err_unmap_eq:
  511. mthca_unmap_eq_icm(mdev);
  512. err_unmap_aux:
  513. mthca_UNMAP_ICM_AUX(mdev, &status);
  514. err_free_aux:
  515. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
  516. return err;
  517. }
  518. static void mthca_free_icms(struct mthca_dev *mdev)
  519. {
  520. u8 status;
  521. mthca_free_icm_table(mdev, mdev->mcg_table.table);
  522. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  523. mthca_free_icm_table(mdev, mdev->srq_table.table);
  524. mthca_free_icm_table(mdev, mdev->cq_table.table);
  525. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  526. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  527. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  528. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  529. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  530. mthca_unmap_eq_icm(mdev);
  531. mthca_UNMAP_ICM_AUX(mdev, &status);
  532. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
  533. }
  534. static int mthca_init_arbel(struct mthca_dev *mdev)
  535. {
  536. struct mthca_dev_lim dev_lim;
  537. struct mthca_profile profile;
  538. struct mthca_init_hca_param init_hca;
  539. s64 icm_size;
  540. u8 status;
  541. int err;
  542. err = mthca_QUERY_FW(mdev, &status);
  543. if (err) {
  544. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  545. return err;
  546. }
  547. if (status) {
  548. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  549. "aborting.\n", status);
  550. return -EINVAL;
  551. }
  552. err = mthca_ENABLE_LAM(mdev, &status);
  553. if (err) {
  554. mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
  555. return err;
  556. }
  557. if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
  558. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  559. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  560. } else if (status) {
  561. mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
  562. "aborting.\n", status);
  563. return -EINVAL;
  564. }
  565. err = mthca_load_fw(mdev);
  566. if (err) {
  567. mthca_err(mdev, "Failed to start FW, aborting.\n");
  568. goto err_disable;
  569. }
  570. err = mthca_dev_lim(mdev, &dev_lim);
  571. if (err) {
  572. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  573. goto err_stop_fw;
  574. }
  575. profile = hca_profile;
  576. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  577. profile.num_udav = 0;
  578. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  579. profile.num_srq = dev_lim.max_srqs;
  580. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  581. if (icm_size < 0) {
  582. err = icm_size;
  583. goto err_stop_fw;
  584. }
  585. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  586. if (err)
  587. goto err_stop_fw;
  588. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  589. if (err) {
  590. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  591. goto err_free_icm;
  592. }
  593. if (status) {
  594. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  595. "aborting.\n", status);
  596. err = -EINVAL;
  597. goto err_free_icm;
  598. }
  599. return 0;
  600. err_free_icm:
  601. mthca_free_icms(mdev);
  602. err_stop_fw:
  603. mthca_UNMAP_FA(mdev, &status);
  604. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  605. err_disable:
  606. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  607. mthca_DISABLE_LAM(mdev, &status);
  608. return err;
  609. }
  610. static void mthca_close_hca(struct mthca_dev *mdev)
  611. {
  612. u8 status;
  613. mthca_CLOSE_HCA(mdev, 0, &status);
  614. if (mthca_is_memfree(mdev)) {
  615. mthca_free_icms(mdev);
  616. mthca_UNMAP_FA(mdev, &status);
  617. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  618. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  619. mthca_DISABLE_LAM(mdev, &status);
  620. } else
  621. mthca_SYS_DIS(mdev, &status);
  622. }
  623. static int mthca_init_hca(struct mthca_dev *mdev)
  624. {
  625. u8 status;
  626. int err;
  627. struct mthca_adapter adapter;
  628. if (mthca_is_memfree(mdev))
  629. err = mthca_init_arbel(mdev);
  630. else
  631. err = mthca_init_tavor(mdev);
  632. if (err)
  633. return err;
  634. err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
  635. if (err) {
  636. mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
  637. goto err_close;
  638. }
  639. if (status) {
  640. mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
  641. "aborting.\n", status);
  642. err = -EINVAL;
  643. goto err_close;
  644. }
  645. mdev->eq_table.inta_pin = adapter.inta_pin;
  646. if (!mthca_is_memfree(mdev))
  647. mdev->rev_id = adapter.revision_id;
  648. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  649. return 0;
  650. err_close:
  651. mthca_close_hca(mdev);
  652. return err;
  653. }
  654. static int mthca_setup_hca(struct mthca_dev *dev)
  655. {
  656. int err;
  657. u8 status;
  658. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  659. err = mthca_init_uar_table(dev);
  660. if (err) {
  661. mthca_err(dev, "Failed to initialize "
  662. "user access region table, aborting.\n");
  663. return err;
  664. }
  665. err = mthca_uar_alloc(dev, &dev->driver_uar);
  666. if (err) {
  667. mthca_err(dev, "Failed to allocate driver access region, "
  668. "aborting.\n");
  669. goto err_uar_table_free;
  670. }
  671. dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  672. if (!dev->kar) {
  673. mthca_err(dev, "Couldn't map kernel access region, "
  674. "aborting.\n");
  675. err = -ENOMEM;
  676. goto err_uar_free;
  677. }
  678. err = mthca_init_pd_table(dev);
  679. if (err) {
  680. mthca_err(dev, "Failed to initialize "
  681. "protection domain table, aborting.\n");
  682. goto err_kar_unmap;
  683. }
  684. err = mthca_init_mr_table(dev);
  685. if (err) {
  686. mthca_err(dev, "Failed to initialize "
  687. "memory region table, aborting.\n");
  688. goto err_pd_table_free;
  689. }
  690. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  691. if (err) {
  692. mthca_err(dev, "Failed to create driver PD, "
  693. "aborting.\n");
  694. goto err_mr_table_free;
  695. }
  696. err = mthca_init_eq_table(dev);
  697. if (err) {
  698. mthca_err(dev, "Failed to initialize "
  699. "event queue table, aborting.\n");
  700. goto err_pd_free;
  701. }
  702. err = mthca_cmd_use_events(dev);
  703. if (err) {
  704. mthca_err(dev, "Failed to switch to event-driven "
  705. "firmware commands, aborting.\n");
  706. goto err_eq_table_free;
  707. }
  708. err = mthca_NOP(dev, &status);
  709. if (err || status) {
  710. if (dev->mthca_flags & MTHCA_FLAG_MSI_X) {
  711. mthca_warn(dev, "NOP command failed to generate interrupt "
  712. "(IRQ %d).\n",
  713. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector);
  714. mthca_warn(dev, "Trying again with MSI-X disabled.\n");
  715. } else {
  716. mthca_err(dev, "NOP command failed to generate interrupt "
  717. "(IRQ %d), aborting.\n",
  718. dev->pdev->irq);
  719. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  720. }
  721. goto err_cmd_poll;
  722. }
  723. mthca_dbg(dev, "NOP command IRQ test passed\n");
  724. err = mthca_init_cq_table(dev);
  725. if (err) {
  726. mthca_err(dev, "Failed to initialize "
  727. "completion queue table, aborting.\n");
  728. goto err_cmd_poll;
  729. }
  730. err = mthca_init_srq_table(dev);
  731. if (err) {
  732. mthca_err(dev, "Failed to initialize "
  733. "shared receive queue table, aborting.\n");
  734. goto err_cq_table_free;
  735. }
  736. err = mthca_init_qp_table(dev);
  737. if (err) {
  738. mthca_err(dev, "Failed to initialize "
  739. "queue pair table, aborting.\n");
  740. goto err_srq_table_free;
  741. }
  742. err = mthca_init_av_table(dev);
  743. if (err) {
  744. mthca_err(dev, "Failed to initialize "
  745. "address vector table, aborting.\n");
  746. goto err_qp_table_free;
  747. }
  748. err = mthca_init_mcg_table(dev);
  749. if (err) {
  750. mthca_err(dev, "Failed to initialize "
  751. "multicast group table, aborting.\n");
  752. goto err_av_table_free;
  753. }
  754. return 0;
  755. err_av_table_free:
  756. mthca_cleanup_av_table(dev);
  757. err_qp_table_free:
  758. mthca_cleanup_qp_table(dev);
  759. err_srq_table_free:
  760. mthca_cleanup_srq_table(dev);
  761. err_cq_table_free:
  762. mthca_cleanup_cq_table(dev);
  763. err_cmd_poll:
  764. mthca_cmd_use_polling(dev);
  765. err_eq_table_free:
  766. mthca_cleanup_eq_table(dev);
  767. err_pd_free:
  768. mthca_pd_free(dev, &dev->driver_pd);
  769. err_mr_table_free:
  770. mthca_cleanup_mr_table(dev);
  771. err_pd_table_free:
  772. mthca_cleanup_pd_table(dev);
  773. err_kar_unmap:
  774. iounmap(dev->kar);
  775. err_uar_free:
  776. mthca_uar_free(dev, &dev->driver_uar);
  777. err_uar_table_free:
  778. mthca_cleanup_uar_table(dev);
  779. return err;
  780. }
  781. static int mthca_enable_msi_x(struct mthca_dev *mdev)
  782. {
  783. struct msix_entry entries[3];
  784. int err;
  785. entries[0].entry = 0;
  786. entries[1].entry = 1;
  787. entries[2].entry = 2;
  788. err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
  789. if (err) {
  790. if (err > 0)
  791. mthca_info(mdev, "Only %d MSI-X vectors available, "
  792. "not using MSI-X\n", err);
  793. return err;
  794. }
  795. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
  796. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
  797. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
  798. return 0;
  799. }
  800. /* Types of supported HCA */
  801. enum {
  802. TAVOR, /* MT23108 */
  803. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  804. ARBEL_NATIVE, /* MT25208 with extended features */
  805. SINAI /* MT25204 */
  806. };
  807. #define MTHCA_FW_VER(major, minor, subminor) \
  808. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  809. static struct {
  810. u64 latest_fw;
  811. u32 flags;
  812. } mthca_hca_table[] = {
  813. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 5, 0),
  814. .flags = 0 },
  815. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 8, 200),
  816. .flags = MTHCA_FLAG_PCIE },
  817. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 3, 0),
  818. .flags = MTHCA_FLAG_MEMFREE |
  819. MTHCA_FLAG_PCIE },
  820. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 2, 0),
  821. .flags = MTHCA_FLAG_MEMFREE |
  822. MTHCA_FLAG_PCIE |
  823. MTHCA_FLAG_SINAI_OPT }
  824. };
  825. static int __mthca_init_one(struct pci_dev *pdev, int hca_type)
  826. {
  827. int ddr_hidden = 0;
  828. int err;
  829. struct mthca_dev *mdev;
  830. printk(KERN_INFO PFX "Initializing %s\n",
  831. pci_name(pdev));
  832. err = pci_enable_device(pdev);
  833. if (err) {
  834. dev_err(&pdev->dev, "Cannot enable PCI device, "
  835. "aborting.\n");
  836. return err;
  837. }
  838. /*
  839. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  840. * be present)
  841. */
  842. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  843. pci_resource_len(pdev, 0) != 1 << 20) {
  844. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  845. err = -ENODEV;
  846. goto err_disable_pdev;
  847. }
  848. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  849. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  850. err = -ENODEV;
  851. goto err_disable_pdev;
  852. }
  853. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  854. ddr_hidden = 1;
  855. err = pci_request_regions(pdev, DRV_NAME);
  856. if (err) {
  857. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  858. "aborting.\n");
  859. goto err_disable_pdev;
  860. }
  861. pci_set_master(pdev);
  862. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  863. if (err) {
  864. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  865. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  866. if (err) {
  867. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  868. goto err_free_res;
  869. }
  870. }
  871. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
  872. if (err) {
  873. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  874. "consistent PCI DMA mask.\n");
  875. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  876. if (err) {
  877. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  878. "aborting.\n");
  879. goto err_free_res;
  880. }
  881. }
  882. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  883. if (!mdev) {
  884. dev_err(&pdev->dev, "Device struct alloc failed, "
  885. "aborting.\n");
  886. err = -ENOMEM;
  887. goto err_free_res;
  888. }
  889. mdev->pdev = pdev;
  890. mdev->mthca_flags = mthca_hca_table[hca_type].flags;
  891. if (ddr_hidden)
  892. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  893. /*
  894. * Now reset the HCA before we touch the PCI capabilities or
  895. * attempt a firmware command, since a boot ROM may have left
  896. * the HCA in an undefined state.
  897. */
  898. err = mthca_reset(mdev);
  899. if (err) {
  900. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  901. goto err_free_dev;
  902. }
  903. if (mthca_cmd_init(mdev)) {
  904. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  905. goto err_free_dev;
  906. }
  907. err = mthca_tune_pci(mdev);
  908. if (err)
  909. goto err_cmd;
  910. err = mthca_init_hca(mdev);
  911. if (err)
  912. goto err_cmd;
  913. if (mdev->fw_ver < mthca_hca_table[hca_type].latest_fw) {
  914. mthca_warn(mdev, "HCA FW version %d.%d.%03d is old (%d.%d.%03d is current).\n",
  915. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  916. (int) (mdev->fw_ver & 0xffff),
  917. (int) (mthca_hca_table[hca_type].latest_fw >> 32),
  918. (int) (mthca_hca_table[hca_type].latest_fw >> 16) & 0xffff,
  919. (int) (mthca_hca_table[hca_type].latest_fw & 0xffff));
  920. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  921. }
  922. if (msi_x && !mthca_enable_msi_x(mdev))
  923. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  924. err = mthca_setup_hca(mdev);
  925. if (err == -EBUSY && (mdev->mthca_flags & MTHCA_FLAG_MSI_X)) {
  926. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  927. pci_disable_msix(pdev);
  928. mdev->mthca_flags &= ~MTHCA_FLAG_MSI_X;
  929. err = mthca_setup_hca(mdev);
  930. }
  931. if (err)
  932. goto err_close;
  933. err = mthca_register_device(mdev);
  934. if (err)
  935. goto err_cleanup;
  936. err = mthca_create_agents(mdev);
  937. if (err)
  938. goto err_unregister;
  939. pci_set_drvdata(pdev, mdev);
  940. mdev->hca_type = hca_type;
  941. mdev->active = true;
  942. return 0;
  943. err_unregister:
  944. mthca_unregister_device(mdev);
  945. err_cleanup:
  946. mthca_cleanup_mcg_table(mdev);
  947. mthca_cleanup_av_table(mdev);
  948. mthca_cleanup_qp_table(mdev);
  949. mthca_cleanup_srq_table(mdev);
  950. mthca_cleanup_cq_table(mdev);
  951. mthca_cmd_use_polling(mdev);
  952. mthca_cleanup_eq_table(mdev);
  953. mthca_pd_free(mdev, &mdev->driver_pd);
  954. mthca_cleanup_mr_table(mdev);
  955. mthca_cleanup_pd_table(mdev);
  956. mthca_cleanup_uar_table(mdev);
  957. err_close:
  958. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  959. pci_disable_msix(pdev);
  960. mthca_close_hca(mdev);
  961. err_cmd:
  962. mthca_cmd_cleanup(mdev);
  963. err_free_dev:
  964. ib_dealloc_device(&mdev->ib_dev);
  965. err_free_res:
  966. pci_release_regions(pdev);
  967. err_disable_pdev:
  968. pci_disable_device(pdev);
  969. pci_set_drvdata(pdev, NULL);
  970. return err;
  971. }
  972. static void __mthca_remove_one(struct pci_dev *pdev)
  973. {
  974. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  975. u8 status;
  976. int p;
  977. if (mdev) {
  978. mthca_free_agents(mdev);
  979. mthca_unregister_device(mdev);
  980. for (p = 1; p <= mdev->limits.num_ports; ++p)
  981. mthca_CLOSE_IB(mdev, p, &status);
  982. mthca_cleanup_mcg_table(mdev);
  983. mthca_cleanup_av_table(mdev);
  984. mthca_cleanup_qp_table(mdev);
  985. mthca_cleanup_srq_table(mdev);
  986. mthca_cleanup_cq_table(mdev);
  987. mthca_cmd_use_polling(mdev);
  988. mthca_cleanup_eq_table(mdev);
  989. mthca_pd_free(mdev, &mdev->driver_pd);
  990. mthca_cleanup_mr_table(mdev);
  991. mthca_cleanup_pd_table(mdev);
  992. iounmap(mdev->kar);
  993. mthca_uar_free(mdev, &mdev->driver_uar);
  994. mthca_cleanup_uar_table(mdev);
  995. mthca_close_hca(mdev);
  996. mthca_cmd_cleanup(mdev);
  997. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  998. pci_disable_msix(pdev);
  999. ib_dealloc_device(&mdev->ib_dev);
  1000. pci_release_regions(pdev);
  1001. pci_disable_device(pdev);
  1002. pci_set_drvdata(pdev, NULL);
  1003. }
  1004. }
  1005. int __mthca_restart_one(struct pci_dev *pdev)
  1006. {
  1007. struct mthca_dev *mdev;
  1008. int hca_type;
  1009. mdev = pci_get_drvdata(pdev);
  1010. if (!mdev)
  1011. return -ENODEV;
  1012. hca_type = mdev->hca_type;
  1013. __mthca_remove_one(pdev);
  1014. return __mthca_init_one(pdev, hca_type);
  1015. }
  1016. static int __devinit mthca_init_one(struct pci_dev *pdev,
  1017. const struct pci_device_id *id)
  1018. {
  1019. int ret;
  1020. mutex_lock(&mthca_device_mutex);
  1021. printk_once(KERN_INFO "%s", mthca_version);
  1022. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  1023. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  1024. pci_name(pdev), id->driver_data);
  1025. mutex_unlock(&mthca_device_mutex);
  1026. return -ENODEV;
  1027. }
  1028. ret = __mthca_init_one(pdev, id->driver_data);
  1029. mutex_unlock(&mthca_device_mutex);
  1030. return ret;
  1031. }
  1032. static void __devexit mthca_remove_one(struct pci_dev *pdev)
  1033. {
  1034. mutex_lock(&mthca_device_mutex);
  1035. __mthca_remove_one(pdev);
  1036. mutex_unlock(&mthca_device_mutex);
  1037. }
  1038. static struct pci_device_id mthca_pci_table[] = {
  1039. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1040. .driver_data = TAVOR },
  1041. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1042. .driver_data = TAVOR },
  1043. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1044. .driver_data = ARBEL_COMPAT },
  1045. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1046. .driver_data = ARBEL_COMPAT },
  1047. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1048. .driver_data = ARBEL_NATIVE },
  1049. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1050. .driver_data = ARBEL_NATIVE },
  1051. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  1052. .driver_data = SINAI },
  1053. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  1054. .driver_data = SINAI },
  1055. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1056. .driver_data = SINAI },
  1057. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1058. .driver_data = SINAI },
  1059. { 0, }
  1060. };
  1061. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  1062. static struct pci_driver mthca_driver = {
  1063. .name = DRV_NAME,
  1064. .id_table = mthca_pci_table,
  1065. .probe = mthca_init_one,
  1066. .remove = __devexit_p(mthca_remove_one)
  1067. };
  1068. static void __init __mthca_check_profile_val(const char *name, int *pval,
  1069. int pval_default)
  1070. {
  1071. /* value must be positive and power of 2 */
  1072. int old_pval = *pval;
  1073. if (old_pval <= 0)
  1074. *pval = pval_default;
  1075. else
  1076. *pval = roundup_pow_of_two(old_pval);
  1077. if (old_pval != *pval) {
  1078. printk(KERN_WARNING PFX "Invalid value %d for %s in module parameter.\n",
  1079. old_pval, name);
  1080. printk(KERN_WARNING PFX "Corrected %s to %d.\n", name, *pval);
  1081. }
  1082. }
  1083. #define mthca_check_profile_val(name, default) \
  1084. __mthca_check_profile_val(#name, &hca_profile.name, default)
  1085. static void __init mthca_validate_profile(void)
  1086. {
  1087. mthca_check_profile_val(num_qp, MTHCA_DEFAULT_NUM_QP);
  1088. mthca_check_profile_val(rdb_per_qp, MTHCA_DEFAULT_RDB_PER_QP);
  1089. mthca_check_profile_val(num_cq, MTHCA_DEFAULT_NUM_CQ);
  1090. mthca_check_profile_val(num_mcg, MTHCA_DEFAULT_NUM_MCG);
  1091. mthca_check_profile_val(num_mpt, MTHCA_DEFAULT_NUM_MPT);
  1092. mthca_check_profile_val(num_mtt, MTHCA_DEFAULT_NUM_MTT);
  1093. mthca_check_profile_val(num_udav, MTHCA_DEFAULT_NUM_UDAV);
  1094. mthca_check_profile_val(fmr_reserved_mtts, MTHCA_DEFAULT_NUM_RESERVED_MTTS);
  1095. if (hca_profile.fmr_reserved_mtts >= hca_profile.num_mtt) {
  1096. printk(KERN_WARNING PFX "Invalid fmr_reserved_mtts module parameter %d.\n",
  1097. hca_profile.fmr_reserved_mtts);
  1098. printk(KERN_WARNING PFX "(Must be smaller than num_mtt %d)\n",
  1099. hca_profile.num_mtt);
  1100. hca_profile.fmr_reserved_mtts = hca_profile.num_mtt / 2;
  1101. printk(KERN_WARNING PFX "Corrected fmr_reserved_mtts to %d.\n",
  1102. hca_profile.fmr_reserved_mtts);
  1103. }
  1104. if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 5)) {
  1105. printk(KERN_WARNING PFX "bad log_mtts_per_seg (%d). Using default - %d\n",
  1106. log_mtts_per_seg, ilog2(MTHCA_MTT_SEG_SIZE / 8));
  1107. log_mtts_per_seg = ilog2(MTHCA_MTT_SEG_SIZE / 8);
  1108. }
  1109. }
  1110. static int __init mthca_init(void)
  1111. {
  1112. int ret;
  1113. mthca_validate_profile();
  1114. ret = mthca_catas_init();
  1115. if (ret)
  1116. return ret;
  1117. ret = pci_register_driver(&mthca_driver);
  1118. if (ret < 0) {
  1119. mthca_catas_cleanup();
  1120. return ret;
  1121. }
  1122. return 0;
  1123. }
  1124. static void __exit mthca_cleanup(void)
  1125. {
  1126. pci_unregister_driver(&mthca_driver);
  1127. mthca_catas_cleanup();
  1128. }
  1129. module_init(mthca_init);
  1130. module_exit(mthca_cleanup);