i2c-ocores.c 8.5 KB

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  1. /*
  2. * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
  3. * (http://www.opencores.org/projects.cgi/web/i2c/overview).
  4. *
  5. * Peter Korsgaard <jacmet@sunsite.dk>
  6. *
  7. * This file is licensed under the terms of the GNU General Public License
  8. * version 2. This program is licensed "as is" without any warranty of any
  9. * kind, whether express or implied.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/init.h>
  14. #include <linux/errno.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/i2c.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/wait.h>
  19. #include <linux/i2c-ocores.h>
  20. #include <linux/slab.h>
  21. #include <linux/io.h>
  22. struct ocores_i2c {
  23. void __iomem *base;
  24. int regstep;
  25. wait_queue_head_t wait;
  26. struct i2c_adapter adap;
  27. struct i2c_msg *msg;
  28. int pos;
  29. int nmsgs;
  30. int state; /* see STATE_ */
  31. int clock_khz;
  32. };
  33. /* registers */
  34. #define OCI2C_PRELOW 0
  35. #define OCI2C_PREHIGH 1
  36. #define OCI2C_CONTROL 2
  37. #define OCI2C_DATA 3
  38. #define OCI2C_CMD 4 /* write only */
  39. #define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
  40. #define OCI2C_CTRL_IEN 0x40
  41. #define OCI2C_CTRL_EN 0x80
  42. #define OCI2C_CMD_START 0x91
  43. #define OCI2C_CMD_STOP 0x41
  44. #define OCI2C_CMD_READ 0x21
  45. #define OCI2C_CMD_WRITE 0x11
  46. #define OCI2C_CMD_READ_ACK 0x21
  47. #define OCI2C_CMD_READ_NACK 0x29
  48. #define OCI2C_CMD_IACK 0x01
  49. #define OCI2C_STAT_IF 0x01
  50. #define OCI2C_STAT_TIP 0x02
  51. #define OCI2C_STAT_ARBLOST 0x20
  52. #define OCI2C_STAT_BUSY 0x40
  53. #define OCI2C_STAT_NACK 0x80
  54. #define STATE_DONE 0
  55. #define STATE_START 1
  56. #define STATE_WRITE 2
  57. #define STATE_READ 3
  58. #define STATE_ERROR 4
  59. static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
  60. {
  61. iowrite8(value, i2c->base + reg * i2c->regstep);
  62. }
  63. static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
  64. {
  65. return ioread8(i2c->base + reg * i2c->regstep);
  66. }
  67. static void ocores_process(struct ocores_i2c *i2c)
  68. {
  69. struct i2c_msg *msg = i2c->msg;
  70. u8 stat = oc_getreg(i2c, OCI2C_STATUS);
  71. if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
  72. /* stop has been sent */
  73. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
  74. wake_up(&i2c->wait);
  75. return;
  76. }
  77. /* error? */
  78. if (stat & OCI2C_STAT_ARBLOST) {
  79. i2c->state = STATE_ERROR;
  80. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
  81. return;
  82. }
  83. if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
  84. i2c->state =
  85. (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
  86. if (stat & OCI2C_STAT_NACK) {
  87. i2c->state = STATE_ERROR;
  88. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
  89. return;
  90. }
  91. } else
  92. msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
  93. /* end of msg? */
  94. if (i2c->pos == msg->len) {
  95. i2c->nmsgs--;
  96. i2c->msg++;
  97. i2c->pos = 0;
  98. msg = i2c->msg;
  99. if (i2c->nmsgs) { /* end? */
  100. /* send start? */
  101. if (!(msg->flags & I2C_M_NOSTART)) {
  102. u8 addr = (msg->addr << 1);
  103. if (msg->flags & I2C_M_RD)
  104. addr |= 1;
  105. i2c->state = STATE_START;
  106. oc_setreg(i2c, OCI2C_DATA, addr);
  107. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
  108. return;
  109. } else
  110. i2c->state = (msg->flags & I2C_M_RD)
  111. ? STATE_READ : STATE_WRITE;
  112. } else {
  113. i2c->state = STATE_DONE;
  114. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
  115. return;
  116. }
  117. }
  118. if (i2c->state == STATE_READ) {
  119. oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
  120. OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
  121. } else {
  122. oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
  123. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
  124. }
  125. }
  126. static irqreturn_t ocores_isr(int irq, void *dev_id)
  127. {
  128. struct ocores_i2c *i2c = dev_id;
  129. ocores_process(i2c);
  130. return IRQ_HANDLED;
  131. }
  132. static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
  133. {
  134. struct ocores_i2c *i2c = i2c_get_adapdata(adap);
  135. i2c->msg = msgs;
  136. i2c->pos = 0;
  137. i2c->nmsgs = num;
  138. i2c->state = STATE_START;
  139. oc_setreg(i2c, OCI2C_DATA,
  140. (i2c->msg->addr << 1) |
  141. ((i2c->msg->flags & I2C_M_RD) ? 1:0));
  142. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
  143. if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
  144. (i2c->state == STATE_DONE), HZ))
  145. return (i2c->state == STATE_DONE) ? num : -EIO;
  146. else
  147. return -ETIMEDOUT;
  148. }
  149. static void ocores_init(struct ocores_i2c *i2c)
  150. {
  151. int prescale;
  152. u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
  153. /* make sure the device is disabled */
  154. oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
  155. prescale = (i2c->clock_khz / (5*100)) - 1;
  156. oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
  157. oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
  158. /* Init the device */
  159. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
  160. oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN);
  161. }
  162. static u32 ocores_func(struct i2c_adapter *adap)
  163. {
  164. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  165. }
  166. static const struct i2c_algorithm ocores_algorithm = {
  167. .master_xfer = ocores_xfer,
  168. .functionality = ocores_func,
  169. };
  170. static struct i2c_adapter ocores_adapter = {
  171. .owner = THIS_MODULE,
  172. .name = "i2c-ocores",
  173. .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
  174. .algo = &ocores_algorithm,
  175. };
  176. static int __devinit ocores_i2c_probe(struct platform_device *pdev)
  177. {
  178. struct ocores_i2c *i2c;
  179. struct ocores_i2c_platform_data *pdata;
  180. struct resource *res, *res2;
  181. int ret;
  182. int i;
  183. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  184. if (!res)
  185. return -ENODEV;
  186. res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  187. if (!res2)
  188. return -ENODEV;
  189. pdata = (struct ocores_i2c_platform_data*) pdev->dev.platform_data;
  190. if (!pdata)
  191. return -ENODEV;
  192. i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
  193. if (!i2c)
  194. return -ENOMEM;
  195. if (!request_mem_region(res->start, resource_size(res),
  196. pdev->name)) {
  197. dev_err(&pdev->dev, "Memory region busy\n");
  198. ret = -EBUSY;
  199. goto request_mem_failed;
  200. }
  201. i2c->base = ioremap(res->start, resource_size(res));
  202. if (!i2c->base) {
  203. dev_err(&pdev->dev, "Unable to map registers\n");
  204. ret = -EIO;
  205. goto map_failed;
  206. }
  207. i2c->regstep = pdata->regstep;
  208. i2c->clock_khz = pdata->clock_khz;
  209. ocores_init(i2c);
  210. init_waitqueue_head(&i2c->wait);
  211. ret = request_irq(res2->start, ocores_isr, 0, pdev->name, i2c);
  212. if (ret) {
  213. dev_err(&pdev->dev, "Cannot claim IRQ\n");
  214. goto request_irq_failed;
  215. }
  216. /* hook up driver to tree */
  217. platform_set_drvdata(pdev, i2c);
  218. i2c->adap = ocores_adapter;
  219. i2c_set_adapdata(&i2c->adap, i2c);
  220. i2c->adap.dev.parent = &pdev->dev;
  221. /* add i2c adapter to i2c tree */
  222. ret = i2c_add_adapter(&i2c->adap);
  223. if (ret) {
  224. dev_err(&pdev->dev, "Failed to add adapter\n");
  225. goto add_adapter_failed;
  226. }
  227. /* add in known devices to the bus */
  228. for (i = 0; i < pdata->num_devices; i++)
  229. i2c_new_device(&i2c->adap, pdata->devices + i);
  230. return 0;
  231. add_adapter_failed:
  232. free_irq(res2->start, i2c);
  233. request_irq_failed:
  234. iounmap(i2c->base);
  235. map_failed:
  236. release_mem_region(res->start, resource_size(res));
  237. request_mem_failed:
  238. kfree(i2c);
  239. return ret;
  240. }
  241. static int __devexit ocores_i2c_remove(struct platform_device* pdev)
  242. {
  243. struct ocores_i2c *i2c = platform_get_drvdata(pdev);
  244. struct resource *res;
  245. /* disable i2c logic */
  246. oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
  247. & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
  248. /* remove adapter & data */
  249. i2c_del_adapter(&i2c->adap);
  250. platform_set_drvdata(pdev, NULL);
  251. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  252. if (res)
  253. free_irq(res->start, i2c);
  254. iounmap(i2c->base);
  255. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  256. if (res)
  257. release_mem_region(res->start, resource_size(res));
  258. kfree(i2c);
  259. return 0;
  260. }
  261. #ifdef CONFIG_PM
  262. static int ocores_i2c_suspend(struct platform_device *pdev, pm_message_t state)
  263. {
  264. struct ocores_i2c *i2c = platform_get_drvdata(pdev);
  265. u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
  266. /* make sure the device is disabled */
  267. oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
  268. return 0;
  269. }
  270. static int ocores_i2c_resume(struct platform_device *pdev)
  271. {
  272. struct ocores_i2c *i2c = platform_get_drvdata(pdev);
  273. ocores_init(i2c);
  274. return 0;
  275. }
  276. #else
  277. #define ocores_i2c_suspend NULL
  278. #define ocores_i2c_resume NULL
  279. #endif
  280. /* work with hotplug and coldplug */
  281. MODULE_ALIAS("platform:ocores-i2c");
  282. static struct platform_driver ocores_i2c_driver = {
  283. .probe = ocores_i2c_probe,
  284. .remove = __devexit_p(ocores_i2c_remove),
  285. .suspend = ocores_i2c_suspend,
  286. .resume = ocores_i2c_resume,
  287. .driver = {
  288. .owner = THIS_MODULE,
  289. .name = "ocores-i2c",
  290. },
  291. };
  292. static int __init ocores_i2c_init(void)
  293. {
  294. return platform_driver_register(&ocores_i2c_driver);
  295. }
  296. static void __exit ocores_i2c_exit(void)
  297. {
  298. platform_driver_unregister(&ocores_i2c_driver);
  299. }
  300. module_init(ocores_i2c_init);
  301. module_exit(ocores_i2c_exit);
  302. MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
  303. MODULE_DESCRIPTION("OpenCores I2C bus driver");
  304. MODULE_LICENSE("GPL");