nv50_sor.c 9.0 KB

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  1. /*
  2. * Copyright (C) 2008 Maarten Maathuis.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the
  14. * next paragraph) shall be included in all copies or substantial
  15. * portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20. * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21. * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22. * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23. * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24. *
  25. */
  26. #include "drmP.h"
  27. #include "drm_crtc_helper.h"
  28. #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
  29. #include "nouveau_reg.h"
  30. #include "nouveau_drv.h"
  31. #include "nouveau_dma.h"
  32. #include "nouveau_encoder.h"
  33. #include "nouveau_connector.h"
  34. #include "nouveau_crtc.h"
  35. #include "nv50_display.h"
  36. static void
  37. nv50_sor_disconnect(struct drm_encoder *encoder)
  38. {
  39. struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  40. struct drm_device *dev = encoder->dev;
  41. struct drm_nouveau_private *dev_priv = dev->dev_private;
  42. struct nouveau_channel *evo = dev_priv->evo;
  43. int ret;
  44. if (!nv_encoder->crtc)
  45. return;
  46. nv50_crtc_blank(nouveau_crtc(nv_encoder->crtc), true);
  47. NV_DEBUG_KMS(dev, "Disconnecting SOR %d\n", nv_encoder->or);
  48. ret = RING_SPACE(evo, 4);
  49. if (ret) {
  50. NV_ERROR(dev, "no space while disconnecting SOR\n");
  51. return;
  52. }
  53. BEGIN_RING(evo, 0, NV50_EVO_SOR(nv_encoder->or, MODE_CTRL), 1);
  54. OUT_RING (evo, 0);
  55. BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
  56. OUT_RING (evo, 0);
  57. nv_encoder->crtc = NULL;
  58. nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
  59. }
  60. static void
  61. nv50_sor_dpms(struct drm_encoder *encoder, int mode)
  62. {
  63. struct drm_device *dev = encoder->dev;
  64. struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  65. struct drm_encoder *enc;
  66. uint32_t val;
  67. int or = nv_encoder->or;
  68. NV_DEBUG_KMS(dev, "or %d type %d mode %d\n", or, nv_encoder->dcb->type, mode);
  69. nv_encoder->last_dpms = mode;
  70. list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
  71. struct nouveau_encoder *nvenc = nouveau_encoder(enc);
  72. if (nvenc == nv_encoder ||
  73. (nvenc->dcb->type != OUTPUT_TMDS &&
  74. nvenc->dcb->type != OUTPUT_LVDS &&
  75. nvenc->dcb->type != OUTPUT_DP) ||
  76. nvenc->dcb->or != nv_encoder->dcb->or)
  77. continue;
  78. if (nvenc->last_dpms == DRM_MODE_DPMS_ON)
  79. return;
  80. }
  81. /* wait for it to be done */
  82. if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_CTRL(or),
  83. NV50_PDISPLAY_SOR_DPMS_CTRL_PENDING, 0)) {
  84. NV_ERROR(dev, "timeout: SOR_DPMS_CTRL_PENDING(%d) == 0\n", or);
  85. NV_ERROR(dev, "SOR_DPMS_CTRL(%d) = 0x%08x\n", or,
  86. nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_CTRL(or)));
  87. }
  88. val = nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_CTRL(or));
  89. if (mode == DRM_MODE_DPMS_ON)
  90. val |= NV50_PDISPLAY_SOR_DPMS_CTRL_ON;
  91. else
  92. val &= ~NV50_PDISPLAY_SOR_DPMS_CTRL_ON;
  93. nv_wr32(dev, NV50_PDISPLAY_SOR_DPMS_CTRL(or), val |
  94. NV50_PDISPLAY_SOR_DPMS_CTRL_PENDING);
  95. if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(or),
  96. NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
  97. NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", or);
  98. NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", or,
  99. nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(or)));
  100. }
  101. if (nv_encoder->dcb->type == OUTPUT_DP) {
  102. struct nouveau_i2c_chan *auxch;
  103. auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
  104. if (!auxch)
  105. return;
  106. if (mode == DRM_MODE_DPMS_ON) {
  107. u8 status = DP_SET_POWER_D0;
  108. nouveau_dp_auxch(auxch, 8, DP_SET_POWER, &status, 1);
  109. nouveau_dp_link_train(encoder);
  110. } else {
  111. u8 status = DP_SET_POWER_D3;
  112. nouveau_dp_auxch(auxch, 8, DP_SET_POWER, &status, 1);
  113. }
  114. }
  115. }
  116. static void
  117. nv50_sor_save(struct drm_encoder *encoder)
  118. {
  119. NV_ERROR(encoder->dev, "!!\n");
  120. }
  121. static void
  122. nv50_sor_restore(struct drm_encoder *encoder)
  123. {
  124. NV_ERROR(encoder->dev, "!!\n");
  125. }
  126. static bool
  127. nv50_sor_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
  128. struct drm_display_mode *adjusted_mode)
  129. {
  130. struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  131. struct nouveau_connector *connector;
  132. NV_DEBUG_KMS(encoder->dev, "or %d\n", nv_encoder->or);
  133. connector = nouveau_encoder_connector_get(nv_encoder);
  134. if (!connector) {
  135. NV_ERROR(encoder->dev, "Encoder has no connector\n");
  136. return false;
  137. }
  138. if (connector->scaling_mode != DRM_MODE_SCALE_NONE &&
  139. connector->native_mode) {
  140. int id = adjusted_mode->base.id;
  141. *adjusted_mode = *connector->native_mode;
  142. adjusted_mode->base.id = id;
  143. }
  144. return true;
  145. }
  146. static void
  147. nv50_sor_prepare(struct drm_encoder *encoder)
  148. {
  149. }
  150. static void
  151. nv50_sor_commit(struct drm_encoder *encoder)
  152. {
  153. }
  154. static void
  155. nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
  156. struct drm_display_mode *adjusted_mode)
  157. {
  158. struct drm_nouveau_private *dev_priv = encoder->dev->dev_private;
  159. struct nouveau_channel *evo = dev_priv->evo;
  160. struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  161. struct drm_device *dev = encoder->dev;
  162. struct nouveau_crtc *crtc = nouveau_crtc(encoder->crtc);
  163. uint32_t mode_ctl = 0;
  164. int ret;
  165. NV_DEBUG_KMS(dev, "or %d type %d -> crtc %d\n",
  166. nv_encoder->or, nv_encoder->dcb->type, crtc->index);
  167. nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON);
  168. switch (nv_encoder->dcb->type) {
  169. case OUTPUT_TMDS:
  170. if (nv_encoder->dcb->sorconf.link & 1) {
  171. if (adjusted_mode->clock < 165000)
  172. mode_ctl = 0x0100;
  173. else
  174. mode_ctl = 0x0500;
  175. } else
  176. mode_ctl = 0x0200;
  177. break;
  178. case OUTPUT_DP:
  179. mode_ctl |= (nv_encoder->dp.mc_unknown << 16);
  180. if (nv_encoder->dcb->sorconf.link & 1)
  181. mode_ctl |= 0x00000800;
  182. else
  183. mode_ctl |= 0x00000900;
  184. break;
  185. default:
  186. break;
  187. }
  188. if (crtc->index == 1)
  189. mode_ctl |= NV50_EVO_SOR_MODE_CTRL_CRTC1;
  190. else
  191. mode_ctl |= NV50_EVO_SOR_MODE_CTRL_CRTC0;
  192. if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
  193. mode_ctl |= NV50_EVO_SOR_MODE_CTRL_NHSYNC;
  194. if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
  195. mode_ctl |= NV50_EVO_SOR_MODE_CTRL_NVSYNC;
  196. ret = RING_SPACE(evo, 2);
  197. if (ret) {
  198. NV_ERROR(dev, "no space while connecting SOR\n");
  199. return;
  200. }
  201. BEGIN_RING(evo, 0, NV50_EVO_SOR(nv_encoder->or, MODE_CTRL), 1);
  202. OUT_RING(evo, mode_ctl);
  203. nv_encoder->crtc = encoder->crtc;
  204. }
  205. static struct drm_crtc *
  206. nv50_sor_crtc_get(struct drm_encoder *encoder)
  207. {
  208. return nouveau_encoder(encoder)->crtc;
  209. }
  210. static const struct drm_encoder_helper_funcs nv50_sor_helper_funcs = {
  211. .dpms = nv50_sor_dpms,
  212. .save = nv50_sor_save,
  213. .restore = nv50_sor_restore,
  214. .mode_fixup = nv50_sor_mode_fixup,
  215. .prepare = nv50_sor_prepare,
  216. .commit = nv50_sor_commit,
  217. .mode_set = nv50_sor_mode_set,
  218. .get_crtc = nv50_sor_crtc_get,
  219. .detect = NULL,
  220. .disable = nv50_sor_disconnect
  221. };
  222. static void
  223. nv50_sor_destroy(struct drm_encoder *encoder)
  224. {
  225. struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  226. if (!encoder)
  227. return;
  228. NV_DEBUG_KMS(encoder->dev, "\n");
  229. drm_encoder_cleanup(encoder);
  230. kfree(nv_encoder);
  231. }
  232. static const struct drm_encoder_funcs nv50_sor_encoder_funcs = {
  233. .destroy = nv50_sor_destroy,
  234. };
  235. int
  236. nv50_sor_create(struct drm_connector *connector, struct dcb_entry *entry)
  237. {
  238. struct nouveau_encoder *nv_encoder = NULL;
  239. struct drm_device *dev = connector->dev;
  240. struct drm_encoder *encoder;
  241. int type;
  242. NV_DEBUG_KMS(dev, "\n");
  243. switch (entry->type) {
  244. case OUTPUT_TMDS:
  245. case OUTPUT_DP:
  246. type = DRM_MODE_ENCODER_TMDS;
  247. break;
  248. case OUTPUT_LVDS:
  249. type = DRM_MODE_ENCODER_LVDS;
  250. break;
  251. default:
  252. return -EINVAL;
  253. }
  254. nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
  255. if (!nv_encoder)
  256. return -ENOMEM;
  257. encoder = to_drm_encoder(nv_encoder);
  258. nv_encoder->dcb = entry;
  259. nv_encoder->or = ffs(entry->or) - 1;
  260. nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
  261. drm_encoder_init(dev, encoder, &nv50_sor_encoder_funcs, type);
  262. drm_encoder_helper_add(encoder, &nv50_sor_helper_funcs);
  263. encoder->possible_crtcs = entry->heads;
  264. encoder->possible_clones = 0;
  265. if (nv_encoder->dcb->type == OUTPUT_DP) {
  266. int or = nv_encoder->or, link = !(entry->dpconf.sor.link & 1);
  267. uint32_t tmp;
  268. tmp = nv_rd32(dev, 0x61c700 + (or * 0x800));
  269. switch ((tmp & 0x00000f00) >> 8) {
  270. case 8:
  271. case 9:
  272. nv_encoder->dp.mc_unknown = (tmp & 0x000f0000) >> 16;
  273. tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
  274. nv_encoder->dp.unk0 = tmp & 0x000001fc;
  275. tmp = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link));
  276. nv_encoder->dp.unk1 = tmp & 0x010f7f3f;
  277. break;
  278. default:
  279. break;
  280. }
  281. if (!nv_encoder->dp.mc_unknown)
  282. nv_encoder->dp.mc_unknown = 5;
  283. }
  284. drm_mode_connector_attach_encoder(connector, encoder);
  285. return 0;
  286. }