nouveau_fence.c 13 KB

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  1. /*
  2. * Copyright (C) 2007 Ben Skeggs.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the
  14. * next paragraph) shall be included in all copies or substantial
  15. * portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20. * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21. * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22. * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23. * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24. *
  25. */
  26. #include "drmP.h"
  27. #include "drm.h"
  28. #include "nouveau_drv.h"
  29. #include "nouveau_ramht.h"
  30. #include "nouveau_dma.h"
  31. #define USE_REFCNT(dev) (nouveau_private(dev)->chipset >= 0x10)
  32. #define USE_SEMA(dev) (nouveau_private(dev)->chipset >= 0x17 && \
  33. nouveau_private(dev)->card_type < NV_C0)
  34. struct nouveau_fence {
  35. struct nouveau_channel *channel;
  36. struct kref refcount;
  37. struct list_head entry;
  38. uint32_t sequence;
  39. bool signalled;
  40. void (*work)(void *priv, bool signalled);
  41. void *priv;
  42. };
  43. struct nouveau_semaphore {
  44. struct kref ref;
  45. struct drm_device *dev;
  46. struct drm_mm_node *mem;
  47. };
  48. static inline struct nouveau_fence *
  49. nouveau_fence(void *sync_obj)
  50. {
  51. return (struct nouveau_fence *)sync_obj;
  52. }
  53. static void
  54. nouveau_fence_del(struct kref *ref)
  55. {
  56. struct nouveau_fence *fence =
  57. container_of(ref, struct nouveau_fence, refcount);
  58. nouveau_channel_ref(NULL, &fence->channel);
  59. kfree(fence);
  60. }
  61. void
  62. nouveau_fence_update(struct nouveau_channel *chan)
  63. {
  64. struct drm_device *dev = chan->dev;
  65. struct nouveau_fence *tmp, *fence;
  66. uint32_t sequence;
  67. spin_lock(&chan->fence.lock);
  68. /* Fetch the last sequence if the channel is still up and running */
  69. if (likely(!list_empty(&chan->fence.pending))) {
  70. if (USE_REFCNT(dev))
  71. sequence = nvchan_rd32(chan, 0x48);
  72. else
  73. sequence = atomic_read(&chan->fence.last_sequence_irq);
  74. if (chan->fence.sequence_ack == sequence)
  75. goto out;
  76. chan->fence.sequence_ack = sequence;
  77. }
  78. list_for_each_entry_safe(fence, tmp, &chan->fence.pending, entry) {
  79. sequence = fence->sequence;
  80. fence->signalled = true;
  81. list_del(&fence->entry);
  82. if (unlikely(fence->work))
  83. fence->work(fence->priv, true);
  84. kref_put(&fence->refcount, nouveau_fence_del);
  85. if (sequence == chan->fence.sequence_ack)
  86. break;
  87. }
  88. out:
  89. spin_unlock(&chan->fence.lock);
  90. }
  91. int
  92. nouveau_fence_new(struct nouveau_channel *chan, struct nouveau_fence **pfence,
  93. bool emit)
  94. {
  95. struct nouveau_fence *fence;
  96. int ret = 0;
  97. fence = kzalloc(sizeof(*fence), GFP_KERNEL);
  98. if (!fence)
  99. return -ENOMEM;
  100. kref_init(&fence->refcount);
  101. nouveau_channel_ref(chan, &fence->channel);
  102. if (emit)
  103. ret = nouveau_fence_emit(fence);
  104. if (ret)
  105. nouveau_fence_unref(&fence);
  106. *pfence = fence;
  107. return ret;
  108. }
  109. struct nouveau_channel *
  110. nouveau_fence_channel(struct nouveau_fence *fence)
  111. {
  112. return fence ? nouveau_channel_get_unlocked(fence->channel) : NULL;
  113. }
  114. int
  115. nouveau_fence_emit(struct nouveau_fence *fence)
  116. {
  117. struct nouveau_channel *chan = fence->channel;
  118. struct drm_device *dev = chan->dev;
  119. struct drm_nouveau_private *dev_priv = dev->dev_private;
  120. int ret;
  121. ret = RING_SPACE(chan, 2);
  122. if (ret)
  123. return ret;
  124. if (unlikely(chan->fence.sequence == chan->fence.sequence_ack - 1)) {
  125. nouveau_fence_update(chan);
  126. BUG_ON(chan->fence.sequence ==
  127. chan->fence.sequence_ack - 1);
  128. }
  129. fence->sequence = ++chan->fence.sequence;
  130. kref_get(&fence->refcount);
  131. spin_lock(&chan->fence.lock);
  132. list_add_tail(&fence->entry, &chan->fence.pending);
  133. spin_unlock(&chan->fence.lock);
  134. if (USE_REFCNT(dev)) {
  135. if (dev_priv->card_type < NV_C0)
  136. BEGIN_RING(chan, NvSubSw, 0x0050, 1);
  137. else
  138. BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0050, 1);
  139. } else {
  140. BEGIN_RING(chan, NvSubSw, 0x0150, 1);
  141. }
  142. OUT_RING (chan, fence->sequence);
  143. FIRE_RING(chan);
  144. return 0;
  145. }
  146. void
  147. nouveau_fence_work(struct nouveau_fence *fence,
  148. void (*work)(void *priv, bool signalled),
  149. void *priv)
  150. {
  151. BUG_ON(fence->work);
  152. spin_lock(&fence->channel->fence.lock);
  153. if (fence->signalled) {
  154. work(priv, true);
  155. } else {
  156. fence->work = work;
  157. fence->priv = priv;
  158. }
  159. spin_unlock(&fence->channel->fence.lock);
  160. }
  161. void
  162. __nouveau_fence_unref(void **sync_obj)
  163. {
  164. struct nouveau_fence *fence = nouveau_fence(*sync_obj);
  165. if (fence)
  166. kref_put(&fence->refcount, nouveau_fence_del);
  167. *sync_obj = NULL;
  168. }
  169. void *
  170. __nouveau_fence_ref(void *sync_obj)
  171. {
  172. struct nouveau_fence *fence = nouveau_fence(sync_obj);
  173. kref_get(&fence->refcount);
  174. return sync_obj;
  175. }
  176. bool
  177. __nouveau_fence_signalled(void *sync_obj, void *sync_arg)
  178. {
  179. struct nouveau_fence *fence = nouveau_fence(sync_obj);
  180. struct nouveau_channel *chan = fence->channel;
  181. if (fence->signalled)
  182. return true;
  183. nouveau_fence_update(chan);
  184. return fence->signalled;
  185. }
  186. int
  187. __nouveau_fence_wait(void *sync_obj, void *sync_arg, bool lazy, bool intr)
  188. {
  189. unsigned long timeout = jiffies + (3 * DRM_HZ);
  190. unsigned long sleep_time = jiffies + 1;
  191. int ret = 0;
  192. while (1) {
  193. if (__nouveau_fence_signalled(sync_obj, sync_arg))
  194. break;
  195. if (time_after_eq(jiffies, timeout)) {
  196. ret = -EBUSY;
  197. break;
  198. }
  199. __set_current_state(intr ? TASK_INTERRUPTIBLE
  200. : TASK_UNINTERRUPTIBLE);
  201. if (lazy && time_after_eq(jiffies, sleep_time))
  202. schedule_timeout(1);
  203. if (intr && signal_pending(current)) {
  204. ret = -ERESTARTSYS;
  205. break;
  206. }
  207. }
  208. __set_current_state(TASK_RUNNING);
  209. return ret;
  210. }
  211. static struct nouveau_semaphore *
  212. alloc_semaphore(struct drm_device *dev)
  213. {
  214. struct drm_nouveau_private *dev_priv = dev->dev_private;
  215. struct nouveau_semaphore *sema;
  216. int ret;
  217. if (!USE_SEMA(dev))
  218. return NULL;
  219. sema = kmalloc(sizeof(*sema), GFP_KERNEL);
  220. if (!sema)
  221. goto fail;
  222. ret = drm_mm_pre_get(&dev_priv->fence.heap);
  223. if (ret)
  224. goto fail;
  225. spin_lock(&dev_priv->fence.lock);
  226. sema->mem = drm_mm_search_free(&dev_priv->fence.heap, 4, 0, 0);
  227. if (sema->mem)
  228. sema->mem = drm_mm_get_block_atomic(sema->mem, 4, 0);
  229. spin_unlock(&dev_priv->fence.lock);
  230. if (!sema->mem)
  231. goto fail;
  232. kref_init(&sema->ref);
  233. sema->dev = dev;
  234. nouveau_bo_wr32(dev_priv->fence.bo, sema->mem->start / 4, 0);
  235. return sema;
  236. fail:
  237. kfree(sema);
  238. return NULL;
  239. }
  240. static void
  241. free_semaphore(struct kref *ref)
  242. {
  243. struct nouveau_semaphore *sema =
  244. container_of(ref, struct nouveau_semaphore, ref);
  245. struct drm_nouveau_private *dev_priv = sema->dev->dev_private;
  246. spin_lock(&dev_priv->fence.lock);
  247. drm_mm_put_block(sema->mem);
  248. spin_unlock(&dev_priv->fence.lock);
  249. kfree(sema);
  250. }
  251. static void
  252. semaphore_work(void *priv, bool signalled)
  253. {
  254. struct nouveau_semaphore *sema = priv;
  255. struct drm_nouveau_private *dev_priv = sema->dev->dev_private;
  256. if (unlikely(!signalled))
  257. nouveau_bo_wr32(dev_priv->fence.bo, sema->mem->start / 4, 1);
  258. kref_put(&sema->ref, free_semaphore);
  259. }
  260. static int
  261. emit_semaphore(struct nouveau_channel *chan, int method,
  262. struct nouveau_semaphore *sema)
  263. {
  264. struct drm_nouveau_private *dev_priv = sema->dev->dev_private;
  265. struct nouveau_fence *fence;
  266. bool smart = (dev_priv->card_type >= NV_50);
  267. int ret;
  268. ret = RING_SPACE(chan, smart ? 8 : 4);
  269. if (ret)
  270. return ret;
  271. if (smart) {
  272. BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1);
  273. OUT_RING(chan, NvSema);
  274. }
  275. BEGIN_RING(chan, NvSubSw, NV_SW_SEMAPHORE_OFFSET, 1);
  276. OUT_RING(chan, sema->mem->start);
  277. if (smart && method == NV_SW_SEMAPHORE_ACQUIRE) {
  278. /*
  279. * NV50 tries to be too smart and context-switch
  280. * between semaphores instead of doing a "first come,
  281. * first served" strategy like previous cards
  282. * do.
  283. *
  284. * That's bad because the ACQUIRE latency can get as
  285. * large as the PFIFO context time slice in the
  286. * typical DRI2 case where you have several
  287. * outstanding semaphores at the same moment.
  288. *
  289. * If we're going to ACQUIRE, force the card to
  290. * context switch before, just in case the matching
  291. * RELEASE is already scheduled to be executed in
  292. * another channel.
  293. */
  294. BEGIN_RING(chan, NvSubSw, NV_SW_YIELD, 1);
  295. OUT_RING(chan, 0);
  296. }
  297. BEGIN_RING(chan, NvSubSw, method, 1);
  298. OUT_RING(chan, 1);
  299. if (smart && method == NV_SW_SEMAPHORE_RELEASE) {
  300. /*
  301. * Force the card to context switch, there may be
  302. * another channel waiting for the semaphore we just
  303. * released.
  304. */
  305. BEGIN_RING(chan, NvSubSw, NV_SW_YIELD, 1);
  306. OUT_RING(chan, 0);
  307. }
  308. /* Delay semaphore destruction until its work is done */
  309. ret = nouveau_fence_new(chan, &fence, true);
  310. if (ret)
  311. return ret;
  312. kref_get(&sema->ref);
  313. nouveau_fence_work(fence, semaphore_work, sema);
  314. nouveau_fence_unref(&fence);
  315. return 0;
  316. }
  317. int
  318. nouveau_fence_sync(struct nouveau_fence *fence,
  319. struct nouveau_channel *wchan)
  320. {
  321. struct nouveau_channel *chan = nouveau_fence_channel(fence);
  322. struct drm_device *dev = wchan->dev;
  323. struct nouveau_semaphore *sema;
  324. int ret = 0;
  325. if (likely(!chan || chan == wchan ||
  326. nouveau_fence_signalled(fence)))
  327. goto out;
  328. sema = alloc_semaphore(dev);
  329. if (!sema) {
  330. /* Early card or broken userspace, fall back to
  331. * software sync. */
  332. ret = nouveau_fence_wait(fence, true, false);
  333. goto out;
  334. }
  335. /* try to take chan's mutex, if we can't take it right away
  336. * we have to fallback to software sync to prevent locking
  337. * order issues
  338. */
  339. if (!mutex_trylock(&chan->mutex)) {
  340. ret = nouveau_fence_wait(fence, true, false);
  341. goto out_unref;
  342. }
  343. /* Make wchan wait until it gets signalled */
  344. ret = emit_semaphore(wchan, NV_SW_SEMAPHORE_ACQUIRE, sema);
  345. if (ret)
  346. goto out_unlock;
  347. /* Signal the semaphore from chan */
  348. ret = emit_semaphore(chan, NV_SW_SEMAPHORE_RELEASE, sema);
  349. out_unlock:
  350. mutex_unlock(&chan->mutex);
  351. out_unref:
  352. kref_put(&sema->ref, free_semaphore);
  353. out:
  354. if (chan)
  355. nouveau_channel_put_unlocked(&chan);
  356. return ret;
  357. }
  358. int
  359. __nouveau_fence_flush(void *sync_obj, void *sync_arg)
  360. {
  361. return 0;
  362. }
  363. int
  364. nouveau_fence_channel_init(struct nouveau_channel *chan)
  365. {
  366. struct drm_device *dev = chan->dev;
  367. struct drm_nouveau_private *dev_priv = dev->dev_private;
  368. struct nouveau_gpuobj *obj = NULL;
  369. int ret;
  370. /* Create an NV_SW object for various sync purposes */
  371. ret = nouveau_gpuobj_gr_new(chan, NvSw, NV_SW);
  372. if (ret)
  373. return ret;
  374. /* we leave subchannel empty for nvc0 */
  375. if (dev_priv->card_type < NV_C0) {
  376. ret = RING_SPACE(chan, 2);
  377. if (ret)
  378. return ret;
  379. BEGIN_RING(chan, NvSubSw, 0, 1);
  380. OUT_RING(chan, NvSw);
  381. }
  382. /* Create a DMA object for the shared cross-channel sync area. */
  383. if (USE_SEMA(dev)) {
  384. struct ttm_mem_reg *mem = &dev_priv->fence.bo->bo.mem;
  385. ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
  386. mem->start << PAGE_SHIFT,
  387. mem->size, NV_MEM_ACCESS_RW,
  388. NV_MEM_TARGET_VRAM, &obj);
  389. if (ret)
  390. return ret;
  391. ret = nouveau_ramht_insert(chan, NvSema, obj);
  392. nouveau_gpuobj_ref(NULL, &obj);
  393. if (ret)
  394. return ret;
  395. ret = RING_SPACE(chan, 2);
  396. if (ret)
  397. return ret;
  398. BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1);
  399. OUT_RING(chan, NvSema);
  400. }
  401. FIRE_RING(chan);
  402. INIT_LIST_HEAD(&chan->fence.pending);
  403. spin_lock_init(&chan->fence.lock);
  404. atomic_set(&chan->fence.last_sequence_irq, 0);
  405. return 0;
  406. }
  407. void
  408. nouveau_fence_channel_fini(struct nouveau_channel *chan)
  409. {
  410. struct nouveau_fence *tmp, *fence;
  411. spin_lock(&chan->fence.lock);
  412. list_for_each_entry_safe(fence, tmp, &chan->fence.pending, entry) {
  413. fence->signalled = true;
  414. list_del(&fence->entry);
  415. if (unlikely(fence->work))
  416. fence->work(fence->priv, false);
  417. kref_put(&fence->refcount, nouveau_fence_del);
  418. }
  419. spin_unlock(&chan->fence.lock);
  420. }
  421. int
  422. nouveau_fence_init(struct drm_device *dev)
  423. {
  424. struct drm_nouveau_private *dev_priv = dev->dev_private;
  425. int ret;
  426. /* Create a shared VRAM heap for cross-channel sync. */
  427. if (USE_SEMA(dev)) {
  428. ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM,
  429. 0, 0, false, true, &dev_priv->fence.bo);
  430. if (ret)
  431. return ret;
  432. ret = nouveau_bo_pin(dev_priv->fence.bo, TTM_PL_FLAG_VRAM);
  433. if (ret)
  434. goto fail;
  435. ret = nouveau_bo_map(dev_priv->fence.bo);
  436. if (ret)
  437. goto fail;
  438. ret = drm_mm_init(&dev_priv->fence.heap, 0,
  439. dev_priv->fence.bo->bo.mem.size);
  440. if (ret)
  441. goto fail;
  442. spin_lock_init(&dev_priv->fence.lock);
  443. }
  444. return 0;
  445. fail:
  446. nouveau_bo_unmap(dev_priv->fence.bo);
  447. nouveau_bo_ref(NULL, &dev_priv->fence.bo);
  448. return ret;
  449. }
  450. void
  451. nouveau_fence_fini(struct drm_device *dev)
  452. {
  453. struct drm_nouveau_private *dev_priv = dev->dev_private;
  454. if (USE_SEMA(dev)) {
  455. drm_mm_takedown(&dev_priv->fence.heap);
  456. nouveau_bo_unmap(dev_priv->fence.bo);
  457. nouveau_bo_unpin(dev_priv->fence.bo);
  458. nouveau_bo_ref(NULL, &dev_priv->fence.bo);
  459. }
  460. }