sx150x.c 15 KB

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  1. /* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. * You should have received a copy of the GNU General Public License
  13. * along with this program; if not, write to the Free Software
  14. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  15. * 02110-1301, USA.
  16. */
  17. #include <linux/gpio.h>
  18. #include <linux/i2c.h>
  19. #include <linux/init.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/irq.h>
  22. #include <linux/module.h>
  23. #include <linux/mutex.h>
  24. #include <linux/slab.h>
  25. #include <linux/workqueue.h>
  26. #include <linux/i2c/sx150x.h>
  27. struct sx150x_device_data {
  28. u8 reg_pullup;
  29. u8 reg_pulldn;
  30. u8 reg_drain;
  31. u8 reg_polarity;
  32. u8 reg_dir;
  33. u8 reg_data;
  34. u8 reg_irq_mask;
  35. u8 reg_irq_src;
  36. u8 reg_sense;
  37. u8 reg_clock;
  38. u8 reg_misc;
  39. u8 reg_reset;
  40. u8 ngpios;
  41. };
  42. struct sx150x_chip {
  43. struct gpio_chip gpio_chip;
  44. struct i2c_client *client;
  45. const struct sx150x_device_data *dev_cfg;
  46. int irq_summary;
  47. int irq_base;
  48. u32 irq_sense;
  49. unsigned long irq_set_type_pending;
  50. struct irq_chip irq_chip;
  51. struct mutex lock;
  52. };
  53. static const struct sx150x_device_data sx150x_devices[] = {
  54. [0] = { /* sx1508q */
  55. .reg_pullup = 0x03,
  56. .reg_pulldn = 0x04,
  57. .reg_drain = 0x05,
  58. .reg_polarity = 0x06,
  59. .reg_dir = 0x07,
  60. .reg_data = 0x08,
  61. .reg_irq_mask = 0x09,
  62. .reg_irq_src = 0x0c,
  63. .reg_sense = 0x0b,
  64. .reg_clock = 0x0f,
  65. .reg_misc = 0x10,
  66. .reg_reset = 0x7d,
  67. .ngpios = 8
  68. },
  69. [1] = { /* sx1509q */
  70. .reg_pullup = 0x07,
  71. .reg_pulldn = 0x09,
  72. .reg_drain = 0x0b,
  73. .reg_polarity = 0x0d,
  74. .reg_dir = 0x0f,
  75. .reg_data = 0x11,
  76. .reg_irq_mask = 0x13,
  77. .reg_irq_src = 0x19,
  78. .reg_sense = 0x17,
  79. .reg_clock = 0x1e,
  80. .reg_misc = 0x1f,
  81. .reg_reset = 0x7d,
  82. .ngpios = 16
  83. },
  84. };
  85. static const struct i2c_device_id sx150x_id[] = {
  86. {"sx1508q", 0},
  87. {"sx1509q", 1},
  88. {}
  89. };
  90. MODULE_DEVICE_TABLE(i2c, sx150x_id);
  91. static s32 sx150x_i2c_write(struct i2c_client *client, u8 reg, u8 val)
  92. {
  93. s32 err = i2c_smbus_write_byte_data(client, reg, val);
  94. if (err < 0)
  95. dev_warn(&client->dev,
  96. "i2c write fail: can't write %02x to %02x: %d\n",
  97. val, reg, err);
  98. return err;
  99. }
  100. static s32 sx150x_i2c_read(struct i2c_client *client, u8 reg, u8 *val)
  101. {
  102. s32 err = i2c_smbus_read_byte_data(client, reg);
  103. if (err >= 0)
  104. *val = err;
  105. else
  106. dev_warn(&client->dev,
  107. "i2c read fail: can't read from %02x: %d\n",
  108. reg, err);
  109. return err;
  110. }
  111. static inline bool offset_is_oscio(struct sx150x_chip *chip, unsigned offset)
  112. {
  113. return (chip->dev_cfg->ngpios == offset);
  114. }
  115. /*
  116. * These utility functions solve the common problem of locating and setting
  117. * configuration bits. Configuration bits are grouped into registers
  118. * whose indexes increase downwards. For example, with eight-bit registers,
  119. * sixteen gpios would have their config bits grouped in the following order:
  120. * REGISTER N-1 [ f e d c b a 9 8 ]
  121. * N [ 7 6 5 4 3 2 1 0 ]
  122. *
  123. * For multi-bit configurations, the pattern gets wider:
  124. * REGISTER N-3 [ f f e e d d c c ]
  125. * N-2 [ b b a a 9 9 8 8 ]
  126. * N-1 [ 7 7 6 6 5 5 4 4 ]
  127. * N [ 3 3 2 2 1 1 0 0 ]
  128. *
  129. * Given the address of the starting register 'N', the index of the gpio
  130. * whose configuration we seek to change, and the width in bits of that
  131. * configuration, these functions allow us to locate the correct
  132. * register and mask the correct bits.
  133. */
  134. static inline void sx150x_find_cfg(u8 offset, u8 width,
  135. u8 *reg, u8 *mask, u8 *shift)
  136. {
  137. *reg -= offset * width / 8;
  138. *mask = (1 << width) - 1;
  139. *shift = (offset * width) % 8;
  140. *mask <<= *shift;
  141. }
  142. static s32 sx150x_write_cfg(struct sx150x_chip *chip,
  143. u8 offset, u8 width, u8 reg, u8 val)
  144. {
  145. u8 mask;
  146. u8 data;
  147. u8 shift;
  148. s32 err;
  149. sx150x_find_cfg(offset, width, &reg, &mask, &shift);
  150. err = sx150x_i2c_read(chip->client, reg, &data);
  151. if (err < 0)
  152. return err;
  153. data &= ~mask;
  154. data |= (val << shift) & mask;
  155. return sx150x_i2c_write(chip->client, reg, data);
  156. }
  157. static int sx150x_get_io(struct sx150x_chip *chip, unsigned offset)
  158. {
  159. u8 reg = chip->dev_cfg->reg_data;
  160. u8 mask;
  161. u8 data;
  162. u8 shift;
  163. s32 err;
  164. sx150x_find_cfg(offset, 1, &reg, &mask, &shift);
  165. err = sx150x_i2c_read(chip->client, reg, &data);
  166. if (err >= 0)
  167. err = (data & mask) != 0 ? 1 : 0;
  168. return err;
  169. }
  170. static void sx150x_set_oscio(struct sx150x_chip *chip, int val)
  171. {
  172. sx150x_i2c_write(chip->client,
  173. chip->dev_cfg->reg_clock,
  174. (val ? 0x1f : 0x10));
  175. }
  176. static void sx150x_set_io(struct sx150x_chip *chip, unsigned offset, int val)
  177. {
  178. sx150x_write_cfg(chip,
  179. offset,
  180. 1,
  181. chip->dev_cfg->reg_data,
  182. (val ? 1 : 0));
  183. }
  184. static int sx150x_io_input(struct sx150x_chip *chip, unsigned offset)
  185. {
  186. return sx150x_write_cfg(chip,
  187. offset,
  188. 1,
  189. chip->dev_cfg->reg_dir,
  190. 1);
  191. }
  192. static int sx150x_io_output(struct sx150x_chip *chip, unsigned offset, int val)
  193. {
  194. int err;
  195. err = sx150x_write_cfg(chip,
  196. offset,
  197. 1,
  198. chip->dev_cfg->reg_data,
  199. (val ? 1 : 0));
  200. if (err >= 0)
  201. err = sx150x_write_cfg(chip,
  202. offset,
  203. 1,
  204. chip->dev_cfg->reg_dir,
  205. 0);
  206. return err;
  207. }
  208. static int sx150x_gpio_get(struct gpio_chip *gc, unsigned offset)
  209. {
  210. struct sx150x_chip *chip;
  211. int status = -EINVAL;
  212. chip = container_of(gc, struct sx150x_chip, gpio_chip);
  213. if (!offset_is_oscio(chip, offset)) {
  214. mutex_lock(&chip->lock);
  215. status = sx150x_get_io(chip, offset);
  216. mutex_unlock(&chip->lock);
  217. }
  218. return status;
  219. }
  220. static void sx150x_gpio_set(struct gpio_chip *gc, unsigned offset, int val)
  221. {
  222. struct sx150x_chip *chip;
  223. chip = container_of(gc, struct sx150x_chip, gpio_chip);
  224. mutex_lock(&chip->lock);
  225. if (offset_is_oscio(chip, offset))
  226. sx150x_set_oscio(chip, val);
  227. else
  228. sx150x_set_io(chip, offset, val);
  229. mutex_unlock(&chip->lock);
  230. }
  231. static int sx150x_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
  232. {
  233. struct sx150x_chip *chip;
  234. int status = -EINVAL;
  235. chip = container_of(gc, struct sx150x_chip, gpio_chip);
  236. if (!offset_is_oscio(chip, offset)) {
  237. mutex_lock(&chip->lock);
  238. status = sx150x_io_input(chip, offset);
  239. mutex_unlock(&chip->lock);
  240. }
  241. return status;
  242. }
  243. static int sx150x_gpio_direction_output(struct gpio_chip *gc,
  244. unsigned offset,
  245. int val)
  246. {
  247. struct sx150x_chip *chip;
  248. int status = 0;
  249. chip = container_of(gc, struct sx150x_chip, gpio_chip);
  250. if (!offset_is_oscio(chip, offset)) {
  251. mutex_lock(&chip->lock);
  252. status = sx150x_io_output(chip, offset, val);
  253. mutex_unlock(&chip->lock);
  254. }
  255. return status;
  256. }
  257. static int sx150x_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
  258. {
  259. struct sx150x_chip *chip;
  260. chip = container_of(gc, struct sx150x_chip, gpio_chip);
  261. if (offset >= chip->dev_cfg->ngpios)
  262. return -EINVAL;
  263. if (chip->irq_base < 0)
  264. return -EINVAL;
  265. return chip->irq_base + offset;
  266. }
  267. static void sx150x_irq_mask(unsigned int irq)
  268. {
  269. struct irq_chip *ic = get_irq_chip(irq);
  270. struct sx150x_chip *chip;
  271. unsigned n;
  272. chip = container_of(ic, struct sx150x_chip, irq_chip);
  273. n = irq - chip->irq_base;
  274. sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 1);
  275. sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense, 0);
  276. }
  277. static void sx150x_irq_unmask(unsigned int irq)
  278. {
  279. struct irq_chip *ic = get_irq_chip(irq);
  280. struct sx150x_chip *chip;
  281. unsigned n;
  282. chip = container_of(ic, struct sx150x_chip, irq_chip);
  283. n = irq - chip->irq_base;
  284. sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 0);
  285. sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense,
  286. chip->irq_sense >> (n * 2));
  287. }
  288. static int sx150x_irq_set_type(unsigned int irq, unsigned int flow_type)
  289. {
  290. struct irq_chip *ic = get_irq_chip(irq);
  291. struct sx150x_chip *chip;
  292. unsigned n, val = 0;
  293. if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
  294. return -EINVAL;
  295. chip = container_of(ic, struct sx150x_chip, irq_chip);
  296. n = irq - chip->irq_base;
  297. if (flow_type & IRQ_TYPE_EDGE_RISING)
  298. val |= 0x1;
  299. if (flow_type & IRQ_TYPE_EDGE_FALLING)
  300. val |= 0x2;
  301. chip->irq_sense &= ~(3UL << (n * 2));
  302. chip->irq_sense |= val << (n * 2);
  303. chip->irq_set_type_pending |= BIT(n);
  304. return 0;
  305. }
  306. static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
  307. {
  308. struct sx150x_chip *chip = (struct sx150x_chip *)dev_id;
  309. unsigned nhandled = 0;
  310. unsigned sub_irq;
  311. unsigned n;
  312. s32 err;
  313. u8 val;
  314. int i;
  315. for (i = (chip->dev_cfg->ngpios / 8) - 1; i >= 0; --i) {
  316. err = sx150x_i2c_read(chip->client,
  317. chip->dev_cfg->reg_irq_src - i,
  318. &val);
  319. if (err < 0)
  320. continue;
  321. sx150x_i2c_write(chip->client,
  322. chip->dev_cfg->reg_irq_src - i,
  323. val);
  324. for (n = 0; n < 8; ++n) {
  325. if (val & (1 << n)) {
  326. sub_irq = chip->irq_base + (i * 8) + n;
  327. handle_nested_irq(sub_irq);
  328. ++nhandled;
  329. }
  330. }
  331. }
  332. return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
  333. }
  334. static void sx150x_irq_bus_lock(unsigned int irq)
  335. {
  336. struct irq_chip *ic = get_irq_chip(irq);
  337. struct sx150x_chip *chip;
  338. chip = container_of(ic, struct sx150x_chip, irq_chip);
  339. mutex_lock(&chip->lock);
  340. }
  341. static void sx150x_irq_bus_sync_unlock(unsigned int irq)
  342. {
  343. struct irq_chip *ic = get_irq_chip(irq);
  344. struct sx150x_chip *chip;
  345. unsigned n;
  346. chip = container_of(ic, struct sx150x_chip, irq_chip);
  347. while (chip->irq_set_type_pending) {
  348. n = __ffs(chip->irq_set_type_pending);
  349. chip->irq_set_type_pending &= ~BIT(n);
  350. if (!(irq_to_desc(n + chip->irq_base)->status & IRQ_MASKED))
  351. sx150x_write_cfg(chip, n, 2,
  352. chip->dev_cfg->reg_sense,
  353. chip->irq_sense >> (n * 2));
  354. }
  355. mutex_unlock(&chip->lock);
  356. }
  357. static void sx150x_init_chip(struct sx150x_chip *chip,
  358. struct i2c_client *client,
  359. kernel_ulong_t driver_data,
  360. struct sx150x_platform_data *pdata)
  361. {
  362. mutex_init(&chip->lock);
  363. chip->client = client;
  364. chip->dev_cfg = &sx150x_devices[driver_data];
  365. chip->gpio_chip.label = client->name;
  366. chip->gpio_chip.direction_input = sx150x_gpio_direction_input;
  367. chip->gpio_chip.direction_output = sx150x_gpio_direction_output;
  368. chip->gpio_chip.get = sx150x_gpio_get;
  369. chip->gpio_chip.set = sx150x_gpio_set;
  370. chip->gpio_chip.to_irq = sx150x_gpio_to_irq;
  371. chip->gpio_chip.base = pdata->gpio_base;
  372. chip->gpio_chip.can_sleep = 1;
  373. chip->gpio_chip.ngpio = chip->dev_cfg->ngpios;
  374. if (pdata->oscio_is_gpo)
  375. ++chip->gpio_chip.ngpio;
  376. chip->irq_chip.name = client->name;
  377. chip->irq_chip.mask = sx150x_irq_mask;
  378. chip->irq_chip.unmask = sx150x_irq_unmask;
  379. chip->irq_chip.set_type = sx150x_irq_set_type;
  380. chip->irq_chip.bus_lock = sx150x_irq_bus_lock;
  381. chip->irq_chip.bus_sync_unlock = sx150x_irq_bus_sync_unlock;
  382. chip->irq_summary = -1;
  383. chip->irq_base = -1;
  384. chip->irq_sense = 0;
  385. chip->irq_set_type_pending = 0;
  386. }
  387. static int sx150x_init_io(struct sx150x_chip *chip, u8 base, u16 cfg)
  388. {
  389. int err = 0;
  390. unsigned n;
  391. for (n = 0; err >= 0 && n < (chip->dev_cfg->ngpios / 8); ++n)
  392. err = sx150x_i2c_write(chip->client, base - n, cfg >> (n * 8));
  393. return err;
  394. }
  395. static int sx150x_reset(struct sx150x_chip *chip)
  396. {
  397. int err;
  398. err = i2c_smbus_write_byte_data(chip->client,
  399. chip->dev_cfg->reg_reset,
  400. 0x12);
  401. if (err < 0)
  402. return err;
  403. err = i2c_smbus_write_byte_data(chip->client,
  404. chip->dev_cfg->reg_reset,
  405. 0x34);
  406. return err;
  407. }
  408. static int sx150x_init_hw(struct sx150x_chip *chip,
  409. struct sx150x_platform_data *pdata)
  410. {
  411. int err = 0;
  412. if (pdata->reset_during_probe) {
  413. err = sx150x_reset(chip);
  414. if (err < 0)
  415. return err;
  416. }
  417. err = sx150x_i2c_write(chip->client,
  418. chip->dev_cfg->reg_misc,
  419. 0x01);
  420. if (err < 0)
  421. return err;
  422. err = sx150x_init_io(chip, chip->dev_cfg->reg_pullup,
  423. pdata->io_pullup_ena);
  424. if (err < 0)
  425. return err;
  426. err = sx150x_init_io(chip, chip->dev_cfg->reg_pulldn,
  427. pdata->io_pulldn_ena);
  428. if (err < 0)
  429. return err;
  430. err = sx150x_init_io(chip, chip->dev_cfg->reg_drain,
  431. pdata->io_open_drain_ena);
  432. if (err < 0)
  433. return err;
  434. err = sx150x_init_io(chip, chip->dev_cfg->reg_polarity,
  435. pdata->io_polarity);
  436. if (err < 0)
  437. return err;
  438. if (pdata->oscio_is_gpo)
  439. sx150x_set_oscio(chip, 0);
  440. return err;
  441. }
  442. static int sx150x_install_irq_chip(struct sx150x_chip *chip,
  443. int irq_summary,
  444. int irq_base)
  445. {
  446. int err;
  447. unsigned n;
  448. unsigned irq;
  449. chip->irq_summary = irq_summary;
  450. chip->irq_base = irq_base;
  451. for (n = 0; n < chip->dev_cfg->ngpios; ++n) {
  452. irq = irq_base + n;
  453. set_irq_chip_and_handler(irq, &chip->irq_chip, handle_edge_irq);
  454. set_irq_nested_thread(irq, 1);
  455. #ifdef CONFIG_ARM
  456. set_irq_flags(irq, IRQF_VALID);
  457. #else
  458. set_irq_noprobe(irq);
  459. #endif
  460. }
  461. err = request_threaded_irq(irq_summary,
  462. NULL,
  463. sx150x_irq_thread_fn,
  464. IRQF_SHARED | IRQF_TRIGGER_FALLING,
  465. chip->irq_chip.name,
  466. chip);
  467. if (err < 0) {
  468. chip->irq_summary = -1;
  469. chip->irq_base = -1;
  470. }
  471. return err;
  472. }
  473. static void sx150x_remove_irq_chip(struct sx150x_chip *chip)
  474. {
  475. unsigned n;
  476. unsigned irq;
  477. free_irq(chip->irq_summary, chip);
  478. for (n = 0; n < chip->dev_cfg->ngpios; ++n) {
  479. irq = chip->irq_base + n;
  480. set_irq_handler(irq, NULL);
  481. set_irq_chip(irq, NULL);
  482. }
  483. }
  484. static int __devinit sx150x_probe(struct i2c_client *client,
  485. const struct i2c_device_id *id)
  486. {
  487. static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
  488. I2C_FUNC_SMBUS_WRITE_WORD_DATA;
  489. struct sx150x_platform_data *pdata;
  490. struct sx150x_chip *chip;
  491. int rc;
  492. pdata = client->dev.platform_data;
  493. if (!pdata)
  494. return -EINVAL;
  495. if (!i2c_check_functionality(client->adapter, i2c_funcs))
  496. return -ENOSYS;
  497. chip = kzalloc(sizeof(struct sx150x_chip), GFP_KERNEL);
  498. if (!chip)
  499. return -ENOMEM;
  500. sx150x_init_chip(chip, client, id->driver_data, pdata);
  501. rc = sx150x_init_hw(chip, pdata);
  502. if (rc < 0)
  503. goto probe_fail_pre_gpiochip_add;
  504. rc = gpiochip_add(&chip->gpio_chip);
  505. if (rc < 0)
  506. goto probe_fail_pre_gpiochip_add;
  507. if (pdata->irq_summary >= 0) {
  508. rc = sx150x_install_irq_chip(chip,
  509. pdata->irq_summary,
  510. pdata->irq_base);
  511. if (rc < 0)
  512. goto probe_fail_post_gpiochip_add;
  513. }
  514. i2c_set_clientdata(client, chip);
  515. return 0;
  516. probe_fail_post_gpiochip_add:
  517. WARN_ON(gpiochip_remove(&chip->gpio_chip) < 0);
  518. probe_fail_pre_gpiochip_add:
  519. kfree(chip);
  520. return rc;
  521. }
  522. static int __devexit sx150x_remove(struct i2c_client *client)
  523. {
  524. struct sx150x_chip *chip;
  525. int rc;
  526. chip = i2c_get_clientdata(client);
  527. rc = gpiochip_remove(&chip->gpio_chip);
  528. if (rc < 0)
  529. return rc;
  530. if (chip->irq_summary >= 0)
  531. sx150x_remove_irq_chip(chip);
  532. kfree(chip);
  533. return 0;
  534. }
  535. static struct i2c_driver sx150x_driver = {
  536. .driver = {
  537. .name = "sx150x",
  538. .owner = THIS_MODULE
  539. },
  540. .probe = sx150x_probe,
  541. .remove = __devexit_p(sx150x_remove),
  542. .id_table = sx150x_id,
  543. };
  544. static int __init sx150x_init(void)
  545. {
  546. return i2c_add_driver(&sx150x_driver);
  547. }
  548. subsys_initcall(sx150x_init);
  549. static void __exit sx150x_exit(void)
  550. {
  551. return i2c_del_driver(&sx150x_driver);
  552. }
  553. module_exit(sx150x_exit);
  554. MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>");
  555. MODULE_DESCRIPTION("Driver for Semtech SX150X I2C GPIO Expanders");
  556. MODULE_LICENSE("GPL v2");
  557. MODULE_ALIAS("i2c:sx150x");