imx-dma.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424
  1. /*
  2. * drivers/dma/imx-dma.c
  3. *
  4. * This file contains a driver for the Freescale i.MX DMA engine
  5. * found on i.MX1/21/27
  6. *
  7. * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
  8. *
  9. * The code contained herein is licensed under the GNU General Public
  10. * License. You may obtain a copy of the GNU General Public License
  11. * Version 2 or later at the following locations:
  12. *
  13. * http://www.opensource.org/licenses/gpl-license.html
  14. * http://www.gnu.org/copyleft/gpl.html
  15. */
  16. #include <linux/init.h>
  17. #include <linux/types.h>
  18. #include <linux/mm.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/device.h>
  22. #include <linux/dma-mapping.h>
  23. #include <linux/slab.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/dmaengine.h>
  26. #include <asm/irq.h>
  27. #include <mach/dma-v1.h>
  28. #include <mach/hardware.h>
  29. struct imxdma_channel {
  30. struct imxdma_engine *imxdma;
  31. unsigned int channel;
  32. unsigned int imxdma_channel;
  33. enum dma_slave_buswidth word_size;
  34. dma_addr_t per_address;
  35. u32 watermark_level;
  36. struct dma_chan chan;
  37. spinlock_t lock;
  38. struct dma_async_tx_descriptor desc;
  39. dma_cookie_t last_completed;
  40. enum dma_status status;
  41. int dma_request;
  42. struct scatterlist *sg_list;
  43. };
  44. #define MAX_DMA_CHANNELS 8
  45. struct imxdma_engine {
  46. struct device *dev;
  47. struct dma_device dma_device;
  48. struct imxdma_channel channel[MAX_DMA_CHANNELS];
  49. };
  50. static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
  51. {
  52. return container_of(chan, struct imxdma_channel, chan);
  53. }
  54. static void imxdma_handle(struct imxdma_channel *imxdmac)
  55. {
  56. if (imxdmac->desc.callback)
  57. imxdmac->desc.callback(imxdmac->desc.callback_param);
  58. imxdmac->last_completed = imxdmac->desc.cookie;
  59. }
  60. static void imxdma_irq_handler(int channel, void *data)
  61. {
  62. struct imxdma_channel *imxdmac = data;
  63. imxdmac->status = DMA_SUCCESS;
  64. imxdma_handle(imxdmac);
  65. }
  66. static void imxdma_err_handler(int channel, void *data, int error)
  67. {
  68. struct imxdma_channel *imxdmac = data;
  69. imxdmac->status = DMA_ERROR;
  70. imxdma_handle(imxdmac);
  71. }
  72. static void imxdma_progression(int channel, void *data,
  73. struct scatterlist *sg)
  74. {
  75. struct imxdma_channel *imxdmac = data;
  76. imxdmac->status = DMA_SUCCESS;
  77. imxdma_handle(imxdmac);
  78. }
  79. static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
  80. unsigned long arg)
  81. {
  82. struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
  83. struct dma_slave_config *dmaengine_cfg = (void *)arg;
  84. int ret;
  85. unsigned int mode = 0;
  86. switch (cmd) {
  87. case DMA_TERMINATE_ALL:
  88. imxdmac->status = DMA_ERROR;
  89. imx_dma_disable(imxdmac->imxdma_channel);
  90. return 0;
  91. case DMA_SLAVE_CONFIG:
  92. if (dmaengine_cfg->direction == DMA_FROM_DEVICE) {
  93. imxdmac->per_address = dmaengine_cfg->src_addr;
  94. imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
  95. imxdmac->word_size = dmaengine_cfg->src_addr_width;
  96. } else {
  97. imxdmac->per_address = dmaengine_cfg->dst_addr;
  98. imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
  99. imxdmac->word_size = dmaengine_cfg->dst_addr_width;
  100. }
  101. switch (imxdmac->word_size) {
  102. case DMA_SLAVE_BUSWIDTH_1_BYTE:
  103. mode = IMX_DMA_MEMSIZE_8;
  104. break;
  105. case DMA_SLAVE_BUSWIDTH_2_BYTES:
  106. mode = IMX_DMA_MEMSIZE_16;
  107. break;
  108. default:
  109. case DMA_SLAVE_BUSWIDTH_4_BYTES:
  110. mode = IMX_DMA_MEMSIZE_32;
  111. break;
  112. }
  113. ret = imx_dma_config_channel(imxdmac->imxdma_channel,
  114. mode | IMX_DMA_TYPE_FIFO,
  115. IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
  116. imxdmac->dma_request, 1);
  117. if (ret)
  118. return ret;
  119. imx_dma_config_burstlen(imxdmac->imxdma_channel, imxdmac->watermark_level);
  120. return 0;
  121. default:
  122. return -ENOSYS;
  123. }
  124. return -EINVAL;
  125. }
  126. static enum dma_status imxdma_tx_status(struct dma_chan *chan,
  127. dma_cookie_t cookie,
  128. struct dma_tx_state *txstate)
  129. {
  130. struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
  131. dma_cookie_t last_used;
  132. enum dma_status ret;
  133. last_used = chan->cookie;
  134. ret = dma_async_is_complete(cookie, imxdmac->last_completed, last_used);
  135. dma_set_tx_state(txstate, imxdmac->last_completed, last_used, 0);
  136. return ret;
  137. }
  138. static dma_cookie_t imxdma_assign_cookie(struct imxdma_channel *imxdma)
  139. {
  140. dma_cookie_t cookie = imxdma->chan.cookie;
  141. if (++cookie < 0)
  142. cookie = 1;
  143. imxdma->chan.cookie = cookie;
  144. imxdma->desc.cookie = cookie;
  145. return cookie;
  146. }
  147. static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
  148. {
  149. struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
  150. dma_cookie_t cookie;
  151. spin_lock_irq(&imxdmac->lock);
  152. cookie = imxdma_assign_cookie(imxdmac);
  153. imx_dma_enable(imxdmac->imxdma_channel);
  154. spin_unlock_irq(&imxdmac->lock);
  155. return cookie;
  156. }
  157. static int imxdma_alloc_chan_resources(struct dma_chan *chan)
  158. {
  159. struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
  160. struct imx_dma_data *data = chan->private;
  161. imxdmac->dma_request = data->dma_request;
  162. dma_async_tx_descriptor_init(&imxdmac->desc, chan);
  163. imxdmac->desc.tx_submit = imxdma_tx_submit;
  164. /* txd.flags will be overwritten in prep funcs */
  165. imxdmac->desc.flags = DMA_CTRL_ACK;
  166. imxdmac->status = DMA_SUCCESS;
  167. return 0;
  168. }
  169. static void imxdma_free_chan_resources(struct dma_chan *chan)
  170. {
  171. struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
  172. imx_dma_disable(imxdmac->imxdma_channel);
  173. if (imxdmac->sg_list) {
  174. kfree(imxdmac->sg_list);
  175. imxdmac->sg_list = NULL;
  176. }
  177. }
  178. static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
  179. struct dma_chan *chan, struct scatterlist *sgl,
  180. unsigned int sg_len, enum dma_data_direction direction,
  181. unsigned long flags)
  182. {
  183. struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
  184. struct scatterlist *sg;
  185. int i, ret, dma_length = 0;
  186. unsigned int dmamode;
  187. if (imxdmac->status == DMA_IN_PROGRESS)
  188. return NULL;
  189. imxdmac->status = DMA_IN_PROGRESS;
  190. for_each_sg(sgl, sg, sg_len, i) {
  191. dma_length += sg->length;
  192. }
  193. if (direction == DMA_FROM_DEVICE)
  194. dmamode = DMA_MODE_READ;
  195. else
  196. dmamode = DMA_MODE_WRITE;
  197. ret = imx_dma_setup_sg(imxdmac->imxdma_channel, sgl, sg_len,
  198. dma_length, imxdmac->per_address, dmamode);
  199. if (ret)
  200. return NULL;
  201. return &imxdmac->desc;
  202. }
  203. static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
  204. struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
  205. size_t period_len, enum dma_data_direction direction)
  206. {
  207. struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
  208. struct imxdma_engine *imxdma = imxdmac->imxdma;
  209. int i, ret;
  210. unsigned int periods = buf_len / period_len;
  211. unsigned int dmamode;
  212. dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
  213. __func__, imxdmac->channel, buf_len, period_len);
  214. if (imxdmac->status == DMA_IN_PROGRESS)
  215. return NULL;
  216. imxdmac->status = DMA_IN_PROGRESS;
  217. ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
  218. imxdma_progression);
  219. if (ret) {
  220. dev_err(imxdma->dev, "Failed to setup the DMA handler\n");
  221. return NULL;
  222. }
  223. if (imxdmac->sg_list)
  224. kfree(imxdmac->sg_list);
  225. imxdmac->sg_list = kcalloc(periods + 1,
  226. sizeof(struct scatterlist), GFP_KERNEL);
  227. if (!imxdmac->sg_list)
  228. return NULL;
  229. sg_init_table(imxdmac->sg_list, periods);
  230. for (i = 0; i < periods; i++) {
  231. imxdmac->sg_list[i].page_link = 0;
  232. imxdmac->sg_list[i].offset = 0;
  233. imxdmac->sg_list[i].dma_address = dma_addr;
  234. imxdmac->sg_list[i].length = period_len;
  235. dma_addr += period_len;
  236. }
  237. /* close the loop */
  238. imxdmac->sg_list[periods].offset = 0;
  239. imxdmac->sg_list[periods].length = 0;
  240. imxdmac->sg_list[periods].page_link =
  241. ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
  242. if (direction == DMA_FROM_DEVICE)
  243. dmamode = DMA_MODE_READ;
  244. else
  245. dmamode = DMA_MODE_WRITE;
  246. ret = imx_dma_setup_sg(imxdmac->imxdma_channel, imxdmac->sg_list, periods,
  247. IMX_DMA_LENGTH_LOOP, imxdmac->per_address, dmamode);
  248. if (ret)
  249. return NULL;
  250. return &imxdmac->desc;
  251. }
  252. static void imxdma_issue_pending(struct dma_chan *chan)
  253. {
  254. /*
  255. * Nothing to do. We only have a single descriptor
  256. */
  257. }
  258. static int __init imxdma_probe(struct platform_device *pdev)
  259. {
  260. struct imxdma_engine *imxdma;
  261. int ret, i;
  262. imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
  263. if (!imxdma)
  264. return -ENOMEM;
  265. INIT_LIST_HEAD(&imxdma->dma_device.channels);
  266. /* Initialize channel parameters */
  267. for (i = 0; i < MAX_DMA_CHANNELS; i++) {
  268. struct imxdma_channel *imxdmac = &imxdma->channel[i];
  269. imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine",
  270. DMA_PRIO_MEDIUM);
  271. if ((int)imxdmac->channel < 0) {
  272. ret = -ENODEV;
  273. goto err_init;
  274. }
  275. imx_dma_setup_handlers(imxdmac->imxdma_channel,
  276. imxdma_irq_handler, imxdma_err_handler, imxdmac);
  277. imxdmac->imxdma = imxdma;
  278. spin_lock_init(&imxdmac->lock);
  279. dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
  280. dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
  281. imxdmac->chan.device = &imxdma->dma_device;
  282. imxdmac->chan.chan_id = i;
  283. imxdmac->channel = i;
  284. /* Add the channel to the DMAC list */
  285. list_add_tail(&imxdmac->chan.device_node, &imxdma->dma_device.channels);
  286. }
  287. imxdma->dev = &pdev->dev;
  288. imxdma->dma_device.dev = &pdev->dev;
  289. imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
  290. imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
  291. imxdma->dma_device.device_tx_status = imxdma_tx_status;
  292. imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
  293. imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
  294. imxdma->dma_device.device_control = imxdma_control;
  295. imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
  296. platform_set_drvdata(pdev, imxdma);
  297. ret = dma_async_device_register(&imxdma->dma_device);
  298. if (ret) {
  299. dev_err(&pdev->dev, "unable to register\n");
  300. goto err_init;
  301. }
  302. return 0;
  303. err_init:
  304. while (--i >= 0) {
  305. struct imxdma_channel *imxdmac = &imxdma->channel[i];
  306. imx_dma_free(imxdmac->imxdma_channel);
  307. }
  308. kfree(imxdma);
  309. return ret;
  310. }
  311. static int __exit imxdma_remove(struct platform_device *pdev)
  312. {
  313. struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
  314. int i;
  315. dma_async_device_unregister(&imxdma->dma_device);
  316. for (i = 0; i < MAX_DMA_CHANNELS; i++) {
  317. struct imxdma_channel *imxdmac = &imxdma->channel[i];
  318. imx_dma_free(imxdmac->imxdma_channel);
  319. }
  320. kfree(imxdma);
  321. return 0;
  322. }
  323. static struct platform_driver imxdma_driver = {
  324. .driver = {
  325. .name = "imx-dma",
  326. },
  327. .remove = __exit_p(imxdma_remove),
  328. };
  329. static int __init imxdma_module_init(void)
  330. {
  331. return platform_driver_probe(&imxdma_driver, imxdma_probe);
  332. }
  333. subsys_initcall(imxdma_module_init);
  334. MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
  335. MODULE_DESCRIPTION("i.MX dma driver");
  336. MODULE_LICENSE("GPL");