irq.c 2.2 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697
  1. /*
  2. * Toshiba RBTX4939 interrupt routines
  3. * Based on linux/arch/mips/txx9/rbtx4938/irq.c,
  4. * and RBTX49xx patch from CELF patch archive.
  5. *
  6. * Copyright (C) 2000-2001,2005-2006 Toshiba Corporation
  7. * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
  8. * terms of the GNU General Public License version 2. This program is
  9. * licensed "as is" without any warranty of any kind, whether express
  10. * or implied.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/irq.h>
  15. #include <asm/mipsregs.h>
  16. #include <asm/txx9/rbtx4939.h>
  17. /*
  18. * RBTX4939 IOC controller definition
  19. */
  20. static void rbtx4939_ioc_irq_unmask(unsigned int irq)
  21. {
  22. int ioc_nr = irq - RBTX4939_IRQ_IOC;
  23. writeb(readb(rbtx4939_ien_addr) | (1 << ioc_nr), rbtx4939_ien_addr);
  24. }
  25. static void rbtx4939_ioc_irq_mask(unsigned int irq)
  26. {
  27. int ioc_nr = irq - RBTX4939_IRQ_IOC;
  28. writeb(readb(rbtx4939_ien_addr) & ~(1 << ioc_nr), rbtx4939_ien_addr);
  29. mmiowb();
  30. }
  31. static struct irq_chip rbtx4939_ioc_irq_chip = {
  32. .name = "IOC",
  33. .ack = rbtx4939_ioc_irq_mask,
  34. .mask = rbtx4939_ioc_irq_mask,
  35. .mask_ack = rbtx4939_ioc_irq_mask,
  36. .unmask = rbtx4939_ioc_irq_unmask,
  37. };
  38. static inline int rbtx4939_ioc_irqroute(void)
  39. {
  40. unsigned char istat = readb(rbtx4939_ifac2_addr);
  41. if (unlikely(istat == 0))
  42. return -1;
  43. return RBTX4939_IRQ_IOC + __fls8(istat);
  44. }
  45. static int rbtx4939_irq_dispatch(int pending)
  46. {
  47. int irq;
  48. if (pending & CAUSEF_IP7)
  49. return MIPS_CPU_IRQ_BASE + 7;
  50. irq = tx4939_irq();
  51. if (likely(irq >= 0)) {
  52. /* redirect IOC interrupts */
  53. switch (irq) {
  54. case RBTX4939_IRQ_IOCINT:
  55. irq = rbtx4939_ioc_irqroute();
  56. break;
  57. }
  58. } else if (pending & CAUSEF_IP0)
  59. irq = MIPS_CPU_IRQ_BASE + 0;
  60. else if (pending & CAUSEF_IP1)
  61. irq = MIPS_CPU_IRQ_BASE + 1;
  62. else
  63. irq = -1;
  64. return irq;
  65. }
  66. void __init rbtx4939_irq_setup(void)
  67. {
  68. int i;
  69. /* mask all IOC interrupts */
  70. writeb(0, rbtx4939_ien_addr);
  71. /* clear SoftInt interrupts */
  72. writeb(0, rbtx4939_softint_addr);
  73. txx9_irq_dispatch = rbtx4939_irq_dispatch;
  74. tx4939_irq_init();
  75. for (i = RBTX4939_IRQ_IOC;
  76. i < RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC; i++)
  77. set_irq_chip_and_handler(i, &rbtx4939_ioc_irq_chip,
  78. handle_level_irq);
  79. set_irq_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq);
  80. }