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arm
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mach-s5pv310
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include
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mach
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regs-clock.h

regs-clock.h 3.2 KB
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  1. /* linux/arch/arm/mach-s5pv310/include/mach/regs-clock.h
    2. 

  2.  *
    3. 

  3.  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
    4. 

  4.  *		http://www.samsung.com/
    5. 

  5.  *
    6. 

  6.  * S5PV310 - Clock register definitions
    7. 

  7.  *
    8. 

  8.  * This program is free software; you can redistribute it and/or modify
    9. 

  9.  * it under the terms of the GNU General Public License version 2 as
    10. 

  10.  * published by the Free Software Foundation.
    11. 

  11. */
    12. 

  12. 

  13. #ifndef __ASM_ARCH_REGS_CLOCK_H
    14. 

  14. #define __ASM_ARCH_REGS_CLOCK_H __FILE__
    15. 

  15. 

  16. #include <mach/map.h>
    17. 

  17. 

  18. #define S5P_CLKREG(x)			(S5P_VA_CMU + (x))
    19. 

  19. 

  20. #define S5P_INFORM0			S5P_CLKREG(0x800)
    21. 

  21. 

  22. #define S5P_EPLL_CON0			S5P_CLKREG(0x0C110)
    23. 

  23. #define S5P_EPLL_CON1			S5P_CLKREG(0x0C114)
    24. 

  24. #define S5P_VPLL_CON0			S5P_CLKREG(0x0C120)
    25. 

  25. #define S5P_VPLL_CON1			S5P_CLKREG(0x0C124)
    26. 

  26. 

  27. #define S5P_CLKSRC_TOP0			S5P_CLKREG(0x0C210)
    28. 

  28. #define S5P_CLKSRC_TOP1			S5P_CLKREG(0x0C214)
    29. 

  29. #define S5P_CLKSRC_CAM			S5P_CLKREG(0x0C220)
    30. 

  30. #define S5P_CLKSRC_IMAGE		S5P_CLKREG(0x0C230)
    31. 

  31. #define S5P_CLKSRC_LCD0			S5P_CLKREG(0x0C234)
    32. 

  32. #define S5P_CLKSRC_LCD1			S5P_CLKREG(0x0C238)
    33. 

  33. #define S5P_CLKSRC_FSYS			S5P_CLKREG(0x0C240)
    34. 

  34. #define S5P_CLKSRC_PERIL0		S5P_CLKREG(0x0C250)
    35. 

  35. #define S5P_CLKSRC_PERIL1		S5P_CLKREG(0x0C254)
    36. 

  36. 

  37. #define S5P_CLKDIV_TOP			S5P_CLKREG(0x0C510)
    38. 

  38. #define S5P_CLKDIV_CAM			S5P_CLKREG(0x0C520)
    39. 

  39. #define S5P_CLKDIV_IMAGE		S5P_CLKREG(0x0C530)
    40. 

  40. #define S5P_CLKDIV_LCD0			S5P_CLKREG(0x0C534)
    41. 

  41. #define S5P_CLKDIV_LCD1			S5P_CLKREG(0x0C538)
    42. 

  42. #define S5P_CLKDIV_FSYS0		S5P_CLKREG(0x0C540)
    43. 

  43. #define S5P_CLKDIV_FSYS1		S5P_CLKREG(0x0C544)
    44. 

  44. #define S5P_CLKDIV_FSYS2		S5P_CLKREG(0x0C548)
    45. 

  45. #define S5P_CLKDIV_FSYS3		S5P_CLKREG(0x0C54C)
    46. 

  46. #define S5P_CLKDIV_PERIL0		S5P_CLKREG(0x0C550)
    47. 

  47. #define S5P_CLKDIV_PERIL1		S5P_CLKREG(0x0C554)
    48. 

  48. #define S5P_CLKDIV_PERIL2		S5P_CLKREG(0x0C558)
    49. 

  49. #define S5P_CLKDIV_PERIL3		S5P_CLKREG(0x0C55C)
    50. 

  50. #define S5P_CLKDIV_PERIL4		S5P_CLKREG(0x0C560)
    51. 

  51. #define S5P_CLKDIV_PERIL5		S5P_CLKREG(0x0C564)
    52. 

  52. 

  53. #define S5P_CLKSRC_MASK_TOP		S5P_CLKREG(0x0C310)
    54. 

  54. #define S5P_CLKSRC_MASK_CAM		S5P_CLKREG(0x0C320)
    55. 

  55. #define S5P_CLKSRC_MASK_LCD0		S5P_CLKREG(0x0C334)
    56. 

  56. #define S5P_CLKSRC_MASK_LCD1		S5P_CLKREG(0x0C338)
    57. 

  57. #define S5P_CLKSRC_MASK_FSYS		S5P_CLKREG(0x0C340)
    58. 

  58. #define S5P_CLKSRC_MASK_PERIL0		S5P_CLKREG(0x0C350)
    59. 

  59. #define S5P_CLKSRC_MASK_PERIL1		S5P_CLKREG(0x0C354)
    60. 

  60. 

  61. #define S5P_CLKGATE_IP_CAM		S5P_CLKREG(0x0C920)
    62. 

  62. #define S5P_CLKGATE_IP_IMAGE		S5P_CLKREG(0x0C930)
    63. 

  63. #define S5P_CLKGATE_IP_LCD0		S5P_CLKREG(0x0C934)
    64. 

  64. #define S5P_CLKGATE_IP_LCD1		S5P_CLKREG(0x0C938)
    65. 

  65. #define S5P_CLKGATE_IP_FSYS		S5P_CLKREG(0x0C940)
    66. 

  66. #define S5P_CLKGATE_IP_PERIL		S5P_CLKREG(0x0C950)
    67. 

  67. #define S5P_CLKGATE_IP_PERIR		S5P_CLKREG(0x0C960)
    68. 

  68. 

  69. #define S5P_CLKSRC_CORE			S5P_CLKREG(0x10200)
    70. 

  70. #define S5P_CLKDIV_CORE0		S5P_CLKREG(0x10500)
    71. 

  71. 

  72. #define S5P_APLL_LOCK			S5P_CLKREG(0x14000)
    73. 

  73. #define S5P_MPLL_LOCK			S5P_CLKREG(0x14004)
    74. 

  74. #define S5P_APLL_CON0			S5P_CLKREG(0x14100)
    75. 

  75. #define S5P_APLL_CON1			S5P_CLKREG(0x14104)
    76. 

  76. #define S5P_MPLL_CON0			S5P_CLKREG(0x14108)
    77. 

  77. #define S5P_MPLL_CON1			S5P_CLKREG(0x1410C)
    78. 

  78. 

  79. #define S5P_CLKSRC_CPU			S5P_CLKREG(0x14200)
    80. 

  80. #define S5P_CLKMUX_STATCPU		S5P_CLKREG(0x14400)
    81. 

  81. 

  82. #define S5P_CLKDIV_CPU			S5P_CLKREG(0x14500)
    83. 

  83. #define S5P_CLKDIV_STATCPU		S5P_CLKREG(0x14600)
    84. 

  84. 

  85. #define S5P_CLKGATE_SCLKCPU		S5P_CLKREG(0x14800)
    86. 

  86. 

  87. /* Compatibility defines */
    88. 

  88. 

  89. #define S5P_EPLL_CON			S5P_EPLL_CON0
    90. 

  90. 

  91. #endif /* __ASM_ARCH_REGS_CLOCK_H */
    92.