mach-torbreck.c 3.2 KB

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  1. /* linux/arch/arm/mach-s5pv210/mach-torbreck.c
  2. *
  3. * Copyright (c) 2010 aESOP Community
  4. * http://www.aesop.or.kr/
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/types.h>
  12. #include <linux/i2c.h>
  13. #include <linux/init.h>
  14. #include <linux/serial_core.h>
  15. #include <asm/mach/arch.h>
  16. #include <asm/mach/map.h>
  17. #include <asm/setup.h>
  18. #include <asm/mach-types.h>
  19. #include <mach/map.h>
  20. #include <mach/regs-clock.h>
  21. #include <plat/regs-serial.h>
  22. #include <plat/s5pv210.h>
  23. #include <plat/devs.h>
  24. #include <plat/cpu.h>
  25. #include <plat/iic.h>
  26. /* Following are default values for UCON, ULCON and UFCON UART registers */
  27. #define TORBRECK_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
  28. S3C2410_UCON_RXILEVEL | \
  29. S3C2410_UCON_TXIRQMODE | \
  30. S3C2410_UCON_RXIRQMODE | \
  31. S3C2410_UCON_RXFIFO_TOI | \
  32. S3C2443_UCON_RXERR_IRQEN)
  33. #define TORBRECK_ULCON_DEFAULT S3C2410_LCON_CS8
  34. #define TORBRECK_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
  35. S5PV210_UFCON_TXTRIG4 | \
  36. S5PV210_UFCON_RXTRIG4)
  37. static struct s3c2410_uartcfg torbreck_uartcfgs[] __initdata = {
  38. [0] = {
  39. .hwport = 0,
  40. .flags = 0,
  41. .ucon = TORBRECK_UCON_DEFAULT,
  42. .ulcon = TORBRECK_ULCON_DEFAULT,
  43. .ufcon = TORBRECK_UFCON_DEFAULT,
  44. },
  45. [1] = {
  46. .hwport = 1,
  47. .flags = 0,
  48. .ucon = TORBRECK_UCON_DEFAULT,
  49. .ulcon = TORBRECK_ULCON_DEFAULT,
  50. .ufcon = TORBRECK_UFCON_DEFAULT,
  51. },
  52. [2] = {
  53. .hwport = 2,
  54. .flags = 0,
  55. .ucon = TORBRECK_UCON_DEFAULT,
  56. .ulcon = TORBRECK_ULCON_DEFAULT,
  57. .ufcon = TORBRECK_UFCON_DEFAULT,
  58. },
  59. [3] = {
  60. .hwport = 3,
  61. .flags = 0,
  62. .ucon = TORBRECK_UCON_DEFAULT,
  63. .ulcon = TORBRECK_ULCON_DEFAULT,
  64. .ufcon = TORBRECK_UFCON_DEFAULT,
  65. },
  66. };
  67. static struct platform_device *torbreck_devices[] __initdata = {
  68. &s5pv210_device_iis0,
  69. &s3c_device_cfcon,
  70. &s3c_device_hsmmc0,
  71. &s3c_device_hsmmc1,
  72. &s3c_device_hsmmc2,
  73. &s3c_device_hsmmc3,
  74. &s3c_device_i2c0,
  75. &s3c_device_i2c1,
  76. &s3c_device_i2c2,
  77. &s3c_device_rtc,
  78. &s3c_device_wdt,
  79. };
  80. static struct i2c_board_info torbreck_i2c_devs0[] __initdata = {
  81. /* To Be Updated */
  82. };
  83. static struct i2c_board_info torbreck_i2c_devs1[] __initdata = {
  84. /* To Be Updated */
  85. };
  86. static struct i2c_board_info torbreck_i2c_devs2[] __initdata = {
  87. /* To Be Updated */
  88. };
  89. static void __init torbreck_map_io(void)
  90. {
  91. s5p_init_io(NULL, 0, S5P_VA_CHIPID);
  92. s3c24xx_init_clocks(24000000);
  93. s3c24xx_init_uarts(torbreck_uartcfgs, ARRAY_SIZE(torbreck_uartcfgs));
  94. }
  95. static void __init torbreck_machine_init(void)
  96. {
  97. s3c_i2c0_set_platdata(NULL);
  98. s3c_i2c1_set_platdata(NULL);
  99. s3c_i2c2_set_platdata(NULL);
  100. i2c_register_board_info(0, torbreck_i2c_devs0,
  101. ARRAY_SIZE(torbreck_i2c_devs0));
  102. i2c_register_board_info(1, torbreck_i2c_devs1,
  103. ARRAY_SIZE(torbreck_i2c_devs1));
  104. i2c_register_board_info(2, torbreck_i2c_devs2,
  105. ARRAY_SIZE(torbreck_i2c_devs2));
  106. platform_add_devices(torbreck_devices, ARRAY_SIZE(torbreck_devices));
  107. }
  108. MACHINE_START(TORBRECK, "TORBRECK")
  109. /* Maintainer: Hyunchul Ko <ghcstop@gmail.com> */
  110. .boot_params = S5P_PA_SDRAM + 0x100,
  111. .init_irq = s5pv210_init_irq,
  112. .map_io = torbreck_map_io,
  113. .init_machine = torbreck_machine_init,
  114. .timer = &s3c24xx_timer,
  115. MACHINE_END