mce_amd_64.c 15 KB

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  1. /*
  2. * (c) 2005, 2006 Advanced Micro Devices, Inc.
  3. * Your use of this code is subject to the terms and conditions of the
  4. * GNU general public license version 2. See "COPYING" or
  5. * http://www.gnu.org/licenses/gpl.html
  6. *
  7. * Written by Jacob Shin - AMD, Inc.
  8. *
  9. * Support : jacob.shin@amd.com
  10. *
  11. * April 2006
  12. * - added support for AMD Family 0x10 processors
  13. *
  14. * All MC4_MISCi registers are shared between multi-cores
  15. */
  16. #include <linux/interrupt.h>
  17. #include <linux/notifier.h>
  18. #include <linux/kobject.h>
  19. #include <linux/sysdev.h>
  20. #include <linux/errno.h>
  21. #include <linux/sched.h>
  22. #include <linux/sysfs.h>
  23. #include <linux/init.h>
  24. #include <linux/cpu.h>
  25. #include <linux/smp.h>
  26. #include <asm/percpu.h>
  27. #include <asm/apic.h>
  28. #include <asm/idle.h>
  29. #include <asm/mce.h>
  30. #include <asm/msr.h>
  31. #define PFX "mce_threshold: "
  32. #define VERSION "version 1.1.1"
  33. #define NR_BANKS 6
  34. #define NR_BLOCKS 9
  35. #define THRESHOLD_MAX 0xFFF
  36. #define INT_TYPE_APIC 0x00020000
  37. #define MASK_VALID_HI 0x80000000
  38. #define MASK_CNTP_HI 0x40000000
  39. #define MASK_LOCKED_HI 0x20000000
  40. #define MASK_LVTOFF_HI 0x00F00000
  41. #define MASK_COUNT_EN_HI 0x00080000
  42. #define MASK_INT_TYPE_HI 0x00060000
  43. #define MASK_OVERFLOW_HI 0x00010000
  44. #define MASK_ERR_COUNT_HI 0x00000FFF
  45. #define MASK_BLKPTR_LO 0xFF000000
  46. #define MCG_XBLK_ADDR 0xC0000400
  47. struct threshold_block {
  48. unsigned int block;
  49. unsigned int bank;
  50. unsigned int cpu;
  51. u32 address;
  52. u16 interrupt_enable;
  53. u16 threshold_limit;
  54. struct kobject kobj;
  55. struct list_head miscj;
  56. };
  57. /* defaults used early on boot */
  58. static struct threshold_block threshold_defaults = {
  59. .interrupt_enable = 0,
  60. .threshold_limit = THRESHOLD_MAX,
  61. };
  62. struct threshold_bank {
  63. struct kobject *kobj;
  64. struct threshold_block *blocks;
  65. cpumask_var_t cpus;
  66. };
  67. static DEFINE_PER_CPU(struct threshold_bank *, threshold_banks[NR_BANKS]);
  68. #ifdef CONFIG_SMP
  69. static unsigned char shared_bank[NR_BANKS] = {
  70. 0, 0, 0, 0, 1
  71. };
  72. #endif
  73. static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
  74. static void amd_threshold_interrupt(void);
  75. /*
  76. * CPU Initialization
  77. */
  78. struct thresh_restart {
  79. struct threshold_block *b;
  80. int reset;
  81. u16 old_limit;
  82. };
  83. /* must be called with correct cpu affinity */
  84. /* Called via smp_call_function_single() */
  85. static void threshold_restart_bank(void *_tr)
  86. {
  87. struct thresh_restart *tr = _tr;
  88. u32 mci_misc_hi, mci_misc_lo;
  89. rdmsr(tr->b->address, mci_misc_lo, mci_misc_hi);
  90. if (tr->b->threshold_limit < (mci_misc_hi & THRESHOLD_MAX))
  91. tr->reset = 1; /* limit cannot be lower than err count */
  92. if (tr->reset) { /* reset err count and overflow bit */
  93. mci_misc_hi =
  94. (mci_misc_hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
  95. (THRESHOLD_MAX - tr->b->threshold_limit);
  96. } else if (tr->old_limit) { /* change limit w/o reset */
  97. int new_count = (mci_misc_hi & THRESHOLD_MAX) +
  98. (tr->old_limit - tr->b->threshold_limit);
  99. mci_misc_hi = (mci_misc_hi & ~MASK_ERR_COUNT_HI) |
  100. (new_count & THRESHOLD_MAX);
  101. }
  102. tr->b->interrupt_enable ?
  103. (mci_misc_hi = (mci_misc_hi & ~MASK_INT_TYPE_HI) | INT_TYPE_APIC) :
  104. (mci_misc_hi &= ~MASK_INT_TYPE_HI);
  105. mci_misc_hi |= MASK_COUNT_EN_HI;
  106. wrmsr(tr->b->address, mci_misc_lo, mci_misc_hi);
  107. }
  108. /* cpu init entry point, called from mce.c with preempt off */
  109. void mce_amd_feature_init(struct cpuinfo_x86 *c)
  110. {
  111. unsigned int cpu = smp_processor_id();
  112. u32 low = 0, high = 0, address = 0;
  113. unsigned int bank, block;
  114. struct thresh_restart tr;
  115. u8 lvt_off;
  116. for (bank = 0; bank < NR_BANKS; ++bank) {
  117. for (block = 0; block < NR_BLOCKS; ++block) {
  118. if (block == 0)
  119. address = MSR_IA32_MC0_MISC + bank * 4;
  120. else if (block == 1) {
  121. address = (low & MASK_BLKPTR_LO) >> 21;
  122. if (!address)
  123. break;
  124. address += MCG_XBLK_ADDR;
  125. } else
  126. ++address;
  127. if (rdmsr_safe(address, &low, &high))
  128. break;
  129. if (!(high & MASK_VALID_HI)) {
  130. if (block)
  131. continue;
  132. else
  133. break;
  134. }
  135. if (!(high & MASK_CNTP_HI) ||
  136. (high & MASK_LOCKED_HI))
  137. continue;
  138. if (!block)
  139. per_cpu(bank_map, cpu) |= (1 << bank);
  140. #ifdef CONFIG_SMP
  141. if (shared_bank[bank] && c->cpu_core_id)
  142. break;
  143. #endif
  144. lvt_off = setup_APIC_eilvt_mce(THRESHOLD_APIC_VECTOR,
  145. APIC_EILVT_MSG_FIX, 0);
  146. high &= ~MASK_LVTOFF_HI;
  147. high |= lvt_off << 20;
  148. wrmsr(address, low, high);
  149. threshold_defaults.address = address;
  150. tr.b = &threshold_defaults;
  151. tr.reset = 0;
  152. tr.old_limit = 0;
  153. threshold_restart_bank(&tr);
  154. mce_threshold_vector = amd_threshold_interrupt;
  155. }
  156. }
  157. }
  158. /*
  159. * APIC Interrupt Handler
  160. */
  161. /*
  162. * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
  163. * the interrupt goes off when error_count reaches threshold_limit.
  164. * the handler will simply log mcelog w/ software defined bank number.
  165. */
  166. static void amd_threshold_interrupt(void)
  167. {
  168. u32 low = 0, high = 0, address = 0;
  169. unsigned int bank, block;
  170. struct mce m;
  171. mce_setup(&m);
  172. /* assume first bank caused it */
  173. for (bank = 0; bank < NR_BANKS; ++bank) {
  174. if (!(per_cpu(bank_map, m.cpu) & (1 << bank)))
  175. continue;
  176. for (block = 0; block < NR_BLOCKS; ++block) {
  177. if (block == 0) {
  178. address = MSR_IA32_MC0_MISC + bank * 4;
  179. } else if (block == 1) {
  180. address = (low & MASK_BLKPTR_LO) >> 21;
  181. if (!address)
  182. break;
  183. address += MCG_XBLK_ADDR;
  184. } else {
  185. ++address;
  186. }
  187. if (rdmsr_safe(address, &low, &high))
  188. break;
  189. if (!(high & MASK_VALID_HI)) {
  190. if (block)
  191. continue;
  192. else
  193. break;
  194. }
  195. if (!(high & MASK_CNTP_HI) ||
  196. (high & MASK_LOCKED_HI))
  197. continue;
  198. /*
  199. * Log the machine check that caused the threshold
  200. * event.
  201. */
  202. machine_check_poll(MCP_TIMESTAMP,
  203. &__get_cpu_var(mce_poll_banks));
  204. if (high & MASK_OVERFLOW_HI) {
  205. rdmsrl(address, m.misc);
  206. rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,
  207. m.status);
  208. m.bank = K8_MCE_THRESHOLD_BASE
  209. + bank * NR_BLOCKS
  210. + block;
  211. mce_log(&m);
  212. return;
  213. }
  214. }
  215. }
  216. }
  217. /*
  218. * Sysfs Interface
  219. */
  220. struct threshold_attr {
  221. struct attribute attr;
  222. ssize_t (*show) (struct threshold_block *, char *);
  223. ssize_t (*store) (struct threshold_block *, const char *, size_t count);
  224. };
  225. #define SHOW_FIELDS(name) \
  226. static ssize_t show_ ## name(struct threshold_block *b, char *buf) \
  227. { \
  228. return sprintf(buf, "%lx\n", (unsigned long) b->name); \
  229. }
  230. SHOW_FIELDS(interrupt_enable)
  231. SHOW_FIELDS(threshold_limit)
  232. static ssize_t
  233. store_interrupt_enable(struct threshold_block *b, const char *buf, size_t count)
  234. {
  235. struct thresh_restart tr;
  236. unsigned long new;
  237. char *end;
  238. new = simple_strtoul(buf, &end, 0);
  239. if (end == buf)
  240. return -EINVAL;
  241. b->interrupt_enable = !!new;
  242. tr.b = b;
  243. tr.reset = 0;
  244. tr.old_limit = 0;
  245. smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
  246. return end - buf;
  247. }
  248. static ssize_t
  249. store_threshold_limit(struct threshold_block *b, const char *buf, size_t count)
  250. {
  251. struct thresh_restart tr;
  252. unsigned long new;
  253. char *end;
  254. new = simple_strtoul(buf, &end, 0);
  255. if (end == buf)
  256. return -EINVAL;
  257. if (new > THRESHOLD_MAX)
  258. new = THRESHOLD_MAX;
  259. if (new < 1)
  260. new = 1;
  261. tr.old_limit = b->threshold_limit;
  262. b->threshold_limit = new;
  263. tr.b = b;
  264. tr.reset = 0;
  265. smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
  266. return end - buf;
  267. }
  268. struct threshold_block_cross_cpu {
  269. struct threshold_block *tb;
  270. long retval;
  271. };
  272. static void local_error_count_handler(void *_tbcc)
  273. {
  274. struct threshold_block_cross_cpu *tbcc = _tbcc;
  275. struct threshold_block *b = tbcc->tb;
  276. u32 low, high;
  277. rdmsr(b->address, low, high);
  278. tbcc->retval = (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit);
  279. }
  280. static ssize_t show_error_count(struct threshold_block *b, char *buf)
  281. {
  282. struct threshold_block_cross_cpu tbcc = { .tb = b, };
  283. smp_call_function_single(b->cpu, local_error_count_handler, &tbcc, 1);
  284. return sprintf(buf, "%lx\n", tbcc.retval);
  285. }
  286. static ssize_t store_error_count(struct threshold_block *b,
  287. const char *buf, size_t count)
  288. {
  289. struct thresh_restart tr = { .b = b, .reset = 1, .old_limit = 0 };
  290. smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
  291. return 1;
  292. }
  293. #define THRESHOLD_ATTR(_name, _mode, _show, _store) \
  294. { \
  295. .attr = {.name = __stringify(_name), .mode = _mode }, \
  296. .show = _show, \
  297. .store = _store, \
  298. };
  299. #define RW_ATTR(name) \
  300. static struct threshold_attr name = \
  301. THRESHOLD_ATTR(name, 0644, show_## name, store_## name)
  302. RW_ATTR(interrupt_enable);
  303. RW_ATTR(threshold_limit);
  304. RW_ATTR(error_count);
  305. static struct attribute *default_attrs[] = {
  306. &interrupt_enable.attr,
  307. &threshold_limit.attr,
  308. &error_count.attr,
  309. NULL
  310. };
  311. #define to_block(k) container_of(k, struct threshold_block, kobj)
  312. #define to_attr(a) container_of(a, struct threshold_attr, attr)
  313. static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
  314. {
  315. struct threshold_block *b = to_block(kobj);
  316. struct threshold_attr *a = to_attr(attr);
  317. ssize_t ret;
  318. ret = a->show ? a->show(b, buf) : -EIO;
  319. return ret;
  320. }
  321. static ssize_t store(struct kobject *kobj, struct attribute *attr,
  322. const char *buf, size_t count)
  323. {
  324. struct threshold_block *b = to_block(kobj);
  325. struct threshold_attr *a = to_attr(attr);
  326. ssize_t ret;
  327. ret = a->store ? a->store(b, buf, count) : -EIO;
  328. return ret;
  329. }
  330. static struct sysfs_ops threshold_ops = {
  331. .show = show,
  332. .store = store,
  333. };
  334. static struct kobj_type threshold_ktype = {
  335. .sysfs_ops = &threshold_ops,
  336. .default_attrs = default_attrs,
  337. };
  338. static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
  339. unsigned int bank,
  340. unsigned int block,
  341. u32 address)
  342. {
  343. struct threshold_block *b = NULL;
  344. u32 low, high;
  345. int err;
  346. if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))
  347. return 0;
  348. if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
  349. return 0;
  350. if (!(high & MASK_VALID_HI)) {
  351. if (block)
  352. goto recurse;
  353. else
  354. return 0;
  355. }
  356. if (!(high & MASK_CNTP_HI) ||
  357. (high & MASK_LOCKED_HI))
  358. goto recurse;
  359. b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
  360. if (!b)
  361. return -ENOMEM;
  362. b->block = block;
  363. b->bank = bank;
  364. b->cpu = cpu;
  365. b->address = address;
  366. b->interrupt_enable = 0;
  367. b->threshold_limit = THRESHOLD_MAX;
  368. INIT_LIST_HEAD(&b->miscj);
  369. if (per_cpu(threshold_banks, cpu)[bank]->blocks) {
  370. list_add(&b->miscj,
  371. &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
  372. } else {
  373. per_cpu(threshold_banks, cpu)[bank]->blocks = b;
  374. }
  375. err = kobject_init_and_add(&b->kobj, &threshold_ktype,
  376. per_cpu(threshold_banks, cpu)[bank]->kobj,
  377. "misc%i", block);
  378. if (err)
  379. goto out_free;
  380. recurse:
  381. if (!block) {
  382. address = (low & MASK_BLKPTR_LO) >> 21;
  383. if (!address)
  384. return 0;
  385. address += MCG_XBLK_ADDR;
  386. } else {
  387. ++address;
  388. }
  389. err = allocate_threshold_blocks(cpu, bank, ++block, address);
  390. if (err)
  391. goto out_free;
  392. if (b)
  393. kobject_uevent(&b->kobj, KOBJ_ADD);
  394. return err;
  395. out_free:
  396. if (b) {
  397. kobject_put(&b->kobj);
  398. kfree(b);
  399. }
  400. return err;
  401. }
  402. static __cpuinit long
  403. local_allocate_threshold_blocks(int cpu, unsigned int bank)
  404. {
  405. return allocate_threshold_blocks(cpu, bank, 0,
  406. MSR_IA32_MC0_MISC + bank * 4);
  407. }
  408. /* symlinks sibling shared banks to first core. first core owns dir/files. */
  409. static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
  410. {
  411. int i, err = 0;
  412. struct threshold_bank *b = NULL;
  413. char name[32];
  414. sprintf(name, "threshold_bank%i", bank);
  415. #ifdef CONFIG_SMP
  416. if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) { /* symlink */
  417. i = cpumask_first(cpu_core_mask(cpu));
  418. /* first core not up yet */
  419. if (cpu_data(i).cpu_core_id)
  420. goto out;
  421. /* already linked */
  422. if (per_cpu(threshold_banks, cpu)[bank])
  423. goto out;
  424. b = per_cpu(threshold_banks, i)[bank];
  425. if (!b)
  426. goto out;
  427. err = sysfs_create_link(&per_cpu(mce_dev, cpu).kobj,
  428. b->kobj, name);
  429. if (err)
  430. goto out;
  431. cpumask_copy(b->cpus, cpu_core_mask(cpu));
  432. per_cpu(threshold_banks, cpu)[bank] = b;
  433. goto out;
  434. }
  435. #endif
  436. b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
  437. if (!b) {
  438. err = -ENOMEM;
  439. goto out;
  440. }
  441. if (!alloc_cpumask_var(&b->cpus, GFP_KERNEL)) {
  442. kfree(b);
  443. err = -ENOMEM;
  444. goto out;
  445. }
  446. b->kobj = kobject_create_and_add(name, &per_cpu(mce_dev, cpu).kobj);
  447. if (!b->kobj)
  448. goto out_free;
  449. #ifndef CONFIG_SMP
  450. cpumask_setall(b->cpus);
  451. #else
  452. cpumask_copy(b->cpus, cpu_core_mask(cpu));
  453. #endif
  454. per_cpu(threshold_banks, cpu)[bank] = b;
  455. err = local_allocate_threshold_blocks(cpu, bank);
  456. if (err)
  457. goto out_free;
  458. for_each_cpu(i, b->cpus) {
  459. if (i == cpu)
  460. continue;
  461. err = sysfs_create_link(&per_cpu(mce_dev, i).kobj,
  462. b->kobj, name);
  463. if (err)
  464. goto out;
  465. per_cpu(threshold_banks, i)[bank] = b;
  466. }
  467. goto out;
  468. out_free:
  469. per_cpu(threshold_banks, cpu)[bank] = NULL;
  470. free_cpumask_var(b->cpus);
  471. kfree(b);
  472. out:
  473. return err;
  474. }
  475. /* create dir/files for all valid threshold banks */
  476. static __cpuinit int threshold_create_device(unsigned int cpu)
  477. {
  478. unsigned int bank;
  479. int err = 0;
  480. for (bank = 0; bank < NR_BANKS; ++bank) {
  481. if (!(per_cpu(bank_map, cpu) & (1 << bank)))
  482. continue;
  483. err = threshold_create_bank(cpu, bank);
  484. if (err)
  485. goto out;
  486. }
  487. out:
  488. return err;
  489. }
  490. /*
  491. * let's be hotplug friendly.
  492. * in case of multiple core processors, the first core always takes ownership
  493. * of shared sysfs dir/files, and rest of the cores will be symlinked to it.
  494. */
  495. static void deallocate_threshold_block(unsigned int cpu,
  496. unsigned int bank)
  497. {
  498. struct threshold_block *pos = NULL;
  499. struct threshold_block *tmp = NULL;
  500. struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
  501. if (!head)
  502. return;
  503. list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
  504. kobject_put(&pos->kobj);
  505. list_del(&pos->miscj);
  506. kfree(pos);
  507. }
  508. kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
  509. per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
  510. }
  511. static void threshold_remove_bank(unsigned int cpu, int bank)
  512. {
  513. struct threshold_bank *b;
  514. char name[32];
  515. int i = 0;
  516. b = per_cpu(threshold_banks, cpu)[bank];
  517. if (!b)
  518. return;
  519. if (!b->blocks)
  520. goto free_out;
  521. sprintf(name, "threshold_bank%i", bank);
  522. #ifdef CONFIG_SMP
  523. /* sibling symlink */
  524. if (shared_bank[bank] && b->blocks->cpu != cpu) {
  525. sysfs_remove_link(&per_cpu(mce_dev, cpu).kobj, name);
  526. per_cpu(threshold_banks, cpu)[bank] = NULL;
  527. return;
  528. }
  529. #endif
  530. /* remove all sibling symlinks before unregistering */
  531. for_each_cpu(i, b->cpus) {
  532. if (i == cpu)
  533. continue;
  534. sysfs_remove_link(&per_cpu(mce_dev, i).kobj, name);
  535. per_cpu(threshold_banks, i)[bank] = NULL;
  536. }
  537. deallocate_threshold_block(cpu, bank);
  538. free_out:
  539. kobject_del(b->kobj);
  540. kobject_put(b->kobj);
  541. free_cpumask_var(b->cpus);
  542. kfree(b);
  543. per_cpu(threshold_banks, cpu)[bank] = NULL;
  544. }
  545. static void threshold_remove_device(unsigned int cpu)
  546. {
  547. unsigned int bank;
  548. for (bank = 0; bank < NR_BANKS; ++bank) {
  549. if (!(per_cpu(bank_map, cpu) & (1 << bank)))
  550. continue;
  551. threshold_remove_bank(cpu, bank);
  552. }
  553. }
  554. /* get notified when a cpu comes on/off */
  555. static void __cpuinit
  556. amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu)
  557. {
  558. if (cpu >= NR_CPUS)
  559. return;
  560. switch (action) {
  561. case CPU_ONLINE:
  562. case CPU_ONLINE_FROZEN:
  563. threshold_create_device(cpu);
  564. break;
  565. case CPU_DEAD:
  566. case CPU_DEAD_FROZEN:
  567. threshold_remove_device(cpu);
  568. break;
  569. default:
  570. break;
  571. }
  572. }
  573. static __init int threshold_init_device(void)
  574. {
  575. unsigned lcpu = 0;
  576. /* to hit CPUs online before the notifier is up */
  577. for_each_online_cpu(lcpu) {
  578. int err = threshold_create_device(lcpu);
  579. if (err)
  580. return err;
  581. }
  582. threshold_cpu_callback = amd_64_threshold_cpu_callback;
  583. return 0;
  584. }
  585. device_initcall(threshold_init_device);