netxen_nic.h 45 KB

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  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen Inc,
  26. * 18922 Forge Drive
  27. * Cupertino, CA 95014-0701
  28. *
  29. */
  30. #ifndef _NETXEN_NIC_H_
  31. #define _NETXEN_NIC_H_
  32. #include <linux/module.h>
  33. #include <linux/kernel.h>
  34. #include <linux/types.h>
  35. #include <linux/ioport.h>
  36. #include <linux/pci.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/etherdevice.h>
  39. #include <linux/ip.h>
  40. #include <linux/in.h>
  41. #include <linux/tcp.h>
  42. #include <linux/skbuff.h>
  43. #include <linux/firmware.h>
  44. #include <linux/ethtool.h>
  45. #include <linux/mii.h>
  46. #include <linux/timer.h>
  47. #include <linux/vmalloc.h>
  48. #include <asm/io.h>
  49. #include <asm/byteorder.h>
  50. #include "netxen_nic_hw.h"
  51. #define _NETXEN_NIC_LINUX_MAJOR 4
  52. #define _NETXEN_NIC_LINUX_MINOR 0
  53. #define _NETXEN_NIC_LINUX_SUBVERSION 30
  54. #define NETXEN_NIC_LINUX_VERSIONID "4.0.30"
  55. #define NETXEN_VERSION_CODE(a, b, c) (((a) << 16) + ((b) << 8) + (c))
  56. #define NETXEN_NUM_FLASH_SECTORS (64)
  57. #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
  58. #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
  59. * NETXEN_FLASH_SECTOR_SIZE)
  60. #define PHAN_VENDOR_ID 0x4040
  61. #define RCV_DESC_RINGSIZE(rds_ring) \
  62. (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
  63. #define RCV_BUFF_RINGSIZE(rds_ring) \
  64. (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
  65. #define STATUS_DESC_RINGSIZE(sds_ring) \
  66. (sizeof(struct status_desc) * (sds_ring)->num_desc)
  67. #define TX_BUFF_RINGSIZE(tx_ring) \
  68. (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
  69. #define TX_DESC_RINGSIZE(tx_ring) \
  70. (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
  71. #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
  72. #define NETXEN_RCV_PRODUCER_OFFSET 0
  73. #define NETXEN_RCV_PEG_DB_ID 2
  74. #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
  75. #define FLASH_SUCCESS 0
  76. #define ADDR_IN_WINDOW1(off) \
  77. ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
  78. /*
  79. * normalize a 64MB crb address to 32MB PCI window
  80. * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
  81. */
  82. #define NETXEN_CRB_NORMAL(reg) \
  83. ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
  84. #define NETXEN_CRB_NORMALIZE(adapter, reg) \
  85. pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
  86. #define DB_NORMALIZE(adapter, off) \
  87. (adapter->ahw.db_base + (off))
  88. #define NX_P2_C0 0x24
  89. #define NX_P2_C1 0x25
  90. #define NX_P3_A0 0x30
  91. #define NX_P3_A2 0x30
  92. #define NX_P3_B0 0x40
  93. #define NX_P3_B1 0x41
  94. #define NX_P3_B2 0x42
  95. #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
  96. #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
  97. #define FIRST_PAGE_GROUP_START 0
  98. #define FIRST_PAGE_GROUP_END 0x100000
  99. #define SECOND_PAGE_GROUP_START 0x6000000
  100. #define SECOND_PAGE_GROUP_END 0x68BC000
  101. #define THIRD_PAGE_GROUP_START 0x70E4000
  102. #define THIRD_PAGE_GROUP_END 0x8000000
  103. #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
  104. #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
  105. #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
  106. #define P2_MAX_MTU (8000)
  107. #define P3_MAX_MTU (9600)
  108. #define NX_ETHERMTU 1500
  109. #define NX_MAX_ETHERHDR 32 /* This contains some padding */
  110. #define NX_RX_NORMAL_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
  111. #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
  112. #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
  113. #define NX_CT_DEFAULT_RX_BUF_LEN 2048
  114. #define MAX_RX_BUFFER_LENGTH 1760
  115. #define MAX_RX_JUMBO_BUFFER_LENGTH 8062
  116. #define MAX_RX_LRO_BUFFER_LENGTH (8062)
  117. #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2)
  118. #define RX_JUMBO_DMA_MAP_LEN \
  119. (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
  120. #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2)
  121. /*
  122. * Maximum number of ring contexts
  123. */
  124. #define MAX_RING_CTX 1
  125. /* Opcodes to be used with the commands */
  126. #define TX_ETHER_PKT 0x01
  127. #define TX_TCP_PKT 0x02
  128. #define TX_UDP_PKT 0x03
  129. #define TX_IP_PKT 0x04
  130. #define TX_TCP_LSO 0x05
  131. #define TX_TCP_LSO6 0x06
  132. #define TX_IPSEC 0x07
  133. #define TX_IPSEC_CMD 0x0a
  134. #define TX_TCPV6_PKT 0x0b
  135. #define TX_UDPV6_PKT 0x0c
  136. /* The following opcodes are for internal consumption. */
  137. #define NETXEN_CONTROL_OP 0x10
  138. #define PEGNET_REQUEST 0x11
  139. #define MAX_NUM_CARDS 4
  140. #define MAX_BUFFERS_PER_CMD 32
  141. #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + 4)
  142. /*
  143. * Following are the states of the Phantom. Phantom will set them and
  144. * Host will read to check if the fields are correct.
  145. */
  146. #define PHAN_INITIALIZE_START 0xff00
  147. #define PHAN_INITIALIZE_FAILED 0xffff
  148. #define PHAN_INITIALIZE_COMPLETE 0xff01
  149. /* Host writes the following to notify that it has done the init-handshake */
  150. #define PHAN_INITIALIZE_ACK 0xf00f
  151. #define NUM_RCV_DESC_RINGS 3
  152. #define NUM_STS_DESC_RINGS 4
  153. #define RCV_RING_NORMAL 0
  154. #define RCV_RING_JUMBO 1
  155. #define RCV_RING_LRO 2
  156. #define MAX_CMD_DESCRIPTORS 4096
  157. #define MAX_RCV_DESCRIPTORS 16384
  158. #define MAX_CMD_DESCRIPTORS_HOST 1024
  159. #define MAX_RCV_DESCRIPTORS_1G 2048
  160. #define MAX_RCV_DESCRIPTORS_10G 4096
  161. #define MAX_JUMBO_RCV_DESCRIPTORS 1024
  162. #define MAX_LRO_RCV_DESCRIPTORS 8
  163. #define NETXEN_CTX_SIGNATURE 0xdee0
  164. #define NETXEN_CTX_SIGNATURE_V2 0x0002dee0
  165. #define NETXEN_CTX_RESET 0xbad0
  166. #define NETXEN_RCV_PRODUCER(ringid) (ringid)
  167. #define PHAN_PEG_RCV_INITIALIZED 0xff01
  168. #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
  169. #define get_next_index(index, length) \
  170. (((index) + 1) & ((length) - 1))
  171. #define get_index_range(index,length,count) \
  172. (((index) + (count)) & ((length) - 1))
  173. #define MPORT_SINGLE_FUNCTION_MODE 0x1111
  174. #define MPORT_MULTI_FUNCTION_MODE 0x2222
  175. #include "netxen_nic_phan_reg.h"
  176. /*
  177. * NetXen host-peg signal message structure
  178. *
  179. * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
  180. * Bit 2 : priv_id => must be 1
  181. * Bit 3-17 : count => for doorbell
  182. * Bit 18-27 : ctx_id => Context id
  183. * Bit 28-31 : opcode
  184. */
  185. typedef u32 netxen_ctx_msg;
  186. #define netxen_set_msg_peg_id(config_word, val) \
  187. ((config_word) &= ~3, (config_word) |= val & 3)
  188. #define netxen_set_msg_privid(config_word) \
  189. ((config_word) |= 1 << 2)
  190. #define netxen_set_msg_count(config_word, val) \
  191. ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
  192. #define netxen_set_msg_ctxid(config_word, val) \
  193. ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
  194. #define netxen_set_msg_opcode(config_word, val) \
  195. ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
  196. struct netxen_rcv_ring {
  197. __le64 addr;
  198. __le32 size;
  199. __le32 rsrvd;
  200. };
  201. struct netxen_sts_ring {
  202. __le64 addr;
  203. __le32 size;
  204. __le16 msi_index;
  205. __le16 rsvd;
  206. } ;
  207. struct netxen_ring_ctx {
  208. /* one command ring */
  209. __le64 cmd_consumer_offset;
  210. __le64 cmd_ring_addr;
  211. __le32 cmd_ring_size;
  212. __le32 rsrvd;
  213. /* three receive rings */
  214. struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS];
  215. __le64 sts_ring_addr;
  216. __le32 sts_ring_size;
  217. __le32 ctx_id;
  218. __le64 rsrvd_2[3];
  219. __le32 sts_ring_count;
  220. __le32 rsrvd_3;
  221. struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS];
  222. } __attribute__ ((aligned(64)));
  223. /*
  224. * Following data structures describe the descriptors that will be used.
  225. * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
  226. * we are doing LSO (above the 1500 size packet) only.
  227. */
  228. /*
  229. * The size of reference handle been changed to 16 bits to pass the MSS fields
  230. * for the LSO packet
  231. */
  232. #define FLAGS_CHECKSUM_ENABLED 0x01
  233. #define FLAGS_LSO_ENABLED 0x02
  234. #define FLAGS_IPSEC_SA_ADD 0x04
  235. #define FLAGS_IPSEC_SA_DELETE 0x08
  236. #define FLAGS_VLAN_TAGGED 0x10
  237. #define netxen_set_cmd_desc_port(cmd_desc, var) \
  238. ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
  239. #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
  240. ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
  241. #define netxen_set_tx_port(_desc, _port) \
  242. (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
  243. #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
  244. (_desc)->flags_opcode = \
  245. cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
  246. #define netxen_set_tx_frags_len(_desc, _frags, _len) \
  247. (_desc)->num_of_buffers_total_length = \
  248. cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
  249. struct cmd_desc_type0 {
  250. u8 tcp_hdr_offset; /* For LSO only */
  251. u8 ip_hdr_offset; /* For LSO only */
  252. /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
  253. __le16 flags_opcode;
  254. /* Bit pattern: 0-7 total number of segments,
  255. 8-31 Total size of the packet */
  256. __le32 num_of_buffers_total_length;
  257. union {
  258. struct {
  259. __le32 addr_low_part2;
  260. __le32 addr_high_part2;
  261. };
  262. __le64 addr_buffer2;
  263. };
  264. __le16 reference_handle; /* changed to u16 to add mss */
  265. __le16 mss; /* passed by NDIS_PACKET for LSO */
  266. /* Bit pattern 0-3 port, 0-3 ctx id */
  267. u8 port_ctxid;
  268. u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
  269. __le16 conn_id; /* IPSec offoad only */
  270. union {
  271. struct {
  272. __le32 addr_low_part3;
  273. __le32 addr_high_part3;
  274. };
  275. __le64 addr_buffer3;
  276. };
  277. union {
  278. struct {
  279. __le32 addr_low_part1;
  280. __le32 addr_high_part1;
  281. };
  282. __le64 addr_buffer1;
  283. };
  284. __le16 buffer_length[4];
  285. union {
  286. struct {
  287. __le32 addr_low_part4;
  288. __le32 addr_high_part4;
  289. };
  290. __le64 addr_buffer4;
  291. };
  292. __le64 unused;
  293. } __attribute__ ((aligned(64)));
  294. /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
  295. struct rcv_desc {
  296. __le16 reference_handle;
  297. __le16 reserved;
  298. __le32 buffer_length; /* allocated buffer length (usually 2K) */
  299. __le64 addr_buffer;
  300. };
  301. /* opcode field in status_desc */
  302. #define NETXEN_NIC_RXPKT_DESC 0x04
  303. #define NETXEN_OLD_RXPKT_DESC 0x3f
  304. #define NETXEN_NIC_RESPONSE_DESC 0x05
  305. /* for status field in status_desc */
  306. #define STATUS_NEED_CKSUM (1)
  307. #define STATUS_CKSUM_OK (2)
  308. /* owner bits of status_desc */
  309. #define STATUS_OWNER_HOST (0x1ULL << 56)
  310. #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
  311. /* Status descriptor:
  312. 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
  313. 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
  314. 53-55 desc_cnt, 56-57 owner, 58-63 opcode
  315. */
  316. #define netxen_get_sts_port(sts_data) \
  317. ((sts_data) & 0x0F)
  318. #define netxen_get_sts_status(sts_data) \
  319. (((sts_data) >> 4) & 0x0F)
  320. #define netxen_get_sts_type(sts_data) \
  321. (((sts_data) >> 8) & 0x0F)
  322. #define netxen_get_sts_totallength(sts_data) \
  323. (((sts_data) >> 12) & 0xFFFF)
  324. #define netxen_get_sts_refhandle(sts_data) \
  325. (((sts_data) >> 28) & 0xFFFF)
  326. #define netxen_get_sts_prot(sts_data) \
  327. (((sts_data) >> 44) & 0x0F)
  328. #define netxen_get_sts_pkt_offset(sts_data) \
  329. (((sts_data) >> 48) & 0x1F)
  330. #define netxen_get_sts_desc_cnt(sts_data) \
  331. (((sts_data) >> 53) & 0x7)
  332. #define netxen_get_sts_opcode(sts_data) \
  333. (((sts_data) >> 58) & 0x03F)
  334. struct status_desc {
  335. __le64 status_desc_data[2];
  336. } __attribute__ ((aligned(16)));
  337. /* The version of the main data structure */
  338. #define NETXEN_BDINFO_VERSION 1
  339. /* Magic number to let user know flash is programmed */
  340. #define NETXEN_BDINFO_MAGIC 0x12345678
  341. /* Max number of Gig ports on a Phantom board */
  342. #define NETXEN_MAX_PORTS 4
  343. #define NETXEN_BRDTYPE_P1_BD 0x0000
  344. #define NETXEN_BRDTYPE_P1_SB 0x0001
  345. #define NETXEN_BRDTYPE_P1_SMAX 0x0002
  346. #define NETXEN_BRDTYPE_P1_SOCK 0x0003
  347. #define NETXEN_BRDTYPE_P2_SOCK_31 0x0008
  348. #define NETXEN_BRDTYPE_P2_SOCK_35 0x0009
  349. #define NETXEN_BRDTYPE_P2_SB35_4G 0x000a
  350. #define NETXEN_BRDTYPE_P2_SB31_10G 0x000b
  351. #define NETXEN_BRDTYPE_P2_SB31_2G 0x000c
  352. #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d
  353. #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e
  354. #define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f
  355. #define NETXEN_BRDTYPE_P3_REF_QG 0x0021
  356. #define NETXEN_BRDTYPE_P3_HMEZ 0x0022
  357. #define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023
  358. #define NETXEN_BRDTYPE_P3_4_GB 0x0024
  359. #define NETXEN_BRDTYPE_P3_IMEZ 0x0025
  360. #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026
  361. #define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027
  362. #define NETXEN_BRDTYPE_P3_XG_LOM 0x0028
  363. #define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029
  364. #define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a
  365. #define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b
  366. #define NETXEN_BRDTYPE_P3_10G_CX4 0x0031
  367. #define NETXEN_BRDTYPE_P3_10G_XFP 0x0032
  368. #define NETXEN_BRDTYPE_P3_10G_TP 0x0080
  369. struct netxen_board_info {
  370. u32 header_version;
  371. u32 board_mfg;
  372. u32 board_type;
  373. u32 board_num;
  374. u32 chip_id;
  375. u32 chip_minor;
  376. u32 chip_major;
  377. u32 chip_pkg;
  378. u32 chip_lot;
  379. u32 port_mask; /* available niu ports */
  380. u32 peg_mask; /* available pegs */
  381. u32 icache_ok; /* can we run with icache? */
  382. u32 dcache_ok; /* can we run with dcache? */
  383. u32 casper_ok;
  384. u32 mac_addr_lo_0;
  385. u32 mac_addr_lo_1;
  386. u32 mac_addr_lo_2;
  387. u32 mac_addr_lo_3;
  388. /* MN-related config */
  389. u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */
  390. u32 mn_sync_shift_cclk;
  391. u32 mn_sync_shift_mclk;
  392. u32 mn_wb_en;
  393. u32 mn_crystal_freq; /* in MHz */
  394. u32 mn_speed; /* in MHz */
  395. u32 mn_org;
  396. u32 mn_depth;
  397. u32 mn_ranks_0; /* ranks per slot */
  398. u32 mn_ranks_1; /* ranks per slot */
  399. u32 mn_rd_latency_0;
  400. u32 mn_rd_latency_1;
  401. u32 mn_rd_latency_2;
  402. u32 mn_rd_latency_3;
  403. u32 mn_rd_latency_4;
  404. u32 mn_rd_latency_5;
  405. u32 mn_rd_latency_6;
  406. u32 mn_rd_latency_7;
  407. u32 mn_rd_latency_8;
  408. u32 mn_dll_val[18];
  409. u32 mn_mode_reg; /* MIU DDR Mode Register */
  410. u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */
  411. u32 mn_timing_0; /* MIU Memory Control Timing Rgister */
  412. u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */
  413. u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */
  414. /* SN-related config */
  415. u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
  416. u32 sn_pt_mode; /* pass through mode */
  417. u32 sn_ecc_en;
  418. u32 sn_wb_en;
  419. u32 sn_crystal_freq;
  420. u32 sn_speed;
  421. u32 sn_org;
  422. u32 sn_depth;
  423. u32 sn_dll_tap;
  424. u32 sn_rd_latency;
  425. u32 mac_addr_hi_0;
  426. u32 mac_addr_hi_1;
  427. u32 mac_addr_hi_2;
  428. u32 mac_addr_hi_3;
  429. u32 magic; /* indicates flash has been initialized */
  430. u32 mn_rdimm;
  431. u32 mn_dll_override;
  432. };
  433. #define FLASH_NUM_PORTS (4)
  434. struct netxen_flash_mac_addr {
  435. u32 flash_addr[32];
  436. };
  437. struct netxen_user_old_info {
  438. u8 flash_md5[16];
  439. u8 crbinit_md5[16];
  440. u8 brdcfg_md5[16];
  441. /* bootloader */
  442. u32 bootld_version;
  443. u32 bootld_size;
  444. u8 bootld_md5[16];
  445. /* image */
  446. u32 image_version;
  447. u32 image_size;
  448. u8 image_md5[16];
  449. /* primary image status */
  450. u32 primary_status;
  451. u32 secondary_present;
  452. /* MAC address , 4 ports */
  453. struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
  454. };
  455. #define FLASH_NUM_MAC_PER_PORT 32
  456. struct netxen_user_info {
  457. u8 flash_md5[16 * 64];
  458. /* bootloader */
  459. u32 bootld_version;
  460. u32 bootld_size;
  461. /* image */
  462. u32 image_version;
  463. u32 image_size;
  464. /* primary image status */
  465. u32 primary_status;
  466. u32 secondary_present;
  467. /* MAC address , 4 ports, 32 address per port */
  468. u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
  469. u32 sub_sys_id;
  470. u8 serial_num[32];
  471. /* Any user defined data */
  472. };
  473. /*
  474. * Flash Layout - new format.
  475. */
  476. struct netxen_new_user_info {
  477. u8 flash_md5[16 * 64];
  478. /* bootloader */
  479. u32 bootld_version;
  480. u32 bootld_size;
  481. /* image */
  482. u32 image_version;
  483. u32 image_size;
  484. /* primary image status */
  485. u32 primary_status;
  486. u32 secondary_present;
  487. /* MAC address , 4 ports, 32 address per port */
  488. u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
  489. u32 sub_sys_id;
  490. u8 serial_num[32];
  491. /* Any user defined data */
  492. };
  493. #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
  494. #define SECONDARY_IMAGE_ABSENT 0xffffffff
  495. #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a
  496. #define PRIMARY_IMAGE_BAD 0xffffffff
  497. /* Flash memory map */
  498. #define NETXEN_CRBINIT_START 0 /* crbinit section */
  499. #define NETXEN_BRDCFG_START 0x4000 /* board config */
  500. #define NETXEN_INITCODE_START 0x6000 /* pegtune code */
  501. #define NETXEN_BOOTLD_START 0x10000 /* bootld */
  502. #define NETXEN_IMAGE_START 0x43000 /* compressed image */
  503. #define NETXEN_SECONDARY_START 0x200000 /* backup images */
  504. #define NETXEN_PXE_START 0x3E0000 /* PXE boot rom */
  505. #define NETXEN_USER_START 0x3E8000 /* Firmare info */
  506. #define NETXEN_FIXED_START 0x3F0000 /* backup of crbinit */
  507. #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408)
  508. #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c)
  509. #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c)
  510. #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128)
  511. #define NX_FW_MIN_SIZE (0x3fffff)
  512. #define NX_P2_MN_ROMIMAGE 0
  513. #define NX_P3_CT_ROMIMAGE 1
  514. #define NX_P3_MN_ROMIMAGE 2
  515. #define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */
  516. #define NETXEN_FLASH_START (NETXEN_CRBINIT_START)
  517. #define NETXEN_INIT_SECTOR (0)
  518. #define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START)
  519. #define NETXEN_FLASH_CRBINIT_SIZE (0x4000)
  520. #define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info))
  521. #define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32))
  522. #define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START)
  523. #define NETXEN_NUM_PRIMARY_SECTORS (0x20)
  524. #define NETXEN_NUM_CONFIG_SECTORS (1)
  525. extern char netxen_nic_driver_name[];
  526. /* Number of status descriptors to handle per interrupt */
  527. #define MAX_STATUS_HANDLE (64)
  528. /*
  529. * netxen_skb_frag{} is to contain mapping info for each SG list. This
  530. * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
  531. */
  532. struct netxen_skb_frag {
  533. u64 dma;
  534. u64 length;
  535. };
  536. #define _netxen_set_bits(config_word, start, bits, val) {\
  537. unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
  538. unsigned long long __tvalue = (val); \
  539. (config_word) &= ~__tmask; \
  540. (config_word) |= (((__tvalue) << (start)) & __tmask); \
  541. }
  542. #define _netxen_clear_bits(config_word, start, bits) {\
  543. unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \
  544. (config_word) &= ~__tmask; \
  545. }
  546. /* Following defines are for the state of the buffers */
  547. #define NETXEN_BUFFER_FREE 0
  548. #define NETXEN_BUFFER_BUSY 1
  549. /*
  550. * There will be one netxen_buffer per skb packet. These will be
  551. * used to save the dma info for pci_unmap_page()
  552. */
  553. struct netxen_cmd_buffer {
  554. struct sk_buff *skb;
  555. struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
  556. u32 frag_count;
  557. };
  558. /* In rx_buffer, we do not need multiple fragments as is a single buffer */
  559. struct netxen_rx_buffer {
  560. struct list_head list;
  561. struct sk_buff *skb;
  562. u64 dma;
  563. u16 ref_handle;
  564. u16 state;
  565. };
  566. /* Board types */
  567. #define NETXEN_NIC_GBE 0x01
  568. #define NETXEN_NIC_XGBE 0x02
  569. /*
  570. * One hardware_context{} per adapter
  571. * contains interrupt info as well shared hardware info.
  572. */
  573. struct netxen_hardware_context {
  574. void __iomem *pci_base0;
  575. void __iomem *pci_base1;
  576. void __iomem *pci_base2;
  577. void __iomem *db_base;
  578. unsigned long db_len;
  579. unsigned long pci_len0;
  580. int qdr_sn_window;
  581. int ddr_mn_window;
  582. unsigned long mn_win_crb;
  583. unsigned long ms_win_crb;
  584. u8 cut_through;
  585. u8 revision_id;
  586. u8 pci_func;
  587. u8 linkup;
  588. u16 port_type;
  589. u16 board_type;
  590. };
  591. #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
  592. #define ETHERNET_FCS_SIZE 4
  593. struct netxen_adapter_stats {
  594. u64 xmitcalled;
  595. u64 xmitfinished;
  596. u64 rxdropped;
  597. u64 txdropped;
  598. u64 csummed;
  599. u64 no_rcv;
  600. u64 rxbytes;
  601. u64 txbytes;
  602. };
  603. /*
  604. * Rcv Descriptor Context. One such per Rcv Descriptor. There may
  605. * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
  606. */
  607. struct nx_host_rds_ring {
  608. u32 producer;
  609. u32 crb_rcv_producer;
  610. u32 num_desc;
  611. u32 dma_size;
  612. u32 skb_size;
  613. u32 flags;
  614. struct rcv_desc *desc_head;
  615. struct netxen_rx_buffer *rx_buf_arr;
  616. struct list_head free_list;
  617. spinlock_t lock;
  618. dma_addr_t phys_addr;
  619. };
  620. struct nx_host_sds_ring {
  621. u32 consumer;
  622. u32 crb_sts_consumer;
  623. u32 crb_intr_mask;
  624. u32 num_desc;
  625. struct status_desc *desc_head;
  626. struct netxen_adapter *adapter;
  627. struct napi_struct napi;
  628. struct list_head free_list[NUM_RCV_DESC_RINGS];
  629. int irq;
  630. dma_addr_t phys_addr;
  631. char name[IFNAMSIZ+4];
  632. };
  633. struct nx_host_tx_ring {
  634. u32 producer;
  635. __le32 *hw_consumer;
  636. u32 sw_consumer;
  637. u32 crb_cmd_producer;
  638. u32 crb_cmd_consumer;
  639. u32 num_desc;
  640. struct netxen_cmd_buffer *cmd_buf_arr;
  641. struct cmd_desc_type0 *desc_head;
  642. dma_addr_t phys_addr;
  643. };
  644. /*
  645. * Receive context. There is one such structure per instance of the
  646. * receive processing. Any state information that is relevant to
  647. * the receive, and is must be in this structure. The global data may be
  648. * present elsewhere.
  649. */
  650. struct netxen_recv_context {
  651. u32 state;
  652. u16 context_id;
  653. u16 virt_port;
  654. struct nx_host_rds_ring *rds_rings;
  655. struct nx_host_sds_ring *sds_rings;
  656. struct netxen_ring_ctx *hwctx;
  657. dma_addr_t phys_addr;
  658. };
  659. /* New HW context creation */
  660. #define NX_OS_CRB_RETRY_COUNT 4000
  661. #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
  662. (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
  663. #define NX_CDRP_CLEAR 0x00000000
  664. #define NX_CDRP_CMD_BIT 0x80000000
  665. /*
  666. * All responses must have the NX_CDRP_CMD_BIT cleared
  667. * in the crb NX_CDRP_CRB_OFFSET.
  668. */
  669. #define NX_CDRP_FORM_RSP(rsp) (rsp)
  670. #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
  671. #define NX_CDRP_RSP_OK 0x00000001
  672. #define NX_CDRP_RSP_FAIL 0x00000002
  673. #define NX_CDRP_RSP_TIMEOUT 0x00000003
  674. /*
  675. * All commands must have the NX_CDRP_CMD_BIT set in
  676. * the crb NX_CDRP_CRB_OFFSET.
  677. */
  678. #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
  679. #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
  680. #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
  681. #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
  682. #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
  683. #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
  684. #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
  685. #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
  686. #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
  687. #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
  688. #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
  689. #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
  690. #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
  691. #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
  692. #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
  693. #define NX_CDRP_CMD_SET_MTU 0x00000012
  694. #define NX_CDRP_CMD_MAX 0x00000013
  695. #define NX_RCODE_SUCCESS 0
  696. #define NX_RCODE_NO_HOST_MEM 1
  697. #define NX_RCODE_NO_HOST_RESOURCE 2
  698. #define NX_RCODE_NO_CARD_CRB 3
  699. #define NX_RCODE_NO_CARD_MEM 4
  700. #define NX_RCODE_NO_CARD_RESOURCE 5
  701. #define NX_RCODE_INVALID_ARGS 6
  702. #define NX_RCODE_INVALID_ACTION 7
  703. #define NX_RCODE_INVALID_STATE 8
  704. #define NX_RCODE_NOT_SUPPORTED 9
  705. #define NX_RCODE_NOT_PERMITTED 10
  706. #define NX_RCODE_NOT_READY 11
  707. #define NX_RCODE_DOES_NOT_EXIST 12
  708. #define NX_RCODE_ALREADY_EXISTS 13
  709. #define NX_RCODE_BAD_SIGNATURE 14
  710. #define NX_RCODE_CMD_NOT_IMPL 15
  711. #define NX_RCODE_CMD_INVALID 16
  712. #define NX_RCODE_TIMEOUT 17
  713. #define NX_RCODE_CMD_FAILED 18
  714. #define NX_RCODE_MAX_EXCEEDED 19
  715. #define NX_RCODE_MAX 20
  716. #define NX_DESTROY_CTX_RESET 0
  717. #define NX_DESTROY_CTX_D3_RESET 1
  718. #define NX_DESTROY_CTX_MAX 2
  719. /*
  720. * Capabilities
  721. */
  722. #define NX_CAP_BIT(class, bit) (1 << bit)
  723. #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
  724. #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
  725. #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
  726. #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
  727. #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
  728. #define NX_CAP0_LRO NX_CAP_BIT(0, 5)
  729. #define NX_CAP0_LSO NX_CAP_BIT(0, 6)
  730. #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
  731. #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
  732. /*
  733. * Context state
  734. */
  735. #define NX_HOST_CTX_STATE_FREED 0
  736. #define NX_HOST_CTX_STATE_ALLOCATED 1
  737. #define NX_HOST_CTX_STATE_ACTIVE 2
  738. #define NX_HOST_CTX_STATE_DISABLED 3
  739. #define NX_HOST_CTX_STATE_QUIESCED 4
  740. #define NX_HOST_CTX_STATE_MAX 5
  741. /*
  742. * Rx context
  743. */
  744. typedef struct {
  745. __le64 host_phys_addr; /* Ring base addr */
  746. __le32 ring_size; /* Ring entries */
  747. __le16 msi_index;
  748. __le16 rsvd; /* Padding */
  749. } nx_hostrq_sds_ring_t;
  750. typedef struct {
  751. __le64 host_phys_addr; /* Ring base addr */
  752. __le64 buff_size; /* Packet buffer size */
  753. __le32 ring_size; /* Ring entries */
  754. __le32 ring_kind; /* Class of ring */
  755. } nx_hostrq_rds_ring_t;
  756. typedef struct {
  757. __le64 host_rsp_dma_addr; /* Response dma'd here */
  758. __le32 capabilities[4]; /* Flag bit vector */
  759. __le32 host_int_crb_mode; /* Interrupt crb usage */
  760. __le32 host_rds_crb_mode; /* RDS crb usage */
  761. /* These ring offsets are relative to data[0] below */
  762. __le32 rds_ring_offset; /* Offset to RDS config */
  763. __le32 sds_ring_offset; /* Offset to SDS config */
  764. __le16 num_rds_rings; /* Count of RDS rings */
  765. __le16 num_sds_rings; /* Count of SDS rings */
  766. __le16 rsvd1; /* Padding */
  767. __le16 rsvd2; /* Padding */
  768. u8 reserved[128]; /* reserve space for future expansion*/
  769. /* MUST BE 64-bit aligned.
  770. The following is packed:
  771. - N hostrq_rds_rings
  772. - N hostrq_sds_rings */
  773. char data[0];
  774. } nx_hostrq_rx_ctx_t;
  775. typedef struct {
  776. __le32 host_producer_crb; /* Crb to use */
  777. __le32 rsvd1; /* Padding */
  778. } nx_cardrsp_rds_ring_t;
  779. typedef struct {
  780. __le32 host_consumer_crb; /* Crb to use */
  781. __le32 interrupt_crb; /* Crb to use */
  782. } nx_cardrsp_sds_ring_t;
  783. typedef struct {
  784. /* These ring offsets are relative to data[0] below */
  785. __le32 rds_ring_offset; /* Offset to RDS config */
  786. __le32 sds_ring_offset; /* Offset to SDS config */
  787. __le32 host_ctx_state; /* Starting State */
  788. __le32 num_fn_per_port; /* How many PCI fn share the port */
  789. __le16 num_rds_rings; /* Count of RDS rings */
  790. __le16 num_sds_rings; /* Count of SDS rings */
  791. __le16 context_id; /* Handle for context */
  792. u8 phys_port; /* Physical id of port */
  793. u8 virt_port; /* Virtual/Logical id of port */
  794. u8 reserved[128]; /* save space for future expansion */
  795. /* MUST BE 64-bit aligned.
  796. The following is packed:
  797. - N cardrsp_rds_rings
  798. - N cardrs_sds_rings */
  799. char data[0];
  800. } nx_cardrsp_rx_ctx_t;
  801. #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
  802. (sizeof(HOSTRQ_RX) + \
  803. (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
  804. (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
  805. #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
  806. (sizeof(CARDRSP_RX) + \
  807. (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
  808. (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
  809. /*
  810. * Tx context
  811. */
  812. typedef struct {
  813. __le64 host_phys_addr; /* Ring base addr */
  814. __le32 ring_size; /* Ring entries */
  815. __le32 rsvd; /* Padding */
  816. } nx_hostrq_cds_ring_t;
  817. typedef struct {
  818. __le64 host_rsp_dma_addr; /* Response dma'd here */
  819. __le64 cmd_cons_dma_addr; /* */
  820. __le64 dummy_dma_addr; /* */
  821. __le32 capabilities[4]; /* Flag bit vector */
  822. __le32 host_int_crb_mode; /* Interrupt crb usage */
  823. __le32 rsvd1; /* Padding */
  824. __le16 rsvd2; /* Padding */
  825. __le16 interrupt_ctl;
  826. __le16 msi_index;
  827. __le16 rsvd3; /* Padding */
  828. nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
  829. u8 reserved[128]; /* future expansion */
  830. } nx_hostrq_tx_ctx_t;
  831. typedef struct {
  832. __le32 host_producer_crb; /* Crb to use */
  833. __le32 interrupt_crb; /* Crb to use */
  834. } nx_cardrsp_cds_ring_t;
  835. typedef struct {
  836. __le32 host_ctx_state; /* Starting state */
  837. __le16 context_id; /* Handle for context */
  838. u8 phys_port; /* Physical id of port */
  839. u8 virt_port; /* Virtual/Logical id of port */
  840. nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
  841. u8 reserved[128]; /* future expansion */
  842. } nx_cardrsp_tx_ctx_t;
  843. #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
  844. #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
  845. /* CRB */
  846. #define NX_HOST_RDS_CRB_MODE_UNIQUE 0
  847. #define NX_HOST_RDS_CRB_MODE_SHARED 1
  848. #define NX_HOST_RDS_CRB_MODE_CUSTOM 2
  849. #define NX_HOST_RDS_CRB_MODE_MAX 3
  850. #define NX_HOST_INT_CRB_MODE_UNIQUE 0
  851. #define NX_HOST_INT_CRB_MODE_SHARED 1
  852. #define NX_HOST_INT_CRB_MODE_NORX 2
  853. #define NX_HOST_INT_CRB_MODE_NOTX 3
  854. #define NX_HOST_INT_CRB_MODE_NORXTX 4
  855. /* MAC */
  856. #define MC_COUNT_P2 16
  857. #define MC_COUNT_P3 38
  858. #define NETXEN_MAC_NOOP 0
  859. #define NETXEN_MAC_ADD 1
  860. #define NETXEN_MAC_DEL 2
  861. typedef struct nx_mac_list_s {
  862. struct list_head list;
  863. uint8_t mac_addr[ETH_ALEN+2];
  864. } nx_mac_list_t;
  865. /*
  866. * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
  867. * adjusted based on configured MTU.
  868. */
  869. #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
  870. #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
  871. #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
  872. #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
  873. #define NETXEN_NIC_INTR_DEFAULT 0x04
  874. typedef union {
  875. struct {
  876. uint16_t rx_packets;
  877. uint16_t rx_time_us;
  878. uint16_t tx_packets;
  879. uint16_t tx_time_us;
  880. } data;
  881. uint64_t word;
  882. } nx_nic_intr_coalesce_data_t;
  883. typedef struct {
  884. uint16_t stats_time_us;
  885. uint16_t rate_sample_time;
  886. uint16_t flags;
  887. uint16_t rsvd_1;
  888. uint32_t low_threshold;
  889. uint32_t high_threshold;
  890. nx_nic_intr_coalesce_data_t normal;
  891. nx_nic_intr_coalesce_data_t low;
  892. nx_nic_intr_coalesce_data_t high;
  893. nx_nic_intr_coalesce_data_t irq;
  894. } nx_nic_intr_coalesce_t;
  895. #define NX_HOST_REQUEST 0x13
  896. #define NX_NIC_REQUEST 0x14
  897. #define NX_MAC_EVENT 0x1
  898. /*
  899. * Driver --> Firmware
  900. */
  901. #define NX_NIC_H2C_OPCODE_START 0
  902. #define NX_NIC_H2C_OPCODE_CONFIG_RSS 1
  903. #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2
  904. #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
  905. #define NX_NIC_H2C_OPCODE_CONFIG_LED 4
  906. #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
  907. #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6
  908. #define NX_NIC_H2C_OPCODE_LRO_REQUEST 7
  909. #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8
  910. #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9
  911. #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
  912. #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11
  913. #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
  914. #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
  915. #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
  916. #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
  917. #define NX_NIC_H2C_OPCODE_GET_NET_STATS 16
  918. #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
  919. #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18
  920. #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19
  921. #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20
  922. #define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21
  923. #define NX_NIC_C2C_OPCODE 22
  924. #define NX_NIC_H2C_OPCODE_LAST 23
  925. /*
  926. * Firmware --> Driver
  927. */
  928. #define NX_NIC_C2H_OPCODE_START 128
  929. #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
  930. #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
  931. #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
  932. #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
  933. #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
  934. #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
  935. #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
  936. #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136
  937. #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
  938. #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
  939. #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
  940. #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
  941. #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
  942. #define NX_NIC_C2H_OPCODE_LAST 142
  943. #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
  944. #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
  945. #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
  946. #define NX_FW_CAPABILITY_LINK_NOTIFICATION (1 << 5)
  947. #define NX_FW_CAPABILITY_SWITCHING (1 << 6)
  948. /* module types */
  949. #define LINKEVENT_MODULE_NOT_PRESENT 1
  950. #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
  951. #define LINKEVENT_MODULE_OPTICAL_SRLR 3
  952. #define LINKEVENT_MODULE_OPTICAL_LRM 4
  953. #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
  954. #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
  955. #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
  956. #define LINKEVENT_MODULE_TWINAX 8
  957. #define LINKSPEED_10GBPS 10000
  958. #define LINKSPEED_1GBPS 1000
  959. #define LINKSPEED_100MBPS 100
  960. #define LINKSPEED_10MBPS 10
  961. #define LINKSPEED_ENCODED_10MBPS 0
  962. #define LINKSPEED_ENCODED_100MBPS 1
  963. #define LINKSPEED_ENCODED_1GBPS 2
  964. #define LINKEVENT_AUTONEG_DISABLED 0
  965. #define LINKEVENT_AUTONEG_ENABLED 1
  966. #define LINKEVENT_HALF_DUPLEX 0
  967. #define LINKEVENT_FULL_DUPLEX 1
  968. #define LINKEVENT_LINKSPEED_MBPS 0
  969. #define LINKEVENT_LINKSPEED_ENCODED 1
  970. /* firmware response header:
  971. * 63:58 - message type
  972. * 57:56 - owner
  973. * 55:53 - desc count
  974. * 52:48 - reserved
  975. * 47:40 - completion id
  976. * 39:32 - opcode
  977. * 31:16 - error code
  978. * 15:00 - reserved
  979. */
  980. #define netxen_get_nic_msgtype(msg_hdr) \
  981. ((msg_hdr >> 58) & 0x3F)
  982. #define netxen_get_nic_msg_compid(msg_hdr) \
  983. ((msg_hdr >> 40) & 0xFF)
  984. #define netxen_get_nic_msg_opcode(msg_hdr) \
  985. ((msg_hdr >> 32) & 0xFF)
  986. #define netxen_get_nic_msg_errcode(msg_hdr) \
  987. ((msg_hdr >> 16) & 0xFFFF)
  988. typedef struct {
  989. union {
  990. struct {
  991. u64 hdr;
  992. u64 body[7];
  993. };
  994. u64 words[8];
  995. };
  996. } nx_fw_msg_t;
  997. typedef struct {
  998. __le64 qhdr;
  999. __le64 req_hdr;
  1000. __le64 words[6];
  1001. } nx_nic_req_t;
  1002. typedef struct {
  1003. u8 op;
  1004. u8 tag;
  1005. u8 mac_addr[6];
  1006. } nx_mac_req_t;
  1007. #define MAX_PENDING_DESC_BLOCK_SIZE 64
  1008. #define NETXEN_NIC_MSI_ENABLED 0x02
  1009. #define NETXEN_NIC_MSIX_ENABLED 0x04
  1010. #define NETXEN_IS_MSI_FAMILY(adapter) \
  1011. ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
  1012. #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
  1013. #define NETXEN_MSIX_TBL_SPACE 8192
  1014. #define NETXEN_PCI_REG_MSIX_TBL 0x44
  1015. #define NETXEN_DB_MAPSIZE_BYTES 0x1000
  1016. #define NETXEN_NETDEV_WEIGHT 128
  1017. #define NETXEN_ADAPTER_UP_MAGIC 777
  1018. #define NETXEN_NIC_PEG_TUNE 0
  1019. struct netxen_dummy_dma {
  1020. void *addr;
  1021. dma_addr_t phys_addr;
  1022. };
  1023. struct netxen_adapter {
  1024. struct netxen_hardware_context ahw;
  1025. struct net_device *netdev;
  1026. struct pci_dev *pdev;
  1027. struct list_head mac_list;
  1028. u32 curr_window;
  1029. u32 crb_win;
  1030. rwlock_t adapter_lock;
  1031. spinlock_t tx_clean_lock;
  1032. u16 num_txd;
  1033. u16 num_rxd;
  1034. u16 num_jumbo_rxd;
  1035. u16 num_lro_rxd;
  1036. u8 max_rds_rings;
  1037. u8 max_sds_rings;
  1038. u8 driver_mismatch;
  1039. u8 msix_supported;
  1040. u8 rx_csum;
  1041. u8 pci_using_dac;
  1042. u8 portnum;
  1043. u8 physical_port;
  1044. u8 mc_enabled;
  1045. u8 max_mc_count;
  1046. u8 rss_supported;
  1047. u8 resv2;
  1048. u32 resv3;
  1049. u8 has_link_events;
  1050. u8 resv1;
  1051. u16 tx_context_id;
  1052. u16 mtu;
  1053. u16 is_up;
  1054. u16 link_speed;
  1055. u16 link_duplex;
  1056. u16 link_autoneg;
  1057. u16 module_type;
  1058. u32 capabilities;
  1059. u32 flags;
  1060. u32 irq;
  1061. u32 temp;
  1062. u32 msi_tgt_status;
  1063. u32 resv4;
  1064. struct netxen_adapter_stats stats;
  1065. struct netxen_recv_context recv_ctx;
  1066. struct nx_host_tx_ring *tx_ring;
  1067. int (*enable_phy_interrupts) (struct netxen_adapter *);
  1068. int (*disable_phy_interrupts) (struct netxen_adapter *);
  1069. int (*macaddr_set) (struct netxen_adapter *, u8 *);
  1070. int (*set_mtu) (struct netxen_adapter *, int);
  1071. int (*set_promisc) (struct netxen_adapter *, u32);
  1072. void (*set_multi) (struct net_device *);
  1073. int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
  1074. int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
  1075. int (*init_port) (struct netxen_adapter *, int);
  1076. int (*stop_port) (struct netxen_adapter *);
  1077. u32 (*hw_read_wx)(struct netxen_adapter *, ulong);
  1078. int (*hw_write_wx)(struct netxen_adapter *, ulong, u32);
  1079. int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
  1080. int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
  1081. int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
  1082. u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
  1083. unsigned long (*pci_set_window)(struct netxen_adapter *,
  1084. unsigned long long);
  1085. struct netxen_legacy_intr_set legacy_intr;
  1086. struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
  1087. struct netxen_dummy_dma dummy_dma;
  1088. struct work_struct watchdog_task;
  1089. struct timer_list watchdog_timer;
  1090. struct work_struct tx_timeout_task;
  1091. struct net_device_stats net_stats;
  1092. nx_nic_intr_coalesce_t coal;
  1093. u32 fw_major;
  1094. u32 fw_version;
  1095. const struct firmware *fw;
  1096. };
  1097. /*
  1098. * NetXen dma watchdog control structure
  1099. *
  1100. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  1101. * Bit 1 : disable_request => 1 req disable dma watchdog
  1102. * Bit 2 : enable_request => 1 req enable dma watchdog
  1103. * Bit 3-31 : unused
  1104. */
  1105. #define netxen_set_dma_watchdog_disable_req(config_word) \
  1106. _netxen_set_bits(config_word, 1, 1, 1)
  1107. #define netxen_set_dma_watchdog_enable_req(config_word) \
  1108. _netxen_set_bits(config_word, 2, 1, 1)
  1109. #define netxen_get_dma_watchdog_enabled(config_word) \
  1110. ((config_word) & 0x1)
  1111. #define netxen_get_dma_watchdog_disabled(config_word) \
  1112. (((config_word) >> 1) & 0x1)
  1113. int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
  1114. int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
  1115. int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
  1116. int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
  1117. int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
  1118. __u32 * readval);
  1119. int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
  1120. long reg, __u32 val);
  1121. /* Functions available from netxen_nic_hw.c */
  1122. int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
  1123. int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
  1124. int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
  1125. int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
  1126. #define NXRD32(adapter, off) \
  1127. (adapter->hw_read_wx(adapter, off))
  1128. #define NXWR32(adapter, off, val) \
  1129. (adapter->hw_write_wx(adapter, off, val))
  1130. int netxen_nic_get_board_info(struct netxen_adapter *adapter);
  1131. void netxen_nic_get_firmware_info(struct netxen_adapter *adapter);
  1132. int netxen_nic_wol_supported(struct netxen_adapter *adapter);
  1133. u32 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off);
  1134. int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
  1135. ulong off, u32 data);
  1136. int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
  1137. u64 off, void *data, int size);
  1138. int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
  1139. u64 off, void *data, int size);
  1140. int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
  1141. u64 off, u32 data);
  1142. u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
  1143. void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
  1144. u64 off, u32 data);
  1145. u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
  1146. unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
  1147. unsigned long long addr);
  1148. void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
  1149. u32 wndw);
  1150. u32 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off);
  1151. int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
  1152. ulong off, u32 data);
  1153. int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
  1154. u64 off, void *data, int size);
  1155. int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
  1156. u64 off, void *data, int size);
  1157. int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
  1158. u64 off, u32 data);
  1159. u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
  1160. void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
  1161. u64 off, u32 data);
  1162. u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
  1163. unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
  1164. unsigned long long addr);
  1165. /* Functions from netxen_nic_init.c */
  1166. void netxen_free_adapter_offload(struct netxen_adapter *adapter);
  1167. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
  1168. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
  1169. int netxen_load_firmware(struct netxen_adapter *adapter);
  1170. void netxen_request_firmware(struct netxen_adapter *adapter);
  1171. void netxen_release_firmware(struct netxen_adapter *adapter);
  1172. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
  1173. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
  1174. int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  1175. u8 *bytes, size_t size);
  1176. int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
  1177. u8 *bytes, size_t size);
  1178. int netxen_flash_unlock(struct netxen_adapter *adapter);
  1179. int netxen_backup_crbinit(struct netxen_adapter *adapter);
  1180. int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
  1181. int netxen_flash_erase_primary(struct netxen_adapter *adapter);
  1182. void netxen_halt_pegs(struct netxen_adapter *adapter);
  1183. int netxen_rom_se(struct netxen_adapter *adapter, int addr);
  1184. int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
  1185. void netxen_free_sw_resources(struct netxen_adapter *adapter);
  1186. int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
  1187. void netxen_free_hw_resources(struct netxen_adapter *adapter);
  1188. void netxen_release_rx_buffers(struct netxen_adapter *adapter);
  1189. void netxen_release_tx_buffers(struct netxen_adapter *adapter);
  1190. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
  1191. int netxen_init_firmware(struct netxen_adapter *adapter);
  1192. void netxen_nic_clear_stats(struct netxen_adapter *adapter);
  1193. void netxen_watchdog_task(struct work_struct *work);
  1194. void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1195. struct nx_host_rds_ring *rds_ring);
  1196. int netxen_process_cmd_ring(struct netxen_adapter *adapter);
  1197. int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
  1198. void netxen_p2_nic_set_multi(struct net_device *netdev);
  1199. void netxen_p3_nic_set_multi(struct net_device *netdev);
  1200. void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
  1201. int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
  1202. int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
  1203. int netxen_config_rss(struct netxen_adapter *adapter, int enable);
  1204. int netxen_linkevent_request(struct netxen_adapter *adapter, int enable);
  1205. void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup);
  1206. int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
  1207. int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
  1208. int netxen_nic_set_mac(struct net_device *netdev, void *p);
  1209. struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
  1210. void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
  1211. struct nx_host_tx_ring *tx_ring);
  1212. /*
  1213. * NetXen Board information
  1214. */
  1215. #define NETXEN_MAX_SHORT_NAME 32
  1216. struct netxen_brdinfo {
  1217. int brdtype; /* type of board */
  1218. long ports; /* max no of physical ports */
  1219. char short_name[NETXEN_MAX_SHORT_NAME];
  1220. };
  1221. static const struct netxen_brdinfo netxen_boards[] = {
  1222. {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
  1223. {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
  1224. {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
  1225. {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
  1226. {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
  1227. {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
  1228. {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
  1229. {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
  1230. {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
  1231. {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
  1232. {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
  1233. {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
  1234. {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
  1235. {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
  1236. {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
  1237. {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
  1238. {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
  1239. {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
  1240. {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
  1241. };
  1242. #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
  1243. static inline void get_brd_name_by_type(u32 type, char *name)
  1244. {
  1245. int i, found = 0;
  1246. for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
  1247. if (netxen_boards[i].brdtype == type) {
  1248. strcpy(name, netxen_boards[i].short_name);
  1249. found = 1;
  1250. break;
  1251. }
  1252. }
  1253. if (!found)
  1254. name = "Unknown";
  1255. }
  1256. static inline int
  1257. dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
  1258. {
  1259. u32 ctrl;
  1260. /* check if already inactive */
  1261. ctrl = adapter->hw_read_wx(adapter,
  1262. NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL));
  1263. if (netxen_get_dma_watchdog_enabled(ctrl) == 0)
  1264. return 1;
  1265. /* Send the disable request */
  1266. netxen_set_dma_watchdog_disable_req(ctrl);
  1267. NXWR32(adapter, NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
  1268. return 0;
  1269. }
  1270. static inline int
  1271. dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
  1272. {
  1273. u32 ctrl;
  1274. ctrl = adapter->hw_read_wx(adapter,
  1275. NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL));
  1276. return (netxen_get_dma_watchdog_enabled(ctrl) == 0);
  1277. }
  1278. static inline int
  1279. dma_watchdog_wakeup(struct netxen_adapter *adapter)
  1280. {
  1281. u32 ctrl;
  1282. ctrl = adapter->hw_read_wx(adapter,
  1283. NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL));
  1284. if (netxen_get_dma_watchdog_enabled(ctrl))
  1285. return 1;
  1286. /* send the wakeup request */
  1287. netxen_set_dma_watchdog_enable_req(ctrl);
  1288. NXWR32(adapter, NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
  1289. return 0;
  1290. }
  1291. static inline u32 netxen_tx_avail(struct nx_host_tx_ring *tx_ring)
  1292. {
  1293. smp_mb();
  1294. return find_diff_among(tx_ring->producer,
  1295. tx_ring->sw_consumer, tx_ring->num_desc);
  1296. }
  1297. int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
  1298. int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
  1299. extern void netxen_change_ringparam(struct netxen_adapter *adapter);
  1300. extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
  1301. int *valp);
  1302. extern struct ethtool_ops netxen_nic_ethtool_ops;
  1303. #endif /* __NETXEN_NIC_H_ */