nouveau_fence.c 15 KB

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  1. /*
  2. * Copyright (C) 2007 Ben Skeggs.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the
  14. * next paragraph) shall be included in all copies or substantial
  15. * portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20. * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21. * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22. * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23. * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24. *
  25. */
  26. #include "drmP.h"
  27. #include "drm.h"
  28. #include "nouveau_drv.h"
  29. #include "nouveau_ramht.h"
  30. #include "nouveau_dma.h"
  31. #define USE_REFCNT(dev) (nouveau_private(dev)->chipset >= 0x10)
  32. #define USE_SEMA(dev) (nouveau_private(dev)->chipset >= 0x17)
  33. struct nouveau_fence {
  34. struct nouveau_channel *channel;
  35. struct kref refcount;
  36. struct list_head entry;
  37. uint32_t sequence;
  38. bool signalled;
  39. void (*work)(void *priv, bool signalled);
  40. void *priv;
  41. };
  42. struct nouveau_semaphore {
  43. struct kref ref;
  44. struct drm_device *dev;
  45. struct drm_mm_node *mem;
  46. };
  47. static inline struct nouveau_fence *
  48. nouveau_fence(void *sync_obj)
  49. {
  50. return (struct nouveau_fence *)sync_obj;
  51. }
  52. static void
  53. nouveau_fence_del(struct kref *ref)
  54. {
  55. struct nouveau_fence *fence =
  56. container_of(ref, struct nouveau_fence, refcount);
  57. nouveau_channel_ref(NULL, &fence->channel);
  58. kfree(fence);
  59. }
  60. void
  61. nouveau_fence_update(struct nouveau_channel *chan)
  62. {
  63. struct drm_device *dev = chan->dev;
  64. struct nouveau_fence *tmp, *fence;
  65. uint32_t sequence;
  66. spin_lock(&chan->fence.lock);
  67. /* Fetch the last sequence if the channel is still up and running */
  68. if (likely(!list_empty(&chan->fence.pending))) {
  69. if (USE_REFCNT(dev))
  70. sequence = nvchan_rd32(chan, 0x48);
  71. else
  72. sequence = atomic_read(&chan->fence.last_sequence_irq);
  73. if (chan->fence.sequence_ack == sequence)
  74. goto out;
  75. chan->fence.sequence_ack = sequence;
  76. }
  77. list_for_each_entry_safe(fence, tmp, &chan->fence.pending, entry) {
  78. sequence = fence->sequence;
  79. fence->signalled = true;
  80. list_del(&fence->entry);
  81. if (unlikely(fence->work))
  82. fence->work(fence->priv, true);
  83. kref_put(&fence->refcount, nouveau_fence_del);
  84. if (sequence == chan->fence.sequence_ack)
  85. break;
  86. }
  87. out:
  88. spin_unlock(&chan->fence.lock);
  89. }
  90. int
  91. nouveau_fence_new(struct nouveau_channel *chan, struct nouveau_fence **pfence,
  92. bool emit)
  93. {
  94. struct nouveau_fence *fence;
  95. int ret = 0;
  96. fence = kzalloc(sizeof(*fence), GFP_KERNEL);
  97. if (!fence)
  98. return -ENOMEM;
  99. kref_init(&fence->refcount);
  100. nouveau_channel_ref(chan, &fence->channel);
  101. if (emit)
  102. ret = nouveau_fence_emit(fence);
  103. if (ret)
  104. nouveau_fence_unref(&fence);
  105. *pfence = fence;
  106. return ret;
  107. }
  108. struct nouveau_channel *
  109. nouveau_fence_channel(struct nouveau_fence *fence)
  110. {
  111. return fence ? nouveau_channel_get_unlocked(fence->channel) : NULL;
  112. }
  113. int
  114. nouveau_fence_emit(struct nouveau_fence *fence)
  115. {
  116. struct nouveau_channel *chan = fence->channel;
  117. struct drm_device *dev = chan->dev;
  118. struct drm_nouveau_private *dev_priv = dev->dev_private;
  119. int ret;
  120. ret = RING_SPACE(chan, 2);
  121. if (ret)
  122. return ret;
  123. if (unlikely(chan->fence.sequence == chan->fence.sequence_ack - 1)) {
  124. nouveau_fence_update(chan);
  125. BUG_ON(chan->fence.sequence ==
  126. chan->fence.sequence_ack - 1);
  127. }
  128. fence->sequence = ++chan->fence.sequence;
  129. kref_get(&fence->refcount);
  130. spin_lock(&chan->fence.lock);
  131. list_add_tail(&fence->entry, &chan->fence.pending);
  132. spin_unlock(&chan->fence.lock);
  133. if (USE_REFCNT(dev)) {
  134. if (dev_priv->card_type < NV_C0)
  135. BEGIN_RING(chan, NvSubSw, 0x0050, 1);
  136. else
  137. BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0050, 1);
  138. } else {
  139. BEGIN_RING(chan, NvSubSw, 0x0150, 1);
  140. }
  141. OUT_RING (chan, fence->sequence);
  142. FIRE_RING(chan);
  143. return 0;
  144. }
  145. void
  146. nouveau_fence_work(struct nouveau_fence *fence,
  147. void (*work)(void *priv, bool signalled),
  148. void *priv)
  149. {
  150. BUG_ON(fence->work);
  151. spin_lock(&fence->channel->fence.lock);
  152. if (fence->signalled) {
  153. work(priv, true);
  154. } else {
  155. fence->work = work;
  156. fence->priv = priv;
  157. }
  158. spin_unlock(&fence->channel->fence.lock);
  159. }
  160. void
  161. __nouveau_fence_unref(void **sync_obj)
  162. {
  163. struct nouveau_fence *fence = nouveau_fence(*sync_obj);
  164. if (fence)
  165. kref_put(&fence->refcount, nouveau_fence_del);
  166. *sync_obj = NULL;
  167. }
  168. void *
  169. __nouveau_fence_ref(void *sync_obj)
  170. {
  171. struct nouveau_fence *fence = nouveau_fence(sync_obj);
  172. kref_get(&fence->refcount);
  173. return sync_obj;
  174. }
  175. bool
  176. __nouveau_fence_signalled(void *sync_obj, void *sync_arg)
  177. {
  178. struct nouveau_fence *fence = nouveau_fence(sync_obj);
  179. struct nouveau_channel *chan = fence->channel;
  180. if (fence->signalled)
  181. return true;
  182. nouveau_fence_update(chan);
  183. return fence->signalled;
  184. }
  185. int
  186. __nouveau_fence_wait(void *sync_obj, void *sync_arg, bool lazy, bool intr)
  187. {
  188. unsigned long timeout = jiffies + (3 * DRM_HZ);
  189. unsigned long sleep_time = jiffies + 1;
  190. int ret = 0;
  191. while (1) {
  192. if (__nouveau_fence_signalled(sync_obj, sync_arg))
  193. break;
  194. if (time_after_eq(jiffies, timeout)) {
  195. ret = -EBUSY;
  196. break;
  197. }
  198. __set_current_state(intr ? TASK_INTERRUPTIBLE
  199. : TASK_UNINTERRUPTIBLE);
  200. if (lazy && time_after_eq(jiffies, sleep_time))
  201. schedule_timeout(1);
  202. if (intr && signal_pending(current)) {
  203. ret = -ERESTARTSYS;
  204. break;
  205. }
  206. }
  207. __set_current_state(TASK_RUNNING);
  208. return ret;
  209. }
  210. static struct nouveau_semaphore *
  211. semaphore_alloc(struct drm_device *dev)
  212. {
  213. struct drm_nouveau_private *dev_priv = dev->dev_private;
  214. struct nouveau_semaphore *sema;
  215. int size = (dev_priv->chipset < 0x84) ? 4 : 16;
  216. int ret, i;
  217. if (!USE_SEMA(dev))
  218. return NULL;
  219. sema = kmalloc(sizeof(*sema), GFP_KERNEL);
  220. if (!sema)
  221. goto fail;
  222. ret = drm_mm_pre_get(&dev_priv->fence.heap);
  223. if (ret)
  224. goto fail;
  225. spin_lock(&dev_priv->fence.lock);
  226. sema->mem = drm_mm_search_free(&dev_priv->fence.heap, size, 0, 0);
  227. if (sema->mem)
  228. sema->mem = drm_mm_get_block_atomic(sema->mem, size, 0);
  229. spin_unlock(&dev_priv->fence.lock);
  230. if (!sema->mem)
  231. goto fail;
  232. kref_init(&sema->ref);
  233. sema->dev = dev;
  234. for (i = sema->mem->start; i < sema->mem->start + size; i += 4)
  235. nouveau_bo_wr32(dev_priv->fence.bo, i / 4, 0);
  236. return sema;
  237. fail:
  238. kfree(sema);
  239. return NULL;
  240. }
  241. static void
  242. semaphore_free(struct kref *ref)
  243. {
  244. struct nouveau_semaphore *sema =
  245. container_of(ref, struct nouveau_semaphore, ref);
  246. struct drm_nouveau_private *dev_priv = sema->dev->dev_private;
  247. spin_lock(&dev_priv->fence.lock);
  248. drm_mm_put_block(sema->mem);
  249. spin_unlock(&dev_priv->fence.lock);
  250. kfree(sema);
  251. }
  252. static void
  253. semaphore_work(void *priv, bool signalled)
  254. {
  255. struct nouveau_semaphore *sema = priv;
  256. struct drm_nouveau_private *dev_priv = sema->dev->dev_private;
  257. if (unlikely(!signalled))
  258. nouveau_bo_wr32(dev_priv->fence.bo, sema->mem->start / 4, 1);
  259. kref_put(&sema->ref, semaphore_free);
  260. }
  261. static int
  262. semaphore_acquire(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
  263. {
  264. struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
  265. struct nouveau_fence *fence = NULL;
  266. int ret;
  267. if (dev_priv->chipset < 0x84) {
  268. ret = RING_SPACE(chan, 3);
  269. if (ret)
  270. return ret;
  271. BEGIN_RING(chan, NvSubSw, NV_SW_SEMAPHORE_OFFSET, 2);
  272. OUT_RING (chan, sema->mem->start);
  273. OUT_RING (chan, 1);
  274. } else
  275. if (dev_priv->chipset < 0xc0) {
  276. /*
  277. * NV50 tries to be too smart and context-switch
  278. * between semaphores instead of doing a "first come,
  279. * first served" strategy like previous cards
  280. * do.
  281. *
  282. * That's bad because the ACQUIRE latency can get as
  283. * large as the PFIFO context time slice in the
  284. * typical DRI2 case where you have several
  285. * outstanding semaphores at the same moment.
  286. *
  287. * If we're going to ACQUIRE, force the card to
  288. * context switch before, just in case the matching
  289. * RELEASE is already scheduled to be executed in
  290. * another channel.
  291. */
  292. ret = RING_SPACE(chan, 7);
  293. if (ret)
  294. return ret;
  295. BEGIN_RING(chan, NvSubSw, 0x0080, 1);
  296. OUT_RING (chan, 0);
  297. BEGIN_RING(chan, NvSubSw, 0x0010, 4);
  298. OUT_RING (chan, upper_32_bits(sema->mem->start));
  299. OUT_RING (chan, lower_32_bits(sema->mem->start));
  300. OUT_RING (chan, 1);
  301. OUT_RING (chan, 1); /* ACQUIRE_EQ */
  302. } else {
  303. struct nouveau_vma *vma = &dev_priv->fence.bo->vma;
  304. u64 offset = vma->offset + sema->mem->start;
  305. ret = RING_SPACE(chan, 5);
  306. if (ret)
  307. return ret;
  308. BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
  309. OUT_RING (chan, upper_32_bits(offset));
  310. OUT_RING (chan, lower_32_bits(offset));
  311. OUT_RING (chan, 1);
  312. OUT_RING (chan, 0x1001); /* ACQUIRE_EQ */
  313. }
  314. /* Delay semaphore destruction until its work is done */
  315. ret = nouveau_fence_new(chan, &fence, true);
  316. if (ret)
  317. return ret;
  318. kref_get(&sema->ref);
  319. nouveau_fence_work(fence, semaphore_work, sema);
  320. nouveau_fence_unref(&fence);
  321. return 0;
  322. }
  323. static int
  324. semaphore_release(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
  325. {
  326. struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
  327. struct nouveau_fence *fence = NULL;
  328. int ret;
  329. if (dev_priv->chipset < 0x84) {
  330. ret = RING_SPACE(chan, 4);
  331. if (ret)
  332. return ret;
  333. BEGIN_RING(chan, NvSubSw, NV_SW_SEMAPHORE_OFFSET, 1);
  334. OUT_RING (chan, sema->mem->start);
  335. BEGIN_RING(chan, NvSubSw, NV_SW_SEMAPHORE_RELEASE, 1);
  336. OUT_RING (chan, 1);
  337. } else
  338. if (dev_priv->chipset < 0xc0) {
  339. /*
  340. * Emits release and forces the card to context switch right
  341. * afterwards, there may be another channel waiting for the
  342. * semaphore
  343. */
  344. ret = RING_SPACE(chan, 7);
  345. if (ret)
  346. return ret;
  347. BEGIN_RING(chan, NvSubSw, 0x0010, 4);
  348. OUT_RING (chan, upper_32_bits(sema->mem->start));
  349. OUT_RING (chan, lower_32_bits(sema->mem->start));
  350. OUT_RING (chan, 1);
  351. OUT_RING (chan, 2); /* RELEASE */
  352. BEGIN_RING(chan, NvSubSw, 0x0080, 1);
  353. OUT_RING (chan, 0);
  354. } else {
  355. struct nouveau_vma *vma = &dev_priv->fence.bo->vma;
  356. u64 offset = vma->offset + sema->mem->start;
  357. ret = RING_SPACE(chan, 5);
  358. if (ret)
  359. return ret;
  360. BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
  361. OUT_RING (chan, upper_32_bits(offset));
  362. OUT_RING (chan, lower_32_bits(offset));
  363. OUT_RING (chan, 1);
  364. OUT_RING (chan, 0x1002); /* RELEASE */
  365. }
  366. /* Delay semaphore destruction until its work is done */
  367. ret = nouveau_fence_new(chan, &fence, true);
  368. if (ret)
  369. return ret;
  370. kref_get(&sema->ref);
  371. nouveau_fence_work(fence, semaphore_work, sema);
  372. nouveau_fence_unref(&fence);
  373. return 0;
  374. }
  375. int
  376. nouveau_fence_sync(struct nouveau_fence *fence,
  377. struct nouveau_channel *wchan)
  378. {
  379. struct nouveau_channel *chan = nouveau_fence_channel(fence);
  380. struct drm_device *dev = wchan->dev;
  381. struct nouveau_semaphore *sema;
  382. int ret = 0;
  383. if (likely(!chan || chan == wchan ||
  384. nouveau_fence_signalled(fence)))
  385. goto out;
  386. sema = semaphore_alloc(dev);
  387. if (!sema) {
  388. /* Early card or broken userspace, fall back to
  389. * software sync. */
  390. ret = nouveau_fence_wait(fence, true, false);
  391. goto out;
  392. }
  393. /* try to take chan's mutex, if we can't take it right away
  394. * we have to fallback to software sync to prevent locking
  395. * order issues
  396. */
  397. if (!mutex_trylock(&chan->mutex)) {
  398. ret = nouveau_fence_wait(fence, true, false);
  399. goto out_unref;
  400. }
  401. /* Make wchan wait until it gets signalled */
  402. ret = semaphore_acquire(wchan, sema);
  403. if (ret)
  404. goto out_unlock;
  405. /* Signal the semaphore from chan */
  406. ret = semaphore_release(chan, sema);
  407. out_unlock:
  408. mutex_unlock(&chan->mutex);
  409. out_unref:
  410. kref_put(&sema->ref, semaphore_free);
  411. out:
  412. if (chan)
  413. nouveau_channel_put_unlocked(&chan);
  414. return ret;
  415. }
  416. int
  417. __nouveau_fence_flush(void *sync_obj, void *sync_arg)
  418. {
  419. return 0;
  420. }
  421. int
  422. nouveau_fence_channel_init(struct nouveau_channel *chan)
  423. {
  424. struct drm_device *dev = chan->dev;
  425. struct drm_nouveau_private *dev_priv = dev->dev_private;
  426. struct nouveau_gpuobj *obj = NULL;
  427. int ret;
  428. if (dev_priv->card_type >= NV_C0)
  429. goto out_initialised;
  430. /* Create an NV_SW object for various sync purposes */
  431. ret = nouveau_gpuobj_gr_new(chan, NvSw, NV_SW);
  432. if (ret)
  433. return ret;
  434. /* we leave subchannel empty for nvc0 */
  435. ret = RING_SPACE(chan, 2);
  436. if (ret)
  437. return ret;
  438. BEGIN_RING(chan, NvSubSw, 0, 1);
  439. OUT_RING(chan, NvSw);
  440. /* Create a DMA object for the shared cross-channel sync area. */
  441. if (USE_SEMA(dev)) {
  442. struct ttm_mem_reg *mem = &dev_priv->fence.bo->bo.mem;
  443. ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
  444. mem->start << PAGE_SHIFT,
  445. mem->size, NV_MEM_ACCESS_RW,
  446. NV_MEM_TARGET_VRAM, &obj);
  447. if (ret)
  448. return ret;
  449. ret = nouveau_ramht_insert(chan, NvSema, obj);
  450. nouveau_gpuobj_ref(NULL, &obj);
  451. if (ret)
  452. return ret;
  453. ret = RING_SPACE(chan, 2);
  454. if (ret)
  455. return ret;
  456. BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1);
  457. OUT_RING(chan, NvSema);
  458. }
  459. FIRE_RING(chan);
  460. out_initialised:
  461. INIT_LIST_HEAD(&chan->fence.pending);
  462. spin_lock_init(&chan->fence.lock);
  463. atomic_set(&chan->fence.last_sequence_irq, 0);
  464. return 0;
  465. }
  466. void
  467. nouveau_fence_channel_fini(struct nouveau_channel *chan)
  468. {
  469. struct nouveau_fence *tmp, *fence;
  470. spin_lock(&chan->fence.lock);
  471. list_for_each_entry_safe(fence, tmp, &chan->fence.pending, entry) {
  472. fence->signalled = true;
  473. list_del(&fence->entry);
  474. if (unlikely(fence->work))
  475. fence->work(fence->priv, false);
  476. kref_put(&fence->refcount, nouveau_fence_del);
  477. }
  478. spin_unlock(&chan->fence.lock);
  479. }
  480. int
  481. nouveau_fence_init(struct drm_device *dev)
  482. {
  483. struct drm_nouveau_private *dev_priv = dev->dev_private;
  484. int size = (dev_priv->chipset < 0x84) ? 4096 : 16384;
  485. int ret;
  486. /* Create a shared VRAM heap for cross-channel sync. */
  487. if (USE_SEMA(dev)) {
  488. ret = nouveau_bo_new(dev, NULL, size, 0, TTM_PL_FLAG_VRAM,
  489. 0, 0, false, true, &dev_priv->fence.bo);
  490. if (ret)
  491. return ret;
  492. ret = nouveau_bo_pin(dev_priv->fence.bo, TTM_PL_FLAG_VRAM);
  493. if (ret)
  494. goto fail;
  495. ret = nouveau_bo_map(dev_priv->fence.bo);
  496. if (ret)
  497. goto fail;
  498. ret = drm_mm_init(&dev_priv->fence.heap, 0,
  499. dev_priv->fence.bo->bo.mem.size);
  500. if (ret)
  501. goto fail;
  502. spin_lock_init(&dev_priv->fence.lock);
  503. }
  504. return 0;
  505. fail:
  506. nouveau_bo_unmap(dev_priv->fence.bo);
  507. nouveau_bo_ref(NULL, &dev_priv->fence.bo);
  508. return ret;
  509. }
  510. void
  511. nouveau_fence_fini(struct drm_device *dev)
  512. {
  513. struct drm_nouveau_private *dev_priv = dev->dev_private;
  514. if (USE_SEMA(dev)) {
  515. drm_mm_takedown(&dev_priv->fence.heap);
  516. nouveau_bo_unmap(dev_priv->fence.bo);
  517. nouveau_bo_unpin(dev_priv->fence.bo);
  518. nouveau_bo_ref(NULL, &dev_priv->fence.bo);
  519. }
  520. }