dl2k.c 50 KB

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  1. /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
  2. /*
  3. Copyright (c) 2001, 2002 by D-Link Corporation
  4. Written by Edward Peng.<edward_peng@dlink.com.tw>
  5. Created 03-May-2001, base on Linux' sundance.c.
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; either version 2 of the License, or
  9. (at your option) any later version.
  10. */
  11. /*
  12. Rev Date Description
  13. ==========================================================================
  14. 0.01 2001/05/03 Created DL2000-based linux driver
  15. 0.02 2001/05/21 Added VLAN and hardware checksum support.
  16. 1.00 2001/06/26 Added jumbo frame support.
  17. 1.01 2001/08/21 Added two parameters, rx_coalesce and rx_timeout.
  18. 1.02 2001/10/08 Supported fiber media.
  19. Added flow control parameters.
  20. 1.03 2001/10/12 Changed the default media to 1000mbps_fd for
  21. the fiber devices.
  22. 1.04 2001/11/08 Fixed Tx stopped when tx very busy.
  23. 1.05 2001/11/22 Fixed Tx stopped when unidirectional tx busy.
  24. 1.06 2001/12/13 Fixed disconnect bug at 10Mbps mode.
  25. Fixed tx_full flag incorrect.
  26. Added tx_coalesce paramter.
  27. 1.07 2002/01/03 Fixed miscount of RX frame error.
  28. 1.08 2002/01/17 Fixed the multicast bug.
  29. 1.09 2002/03/07 Move rx-poll-now to re-fill loop.
  30. Added rio_timer() to watch rx buffers.
  31. 1.10 2002/04/16 Fixed miscount of carrier error.
  32. 1.11 2002/05/23 Added ISR schedule scheme
  33. Fixed miscount of rx frame error for DGE-550SX.
  34. Fixed VLAN bug.
  35. 1.12 2002/06/13 Lock tx_coalesce=1 on 10/100Mbps mode.
  36. 1.13 2002/08/13 1. Fix disconnection (many tx:carrier/rx:frame
  37. errs) with some mainboards.
  38. 2. Use definition "DRV_NAME" "DRV_VERSION"
  39. "DRV_RELDATE" for flexibility.
  40. 1.14 2002/08/14 Support ethtool.
  41. 1.15 2002/08/27 Changed the default media to Auto-Negotiation
  42. for the fiber devices.
  43. 1.16 2002/09/04 More power down time for fiber devices auto-
  44. negotiation.
  45. Fix disconnect bug after ifup and ifdown.
  46. 1.17 2002/10/03 Fix RMON statistics overflow.
  47. Always use I/O mapping to access eeprom,
  48. avoid system freezing with some chipsets.
  49. */
  50. #define DRV_NAME "D-Link DL2000-based linux driver"
  51. #define DRV_VERSION "v1.17b"
  52. #define DRV_RELDATE "2006/03/10"
  53. #include "dl2k.h"
  54. #include <linux/dma-mapping.h>
  55. static char version[] __devinitdata =
  56. KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
  57. #define MAX_UNITS 8
  58. static int mtu[MAX_UNITS];
  59. static int vlan[MAX_UNITS];
  60. static int jumbo[MAX_UNITS];
  61. static char *media[MAX_UNITS];
  62. static int tx_flow=-1;
  63. static int rx_flow=-1;
  64. static int copy_thresh;
  65. static int rx_coalesce=10; /* Rx frame count each interrupt */
  66. static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
  67. static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
  68. MODULE_AUTHOR ("Edward Peng");
  69. MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
  70. MODULE_LICENSE("GPL");
  71. module_param_array(mtu, int, NULL, 0);
  72. module_param_array(media, charp, NULL, 0);
  73. module_param_array(vlan, int, NULL, 0);
  74. module_param_array(jumbo, int, NULL, 0);
  75. module_param(tx_flow, int, 0);
  76. module_param(rx_flow, int, 0);
  77. module_param(copy_thresh, int, 0);
  78. module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
  79. module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
  80. module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
  81. /* Enable the default interrupts */
  82. #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
  83. UpdateStats | LinkEvent)
  84. #define EnableInt() \
  85. writew(DEFAULT_INTR, ioaddr + IntEnable)
  86. static const int max_intrloop = 50;
  87. static const int multicast_filter_limit = 0x40;
  88. static int rio_open (struct net_device *dev);
  89. static void rio_timer (unsigned long data);
  90. static void rio_tx_timeout (struct net_device *dev);
  91. static void alloc_list (struct net_device *dev);
  92. static int start_xmit (struct sk_buff *skb, struct net_device *dev);
  93. static irqreturn_t rio_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
  94. static void rio_free_tx (struct net_device *dev, int irq);
  95. static void tx_error (struct net_device *dev, int tx_status);
  96. static int receive_packet (struct net_device *dev);
  97. static void rio_error (struct net_device *dev, int int_status);
  98. static int change_mtu (struct net_device *dev, int new_mtu);
  99. static void set_multicast (struct net_device *dev);
  100. static struct net_device_stats *get_stats (struct net_device *dev);
  101. static int clear_stats (struct net_device *dev);
  102. static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
  103. static int rio_close (struct net_device *dev);
  104. static int find_miiphy (struct net_device *dev);
  105. static int parse_eeprom (struct net_device *dev);
  106. static int read_eeprom (long ioaddr, int eep_addr);
  107. static int mii_wait_link (struct net_device *dev, int wait);
  108. static int mii_set_media (struct net_device *dev);
  109. static int mii_get_media (struct net_device *dev);
  110. static int mii_set_media_pcs (struct net_device *dev);
  111. static int mii_get_media_pcs (struct net_device *dev);
  112. static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
  113. static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
  114. u16 data);
  115. static struct ethtool_ops ethtool_ops;
  116. static int __devinit
  117. rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
  118. {
  119. struct net_device *dev;
  120. struct netdev_private *np;
  121. static int card_idx;
  122. int chip_idx = ent->driver_data;
  123. int err, irq;
  124. long ioaddr;
  125. static int version_printed;
  126. void *ring_space;
  127. dma_addr_t ring_dma;
  128. if (!version_printed++)
  129. printk ("%s", version);
  130. err = pci_enable_device (pdev);
  131. if (err)
  132. return err;
  133. irq = pdev->irq;
  134. err = pci_request_regions (pdev, "dl2k");
  135. if (err)
  136. goto err_out_disable;
  137. pci_set_master (pdev);
  138. dev = alloc_etherdev (sizeof (*np));
  139. if (!dev) {
  140. err = -ENOMEM;
  141. goto err_out_res;
  142. }
  143. SET_MODULE_OWNER (dev);
  144. SET_NETDEV_DEV(dev, &pdev->dev);
  145. #ifdef MEM_MAPPING
  146. ioaddr = pci_resource_start (pdev, 1);
  147. ioaddr = (long) ioremap (ioaddr, RIO_IO_SIZE);
  148. if (!ioaddr) {
  149. err = -ENOMEM;
  150. goto err_out_dev;
  151. }
  152. #else
  153. ioaddr = pci_resource_start (pdev, 0);
  154. #endif
  155. dev->base_addr = ioaddr;
  156. dev->irq = irq;
  157. np = netdev_priv(dev);
  158. np->chip_id = chip_idx;
  159. np->pdev = pdev;
  160. spin_lock_init (&np->tx_lock);
  161. spin_lock_init (&np->rx_lock);
  162. /* Parse manual configuration */
  163. np->an_enable = 1;
  164. np->tx_coalesce = 1;
  165. if (card_idx < MAX_UNITS) {
  166. if (media[card_idx] != NULL) {
  167. np->an_enable = 0;
  168. if (strcmp (media[card_idx], "auto") == 0 ||
  169. strcmp (media[card_idx], "autosense") == 0 ||
  170. strcmp (media[card_idx], "0") == 0 ) {
  171. np->an_enable = 2;
  172. } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
  173. strcmp (media[card_idx], "4") == 0) {
  174. np->speed = 100;
  175. np->full_duplex = 1;
  176. } else if (strcmp (media[card_idx], "100mbps_hd") == 0
  177. || strcmp (media[card_idx], "3") == 0) {
  178. np->speed = 100;
  179. np->full_duplex = 0;
  180. } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
  181. strcmp (media[card_idx], "2") == 0) {
  182. np->speed = 10;
  183. np->full_duplex = 1;
  184. } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
  185. strcmp (media[card_idx], "1") == 0) {
  186. np->speed = 10;
  187. np->full_duplex = 0;
  188. } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
  189. strcmp (media[card_idx], "6") == 0) {
  190. np->speed=1000;
  191. np->full_duplex=1;
  192. } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
  193. strcmp (media[card_idx], "5") == 0) {
  194. np->speed = 1000;
  195. np->full_duplex = 0;
  196. } else {
  197. np->an_enable = 1;
  198. }
  199. }
  200. if (jumbo[card_idx] != 0) {
  201. np->jumbo = 1;
  202. dev->mtu = MAX_JUMBO;
  203. } else {
  204. np->jumbo = 0;
  205. if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
  206. dev->mtu = mtu[card_idx];
  207. }
  208. np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
  209. vlan[card_idx] : 0;
  210. if (rx_coalesce > 0 && rx_timeout > 0) {
  211. np->rx_coalesce = rx_coalesce;
  212. np->rx_timeout = rx_timeout;
  213. np->coalesce = 1;
  214. }
  215. np->tx_flow = (tx_flow == 0) ? 0 : 1;
  216. np->rx_flow = (rx_flow == 0) ? 0 : 1;
  217. if (tx_coalesce < 1)
  218. tx_coalesce = 1;
  219. else if (tx_coalesce > TX_RING_SIZE-1)
  220. tx_coalesce = TX_RING_SIZE - 1;
  221. }
  222. dev->open = &rio_open;
  223. dev->hard_start_xmit = &start_xmit;
  224. dev->stop = &rio_close;
  225. dev->get_stats = &get_stats;
  226. dev->set_multicast_list = &set_multicast;
  227. dev->do_ioctl = &rio_ioctl;
  228. dev->tx_timeout = &rio_tx_timeout;
  229. dev->watchdog_timeo = TX_TIMEOUT;
  230. dev->change_mtu = &change_mtu;
  231. SET_ETHTOOL_OPS(dev, &ethtool_ops);
  232. #if 0
  233. dev->features = NETIF_F_IP_CSUM;
  234. #endif
  235. pci_set_drvdata (pdev, dev);
  236. ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
  237. if (!ring_space)
  238. goto err_out_iounmap;
  239. np->tx_ring = (struct netdev_desc *) ring_space;
  240. np->tx_ring_dma = ring_dma;
  241. ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
  242. if (!ring_space)
  243. goto err_out_unmap_tx;
  244. np->rx_ring = (struct netdev_desc *) ring_space;
  245. np->rx_ring_dma = ring_dma;
  246. /* Parse eeprom data */
  247. parse_eeprom (dev);
  248. /* Find PHY address */
  249. err = find_miiphy (dev);
  250. if (err)
  251. goto err_out_unmap_rx;
  252. /* Fiber device? */
  253. np->phy_media = (readw(ioaddr + ASICCtrl) & PhyMedia) ? 1 : 0;
  254. np->link_status = 0;
  255. /* Set media and reset PHY */
  256. if (np->phy_media) {
  257. /* default Auto-Negotiation for fiber deivices */
  258. if (np->an_enable == 2) {
  259. np->an_enable = 1;
  260. }
  261. mii_set_media_pcs (dev);
  262. } else {
  263. /* Auto-Negotiation is mandatory for 1000BASE-T,
  264. IEEE 802.3ab Annex 28D page 14 */
  265. if (np->speed == 1000)
  266. np->an_enable = 1;
  267. mii_set_media (dev);
  268. }
  269. pci_read_config_byte(pdev, PCI_REVISION_ID, &np->pci_rev_id);
  270. err = register_netdev (dev);
  271. if (err)
  272. goto err_out_unmap_rx;
  273. card_idx++;
  274. printk (KERN_INFO "%s: %s, %02x:%02x:%02x:%02x:%02x:%02x, IRQ %d\n",
  275. dev->name, np->name,
  276. dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
  277. dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], irq);
  278. if (tx_coalesce > 1)
  279. printk(KERN_INFO "tx_coalesce:\t%d packets\n",
  280. tx_coalesce);
  281. if (np->coalesce)
  282. printk(KERN_INFO "rx_coalesce:\t%d packets\n"
  283. KERN_INFO "rx_timeout: \t%d ns\n",
  284. np->rx_coalesce, np->rx_timeout*640);
  285. if (np->vlan)
  286. printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
  287. return 0;
  288. err_out_unmap_rx:
  289. pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
  290. err_out_unmap_tx:
  291. pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
  292. err_out_iounmap:
  293. #ifdef MEM_MAPPING
  294. iounmap ((void *) ioaddr);
  295. err_out_dev:
  296. #endif
  297. free_netdev (dev);
  298. err_out_res:
  299. pci_release_regions (pdev);
  300. err_out_disable:
  301. pci_disable_device (pdev);
  302. return err;
  303. }
  304. int
  305. find_miiphy (struct net_device *dev)
  306. {
  307. int i, phy_found = 0;
  308. struct netdev_private *np;
  309. long ioaddr;
  310. np = netdev_priv(dev);
  311. ioaddr = dev->base_addr;
  312. np->phy_addr = 1;
  313. for (i = 31; i >= 0; i--) {
  314. int mii_status = mii_read (dev, i, 1);
  315. if (mii_status != 0xffff && mii_status != 0x0000) {
  316. np->phy_addr = i;
  317. phy_found++;
  318. }
  319. }
  320. if (!phy_found) {
  321. printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
  322. return -ENODEV;
  323. }
  324. return 0;
  325. }
  326. int
  327. parse_eeprom (struct net_device *dev)
  328. {
  329. int i, j;
  330. long ioaddr = dev->base_addr;
  331. u8 sromdata[256];
  332. u8 *psib;
  333. u32 crc;
  334. PSROM_t psrom = (PSROM_t) sromdata;
  335. struct netdev_private *np = netdev_priv(dev);
  336. int cid, next;
  337. #ifdef MEM_MAPPING
  338. ioaddr = pci_resource_start (np->pdev, 0);
  339. #endif
  340. /* Read eeprom */
  341. for (i = 0; i < 128; i++) {
  342. ((u16 *) sromdata)[i] = le16_to_cpu (read_eeprom (ioaddr, i));
  343. }
  344. #ifdef MEM_MAPPING
  345. ioaddr = dev->base_addr;
  346. #endif
  347. /* Check CRC */
  348. crc = ~ether_crc_le (256 - 4, sromdata);
  349. if (psrom->crc != crc) {
  350. printk (KERN_ERR "%s: EEPROM data CRC error.\n", dev->name);
  351. return -1;
  352. }
  353. /* Set MAC address */
  354. for (i = 0; i < 6; i++)
  355. dev->dev_addr[i] = psrom->mac_addr[i];
  356. /* Parse Software Infomation Block */
  357. i = 0x30;
  358. psib = (u8 *) sromdata;
  359. do {
  360. cid = psib[i++];
  361. next = psib[i++];
  362. if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
  363. printk (KERN_ERR "Cell data error\n");
  364. return -1;
  365. }
  366. switch (cid) {
  367. case 0: /* Format version */
  368. break;
  369. case 1: /* End of cell */
  370. return 0;
  371. case 2: /* Duplex Polarity */
  372. np->duplex_polarity = psib[i];
  373. writeb (readb (ioaddr + PhyCtrl) | psib[i],
  374. ioaddr + PhyCtrl);
  375. break;
  376. case 3: /* Wake Polarity */
  377. np->wake_polarity = psib[i];
  378. break;
  379. case 9: /* Adapter description */
  380. j = (next - i > 255) ? 255 : next - i;
  381. memcpy (np->name, &(psib[i]), j);
  382. break;
  383. case 4:
  384. case 5:
  385. case 6:
  386. case 7:
  387. case 8: /* Reversed */
  388. break;
  389. default: /* Unknown cell */
  390. return -1;
  391. }
  392. i = next;
  393. } while (1);
  394. return 0;
  395. }
  396. static int
  397. rio_open (struct net_device *dev)
  398. {
  399. struct netdev_private *np = netdev_priv(dev);
  400. long ioaddr = dev->base_addr;
  401. int i;
  402. u16 macctrl;
  403. i = request_irq (dev->irq, &rio_interrupt, SA_SHIRQ, dev->name, dev);
  404. if (i)
  405. return i;
  406. /* Reset all logic functions */
  407. writew (GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset,
  408. ioaddr + ASICCtrl + 2);
  409. mdelay(10);
  410. /* DebugCtrl bit 4, 5, 9 must set */
  411. writel (readl (ioaddr + DebugCtrl) | 0x0230, ioaddr + DebugCtrl);
  412. /* Jumbo frame */
  413. if (np->jumbo != 0)
  414. writew (MAX_JUMBO+14, ioaddr + MaxFrameSize);
  415. alloc_list (dev);
  416. /* Get station address */
  417. for (i = 0; i < 6; i++)
  418. writeb (dev->dev_addr[i], ioaddr + StationAddr0 + i);
  419. set_multicast (dev);
  420. if (np->coalesce) {
  421. writel (np->rx_coalesce | np->rx_timeout << 16,
  422. ioaddr + RxDMAIntCtrl);
  423. }
  424. /* Set RIO to poll every N*320nsec. */
  425. writeb (0x20, ioaddr + RxDMAPollPeriod);
  426. writeb (0xff, ioaddr + TxDMAPollPeriod);
  427. writeb (0x30, ioaddr + RxDMABurstThresh);
  428. writeb (0x30, ioaddr + RxDMAUrgentThresh);
  429. writel (0x0007ffff, ioaddr + RmonStatMask);
  430. /* clear statistics */
  431. clear_stats (dev);
  432. /* VLAN supported */
  433. if (np->vlan) {
  434. /* priority field in RxDMAIntCtrl */
  435. writel (readl(ioaddr + RxDMAIntCtrl) | 0x7 << 10,
  436. ioaddr + RxDMAIntCtrl);
  437. /* VLANId */
  438. writew (np->vlan, ioaddr + VLANId);
  439. /* Length/Type should be 0x8100 */
  440. writel (0x8100 << 16 | np->vlan, ioaddr + VLANTag);
  441. /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
  442. VLAN information tagged by TFC' VID, CFI fields. */
  443. writel (readl (ioaddr + MACCtrl) | AutoVLANuntagging,
  444. ioaddr + MACCtrl);
  445. }
  446. init_timer (&np->timer);
  447. np->timer.expires = jiffies + 1*HZ;
  448. np->timer.data = (unsigned long) dev;
  449. np->timer.function = &rio_timer;
  450. add_timer (&np->timer);
  451. /* Start Tx/Rx */
  452. writel (readl (ioaddr + MACCtrl) | StatsEnable | RxEnable | TxEnable,
  453. ioaddr + MACCtrl);
  454. macctrl = 0;
  455. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  456. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  457. macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
  458. macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
  459. writew(macctrl, ioaddr + MACCtrl);
  460. netif_start_queue (dev);
  461. /* Enable default interrupts */
  462. EnableInt ();
  463. return 0;
  464. }
  465. static void
  466. rio_timer (unsigned long data)
  467. {
  468. struct net_device *dev = (struct net_device *)data;
  469. struct netdev_private *np = netdev_priv(dev);
  470. unsigned int entry;
  471. int next_tick = 1*HZ;
  472. unsigned long flags;
  473. spin_lock_irqsave(&np->rx_lock, flags);
  474. /* Recover rx ring exhausted error */
  475. if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
  476. printk(KERN_INFO "Try to recover rx ring exhausted...\n");
  477. /* Re-allocate skbuffs to fill the descriptor ring */
  478. for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
  479. struct sk_buff *skb;
  480. entry = np->old_rx % RX_RING_SIZE;
  481. /* Dropped packets don't need to re-allocate */
  482. if (np->rx_skbuff[entry] == NULL) {
  483. skb = dev_alloc_skb (np->rx_buf_sz);
  484. if (skb == NULL) {
  485. np->rx_ring[entry].fraginfo = 0;
  486. printk (KERN_INFO
  487. "%s: Still unable to re-allocate Rx skbuff.#%d\n",
  488. dev->name, entry);
  489. break;
  490. }
  491. np->rx_skbuff[entry] = skb;
  492. skb->dev = dev;
  493. /* 16 byte align the IP header */
  494. skb_reserve (skb, 2);
  495. np->rx_ring[entry].fraginfo =
  496. cpu_to_le64 (pci_map_single
  497. (np->pdev, skb->data, np->rx_buf_sz,
  498. PCI_DMA_FROMDEVICE));
  499. }
  500. np->rx_ring[entry].fraginfo |=
  501. cpu_to_le64 (np->rx_buf_sz) << 48;
  502. np->rx_ring[entry].status = 0;
  503. } /* end for */
  504. } /* end if */
  505. spin_unlock_irqrestore (&np->rx_lock, flags);
  506. np->timer.expires = jiffies + next_tick;
  507. add_timer(&np->timer);
  508. }
  509. static void
  510. rio_tx_timeout (struct net_device *dev)
  511. {
  512. long ioaddr = dev->base_addr;
  513. printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
  514. dev->name, readl (ioaddr + TxStatus));
  515. rio_free_tx(dev, 0);
  516. dev->if_port = 0;
  517. dev->trans_start = jiffies;
  518. }
  519. /* allocate and initialize Tx and Rx descriptors */
  520. static void
  521. alloc_list (struct net_device *dev)
  522. {
  523. struct netdev_private *np = netdev_priv(dev);
  524. int i;
  525. np->cur_rx = np->cur_tx = 0;
  526. np->old_rx = np->old_tx = 0;
  527. np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
  528. /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
  529. for (i = 0; i < TX_RING_SIZE; i++) {
  530. np->tx_skbuff[i] = NULL;
  531. np->tx_ring[i].status = cpu_to_le64 (TFDDone);
  532. np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma +
  533. ((i+1)%TX_RING_SIZE) *
  534. sizeof (struct netdev_desc));
  535. }
  536. /* Initialize Rx descriptors */
  537. for (i = 0; i < RX_RING_SIZE; i++) {
  538. np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma +
  539. ((i + 1) % RX_RING_SIZE) *
  540. sizeof (struct netdev_desc));
  541. np->rx_ring[i].status = 0;
  542. np->rx_ring[i].fraginfo = 0;
  543. np->rx_skbuff[i] = NULL;
  544. }
  545. /* Allocate the rx buffers */
  546. for (i = 0; i < RX_RING_SIZE; i++) {
  547. /* Allocated fixed size of skbuff */
  548. struct sk_buff *skb = dev_alloc_skb (np->rx_buf_sz);
  549. np->rx_skbuff[i] = skb;
  550. if (skb == NULL) {
  551. printk (KERN_ERR
  552. "%s: alloc_list: allocate Rx buffer error! ",
  553. dev->name);
  554. break;
  555. }
  556. skb->dev = dev; /* Mark as being used by this device. */
  557. skb_reserve (skb, 2); /* 16 byte align the IP header. */
  558. /* Rubicon now supports 40 bits of addressing space. */
  559. np->rx_ring[i].fraginfo =
  560. cpu_to_le64 ( pci_map_single (
  561. np->pdev, skb->data, np->rx_buf_sz,
  562. PCI_DMA_FROMDEVICE));
  563. np->rx_ring[i].fraginfo |= cpu_to_le64 (np->rx_buf_sz) << 48;
  564. }
  565. /* Set RFDListPtr */
  566. writel (cpu_to_le32 (np->rx_ring_dma), dev->base_addr + RFDListPtr0);
  567. writel (0, dev->base_addr + RFDListPtr1);
  568. return;
  569. }
  570. static int
  571. start_xmit (struct sk_buff *skb, struct net_device *dev)
  572. {
  573. struct netdev_private *np = netdev_priv(dev);
  574. struct netdev_desc *txdesc;
  575. unsigned entry;
  576. u32 ioaddr;
  577. u64 tfc_vlan_tag = 0;
  578. if (np->link_status == 0) { /* Link Down */
  579. dev_kfree_skb(skb);
  580. return 0;
  581. }
  582. ioaddr = dev->base_addr;
  583. entry = np->cur_tx % TX_RING_SIZE;
  584. np->tx_skbuff[entry] = skb;
  585. txdesc = &np->tx_ring[entry];
  586. #if 0
  587. if (skb->ip_summed == CHECKSUM_HW) {
  588. txdesc->status |=
  589. cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
  590. IPChecksumEnable);
  591. }
  592. #endif
  593. if (np->vlan) {
  594. tfc_vlan_tag =
  595. cpu_to_le64 (VLANTagInsert) |
  596. (cpu_to_le64 (np->vlan) << 32) |
  597. (cpu_to_le64 (skb->priority) << 45);
  598. }
  599. txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
  600. skb->len,
  601. PCI_DMA_TODEVICE));
  602. txdesc->fraginfo |= cpu_to_le64 (skb->len) << 48;
  603. /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
  604. * Work around: Always use 1 descriptor in 10Mbps mode */
  605. if (entry % np->tx_coalesce == 0 || np->speed == 10)
  606. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  607. WordAlignDisable |
  608. TxDMAIndicate |
  609. (1 << FragCountShift));
  610. else
  611. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  612. WordAlignDisable |
  613. (1 << FragCountShift));
  614. /* TxDMAPollNow */
  615. writel (readl (ioaddr + DMACtrl) | 0x00001000, ioaddr + DMACtrl);
  616. /* Schedule ISR */
  617. writel(10000, ioaddr + CountDown);
  618. np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
  619. if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  620. < TX_QUEUE_LEN - 1 && np->speed != 10) {
  621. /* do nothing */
  622. } else if (!netif_queue_stopped(dev)) {
  623. netif_stop_queue (dev);
  624. }
  625. /* The first TFDListPtr */
  626. if (readl (dev->base_addr + TFDListPtr0) == 0) {
  627. writel (np->tx_ring_dma + entry * sizeof (struct netdev_desc),
  628. dev->base_addr + TFDListPtr0);
  629. writel (0, dev->base_addr + TFDListPtr1);
  630. }
  631. /* NETDEV WATCHDOG timer */
  632. dev->trans_start = jiffies;
  633. return 0;
  634. }
  635. static irqreturn_t
  636. rio_interrupt (int irq, void *dev_instance, struct pt_regs *rgs)
  637. {
  638. struct net_device *dev = dev_instance;
  639. struct netdev_private *np;
  640. unsigned int_status;
  641. long ioaddr;
  642. int cnt = max_intrloop;
  643. int handled = 0;
  644. ioaddr = dev->base_addr;
  645. np = netdev_priv(dev);
  646. while (1) {
  647. int_status = readw (ioaddr + IntStatus);
  648. writew (int_status, ioaddr + IntStatus);
  649. int_status &= DEFAULT_INTR;
  650. if (int_status == 0 || --cnt < 0)
  651. break;
  652. handled = 1;
  653. /* Processing received packets */
  654. if (int_status & RxDMAComplete)
  655. receive_packet (dev);
  656. /* TxDMAComplete interrupt */
  657. if ((int_status & (TxDMAComplete|IntRequested))) {
  658. int tx_status;
  659. tx_status = readl (ioaddr + TxStatus);
  660. if (tx_status & 0x01)
  661. tx_error (dev, tx_status);
  662. /* Free used tx skbuffs */
  663. rio_free_tx (dev, 1);
  664. }
  665. /* Handle uncommon events */
  666. if (int_status &
  667. (HostError | LinkEvent | UpdateStats))
  668. rio_error (dev, int_status);
  669. }
  670. if (np->cur_tx != np->old_tx)
  671. writel (100, ioaddr + CountDown);
  672. return IRQ_RETVAL(handled);
  673. }
  674. static void
  675. rio_free_tx (struct net_device *dev, int irq)
  676. {
  677. struct netdev_private *np = netdev_priv(dev);
  678. int entry = np->old_tx % TX_RING_SIZE;
  679. int tx_use = 0;
  680. unsigned long flag = 0;
  681. if (irq)
  682. spin_lock(&np->tx_lock);
  683. else
  684. spin_lock_irqsave(&np->tx_lock, flag);
  685. /* Free used tx skbuffs */
  686. while (entry != np->cur_tx) {
  687. struct sk_buff *skb;
  688. if (!(np->tx_ring[entry].status & TFDDone))
  689. break;
  690. skb = np->tx_skbuff[entry];
  691. pci_unmap_single (np->pdev,
  692. np->tx_ring[entry].fraginfo & DMA_48BIT_MASK,
  693. skb->len, PCI_DMA_TODEVICE);
  694. if (irq)
  695. dev_kfree_skb_irq (skb);
  696. else
  697. dev_kfree_skb (skb);
  698. np->tx_skbuff[entry] = NULL;
  699. entry = (entry + 1) % TX_RING_SIZE;
  700. tx_use++;
  701. }
  702. if (irq)
  703. spin_unlock(&np->tx_lock);
  704. else
  705. spin_unlock_irqrestore(&np->tx_lock, flag);
  706. np->old_tx = entry;
  707. /* If the ring is no longer full, clear tx_full and
  708. call netif_wake_queue() */
  709. if (netif_queue_stopped(dev) &&
  710. ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  711. < TX_QUEUE_LEN - 1 || np->speed == 10)) {
  712. netif_wake_queue (dev);
  713. }
  714. }
  715. static void
  716. tx_error (struct net_device *dev, int tx_status)
  717. {
  718. struct netdev_private *np;
  719. long ioaddr = dev->base_addr;
  720. int frame_id;
  721. int i;
  722. np = netdev_priv(dev);
  723. frame_id = (tx_status & 0xffff0000);
  724. printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
  725. dev->name, tx_status, frame_id);
  726. np->stats.tx_errors++;
  727. /* Ttransmit Underrun */
  728. if (tx_status & 0x10) {
  729. np->stats.tx_fifo_errors++;
  730. writew (readw (ioaddr + TxStartThresh) + 0x10,
  731. ioaddr + TxStartThresh);
  732. /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
  733. writew (TxReset | DMAReset | FIFOReset | NetworkReset,
  734. ioaddr + ASICCtrl + 2);
  735. /* Wait for ResetBusy bit clear */
  736. for (i = 50; i > 0; i--) {
  737. if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
  738. break;
  739. mdelay (1);
  740. }
  741. rio_free_tx (dev, 1);
  742. /* Reset TFDListPtr */
  743. writel (np->tx_ring_dma +
  744. np->old_tx * sizeof (struct netdev_desc),
  745. dev->base_addr + TFDListPtr0);
  746. writel (0, dev->base_addr + TFDListPtr1);
  747. /* Let TxStartThresh stay default value */
  748. }
  749. /* Late Collision */
  750. if (tx_status & 0x04) {
  751. np->stats.tx_fifo_errors++;
  752. /* TxReset and clear FIFO */
  753. writew (TxReset | FIFOReset, ioaddr + ASICCtrl + 2);
  754. /* Wait reset done */
  755. for (i = 50; i > 0; i--) {
  756. if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
  757. break;
  758. mdelay (1);
  759. }
  760. /* Let TxStartThresh stay default value */
  761. }
  762. /* Maximum Collisions */
  763. #ifdef ETHER_STATS
  764. if (tx_status & 0x08)
  765. np->stats.collisions16++;
  766. #else
  767. if (tx_status & 0x08)
  768. np->stats.collisions++;
  769. #endif
  770. /* Restart the Tx */
  771. writel (readw (dev->base_addr + MACCtrl) | TxEnable, ioaddr + MACCtrl);
  772. }
  773. static int
  774. receive_packet (struct net_device *dev)
  775. {
  776. struct netdev_private *np = netdev_priv(dev);
  777. int entry = np->cur_rx % RX_RING_SIZE;
  778. int cnt = 30;
  779. /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
  780. while (1) {
  781. struct netdev_desc *desc = &np->rx_ring[entry];
  782. int pkt_len;
  783. u64 frame_status;
  784. if (!(desc->status & RFDDone) ||
  785. !(desc->status & FrameStart) || !(desc->status & FrameEnd))
  786. break;
  787. /* Chip omits the CRC. */
  788. pkt_len = le64_to_cpu (desc->status & 0xffff);
  789. frame_status = le64_to_cpu (desc->status);
  790. if (--cnt < 0)
  791. break;
  792. /* Update rx error statistics, drop packet. */
  793. if (frame_status & RFS_Errors) {
  794. np->stats.rx_errors++;
  795. if (frame_status & (RxRuntFrame | RxLengthError))
  796. np->stats.rx_length_errors++;
  797. if (frame_status & RxFCSError)
  798. np->stats.rx_crc_errors++;
  799. if (frame_status & RxAlignmentError && np->speed != 1000)
  800. np->stats.rx_frame_errors++;
  801. if (frame_status & RxFIFOOverrun)
  802. np->stats.rx_fifo_errors++;
  803. } else {
  804. struct sk_buff *skb;
  805. /* Small skbuffs for short packets */
  806. if (pkt_len > copy_thresh) {
  807. pci_unmap_single (np->pdev,
  808. desc->fraginfo & DMA_48BIT_MASK,
  809. np->rx_buf_sz,
  810. PCI_DMA_FROMDEVICE);
  811. skb_put (skb = np->rx_skbuff[entry], pkt_len);
  812. np->rx_skbuff[entry] = NULL;
  813. } else if ((skb = dev_alloc_skb (pkt_len + 2)) != NULL) {
  814. pci_dma_sync_single_for_cpu(np->pdev,
  815. desc->fraginfo &
  816. DMA_48BIT_MASK,
  817. np->rx_buf_sz,
  818. PCI_DMA_FROMDEVICE);
  819. skb->dev = dev;
  820. /* 16 byte align the IP header */
  821. skb_reserve (skb, 2);
  822. eth_copy_and_sum (skb,
  823. np->rx_skbuff[entry]->data,
  824. pkt_len, 0);
  825. skb_put (skb, pkt_len);
  826. pci_dma_sync_single_for_device(np->pdev,
  827. desc->fraginfo &
  828. DMA_48BIT_MASK,
  829. np->rx_buf_sz,
  830. PCI_DMA_FROMDEVICE);
  831. }
  832. skb->protocol = eth_type_trans (skb, dev);
  833. #if 0
  834. /* Checksum done by hw, but csum value unavailable. */
  835. if (np->pci_rev_id >= 0x0c &&
  836. !(frame_status & (TCPError | UDPError | IPError))) {
  837. skb->ip_summed = CHECKSUM_UNNECESSARY;
  838. }
  839. #endif
  840. netif_rx (skb);
  841. dev->last_rx = jiffies;
  842. }
  843. entry = (entry + 1) % RX_RING_SIZE;
  844. }
  845. spin_lock(&np->rx_lock);
  846. np->cur_rx = entry;
  847. /* Re-allocate skbuffs to fill the descriptor ring */
  848. entry = np->old_rx;
  849. while (entry != np->cur_rx) {
  850. struct sk_buff *skb;
  851. /* Dropped packets don't need to re-allocate */
  852. if (np->rx_skbuff[entry] == NULL) {
  853. skb = dev_alloc_skb (np->rx_buf_sz);
  854. if (skb == NULL) {
  855. np->rx_ring[entry].fraginfo = 0;
  856. printk (KERN_INFO
  857. "%s: receive_packet: "
  858. "Unable to re-allocate Rx skbuff.#%d\n",
  859. dev->name, entry);
  860. break;
  861. }
  862. np->rx_skbuff[entry] = skb;
  863. skb->dev = dev;
  864. /* 16 byte align the IP header */
  865. skb_reserve (skb, 2);
  866. np->rx_ring[entry].fraginfo =
  867. cpu_to_le64 (pci_map_single
  868. (np->pdev, skb->data, np->rx_buf_sz,
  869. PCI_DMA_FROMDEVICE));
  870. }
  871. np->rx_ring[entry].fraginfo |=
  872. cpu_to_le64 (np->rx_buf_sz) << 48;
  873. np->rx_ring[entry].status = 0;
  874. entry = (entry + 1) % RX_RING_SIZE;
  875. }
  876. np->old_rx = entry;
  877. spin_unlock(&np->rx_lock);
  878. return 0;
  879. }
  880. static void
  881. rio_error (struct net_device *dev, int int_status)
  882. {
  883. long ioaddr = dev->base_addr;
  884. struct netdev_private *np = netdev_priv(dev);
  885. u16 macctrl;
  886. /* Link change event */
  887. if (int_status & LinkEvent) {
  888. if (mii_wait_link (dev, 10) == 0) {
  889. printk (KERN_INFO "%s: Link up\n", dev->name);
  890. if (np->phy_media)
  891. mii_get_media_pcs (dev);
  892. else
  893. mii_get_media (dev);
  894. if (np->speed == 1000)
  895. np->tx_coalesce = tx_coalesce;
  896. else
  897. np->tx_coalesce = 1;
  898. macctrl = 0;
  899. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  900. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  901. macctrl |= (np->tx_flow) ?
  902. TxFlowControlEnable : 0;
  903. macctrl |= (np->rx_flow) ?
  904. RxFlowControlEnable : 0;
  905. writew(macctrl, ioaddr + MACCtrl);
  906. np->link_status = 1;
  907. netif_carrier_on(dev);
  908. } else {
  909. printk (KERN_INFO "%s: Link off\n", dev->name);
  910. np->link_status = 0;
  911. netif_carrier_off(dev);
  912. }
  913. }
  914. /* UpdateStats statistics registers */
  915. if (int_status & UpdateStats) {
  916. get_stats (dev);
  917. }
  918. /* PCI Error, a catastronphic error related to the bus interface
  919. occurs, set GlobalReset and HostReset to reset. */
  920. if (int_status & HostError) {
  921. printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
  922. dev->name, int_status);
  923. writew (GlobalReset | HostReset, ioaddr + ASICCtrl + 2);
  924. mdelay (500);
  925. }
  926. }
  927. static struct net_device_stats *
  928. get_stats (struct net_device *dev)
  929. {
  930. long ioaddr = dev->base_addr;
  931. struct netdev_private *np = netdev_priv(dev);
  932. #ifdef MEM_MAPPING
  933. int i;
  934. #endif
  935. unsigned int stat_reg;
  936. /* All statistics registers need to be acknowledged,
  937. else statistic overflow could cause problems */
  938. np->stats.rx_packets += readl (ioaddr + FramesRcvOk);
  939. np->stats.tx_packets += readl (ioaddr + FramesXmtOk);
  940. np->stats.rx_bytes += readl (ioaddr + OctetRcvOk);
  941. np->stats.tx_bytes += readl (ioaddr + OctetXmtOk);
  942. np->stats.multicast = readl (ioaddr + McstFramesRcvdOk);
  943. np->stats.collisions += readl (ioaddr + SingleColFrames)
  944. + readl (ioaddr + MultiColFrames);
  945. /* detailed tx errors */
  946. stat_reg = readw (ioaddr + FramesAbortXSColls);
  947. np->stats.tx_aborted_errors += stat_reg;
  948. np->stats.tx_errors += stat_reg;
  949. stat_reg = readw (ioaddr + CarrierSenseErrors);
  950. np->stats.tx_carrier_errors += stat_reg;
  951. np->stats.tx_errors += stat_reg;
  952. /* Clear all other statistic register. */
  953. readl (ioaddr + McstOctetXmtOk);
  954. readw (ioaddr + BcstFramesXmtdOk);
  955. readl (ioaddr + McstFramesXmtdOk);
  956. readw (ioaddr + BcstFramesRcvdOk);
  957. readw (ioaddr + MacControlFramesRcvd);
  958. readw (ioaddr + FrameTooLongErrors);
  959. readw (ioaddr + InRangeLengthErrors);
  960. readw (ioaddr + FramesCheckSeqErrors);
  961. readw (ioaddr + FramesLostRxErrors);
  962. readl (ioaddr + McstOctetXmtOk);
  963. readl (ioaddr + BcstOctetXmtOk);
  964. readl (ioaddr + McstFramesXmtdOk);
  965. readl (ioaddr + FramesWDeferredXmt);
  966. readl (ioaddr + LateCollisions);
  967. readw (ioaddr + BcstFramesXmtdOk);
  968. readw (ioaddr + MacControlFramesXmtd);
  969. readw (ioaddr + FramesWEXDeferal);
  970. #ifdef MEM_MAPPING
  971. for (i = 0x100; i <= 0x150; i += 4)
  972. readl (ioaddr + i);
  973. #endif
  974. readw (ioaddr + TxJumboFrames);
  975. readw (ioaddr + RxJumboFrames);
  976. readw (ioaddr + TCPCheckSumErrors);
  977. readw (ioaddr + UDPCheckSumErrors);
  978. readw (ioaddr + IPCheckSumErrors);
  979. return &np->stats;
  980. }
  981. static int
  982. clear_stats (struct net_device *dev)
  983. {
  984. long ioaddr = dev->base_addr;
  985. #ifdef MEM_MAPPING
  986. int i;
  987. #endif
  988. /* All statistics registers need to be acknowledged,
  989. else statistic overflow could cause problems */
  990. readl (ioaddr + FramesRcvOk);
  991. readl (ioaddr + FramesXmtOk);
  992. readl (ioaddr + OctetRcvOk);
  993. readl (ioaddr + OctetXmtOk);
  994. readl (ioaddr + McstFramesRcvdOk);
  995. readl (ioaddr + SingleColFrames);
  996. readl (ioaddr + MultiColFrames);
  997. readl (ioaddr + LateCollisions);
  998. /* detailed rx errors */
  999. readw (ioaddr + FrameTooLongErrors);
  1000. readw (ioaddr + InRangeLengthErrors);
  1001. readw (ioaddr + FramesCheckSeqErrors);
  1002. readw (ioaddr + FramesLostRxErrors);
  1003. /* detailed tx errors */
  1004. readw (ioaddr + FramesAbortXSColls);
  1005. readw (ioaddr + CarrierSenseErrors);
  1006. /* Clear all other statistic register. */
  1007. readl (ioaddr + McstOctetXmtOk);
  1008. readw (ioaddr + BcstFramesXmtdOk);
  1009. readl (ioaddr + McstFramesXmtdOk);
  1010. readw (ioaddr + BcstFramesRcvdOk);
  1011. readw (ioaddr + MacControlFramesRcvd);
  1012. readl (ioaddr + McstOctetXmtOk);
  1013. readl (ioaddr + BcstOctetXmtOk);
  1014. readl (ioaddr + McstFramesXmtdOk);
  1015. readl (ioaddr + FramesWDeferredXmt);
  1016. readw (ioaddr + BcstFramesXmtdOk);
  1017. readw (ioaddr + MacControlFramesXmtd);
  1018. readw (ioaddr + FramesWEXDeferal);
  1019. #ifdef MEM_MAPPING
  1020. for (i = 0x100; i <= 0x150; i += 4)
  1021. readl (ioaddr + i);
  1022. #endif
  1023. readw (ioaddr + TxJumboFrames);
  1024. readw (ioaddr + RxJumboFrames);
  1025. readw (ioaddr + TCPCheckSumErrors);
  1026. readw (ioaddr + UDPCheckSumErrors);
  1027. readw (ioaddr + IPCheckSumErrors);
  1028. return 0;
  1029. }
  1030. int
  1031. change_mtu (struct net_device *dev, int new_mtu)
  1032. {
  1033. struct netdev_private *np = netdev_priv(dev);
  1034. int max = (np->jumbo) ? MAX_JUMBO : 1536;
  1035. if ((new_mtu < 68) || (new_mtu > max)) {
  1036. return -EINVAL;
  1037. }
  1038. dev->mtu = new_mtu;
  1039. return 0;
  1040. }
  1041. static void
  1042. set_multicast (struct net_device *dev)
  1043. {
  1044. long ioaddr = dev->base_addr;
  1045. u32 hash_table[2];
  1046. u16 rx_mode = 0;
  1047. struct netdev_private *np = netdev_priv(dev);
  1048. hash_table[0] = hash_table[1] = 0;
  1049. /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
  1050. hash_table[1] |= cpu_to_le32(0x02000000);
  1051. if (dev->flags & IFF_PROMISC) {
  1052. /* Receive all frames promiscuously. */
  1053. rx_mode = ReceiveAllFrames;
  1054. } else if ((dev->flags & IFF_ALLMULTI) ||
  1055. (dev->mc_count > multicast_filter_limit)) {
  1056. /* Receive broadcast and multicast frames */
  1057. rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
  1058. } else if (dev->mc_count > 0) {
  1059. int i;
  1060. struct dev_mc_list *mclist;
  1061. /* Receive broadcast frames and multicast frames filtering
  1062. by Hashtable */
  1063. rx_mode =
  1064. ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
  1065. for (i=0, mclist = dev->mc_list; mclist && i < dev->mc_count;
  1066. i++, mclist=mclist->next)
  1067. {
  1068. int bit, index = 0;
  1069. int crc = ether_crc_le (ETH_ALEN, mclist->dmi_addr);
  1070. /* The inverted high significant 6 bits of CRC are
  1071. used as an index to hashtable */
  1072. for (bit = 0; bit < 6; bit++)
  1073. if (crc & (1 << (31 - bit)))
  1074. index |= (1 << bit);
  1075. hash_table[index / 32] |= (1 << (index % 32));
  1076. }
  1077. } else {
  1078. rx_mode = ReceiveBroadcast | ReceiveUnicast;
  1079. }
  1080. if (np->vlan) {
  1081. /* ReceiveVLANMatch field in ReceiveMode */
  1082. rx_mode |= ReceiveVLANMatch;
  1083. }
  1084. writel (hash_table[0], ioaddr + HashTable0);
  1085. writel (hash_table[1], ioaddr + HashTable1);
  1086. writew (rx_mode, ioaddr + ReceiveMode);
  1087. }
  1088. static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  1089. {
  1090. struct netdev_private *np = netdev_priv(dev);
  1091. strcpy(info->driver, "dl2k");
  1092. strcpy(info->version, DRV_VERSION);
  1093. strcpy(info->bus_info, pci_name(np->pdev));
  1094. }
  1095. static int rio_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1096. {
  1097. struct netdev_private *np = netdev_priv(dev);
  1098. if (np->phy_media) {
  1099. /* fiber device */
  1100. cmd->supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
  1101. cmd->advertising= ADVERTISED_Autoneg | ADVERTISED_FIBRE;
  1102. cmd->port = PORT_FIBRE;
  1103. cmd->transceiver = XCVR_INTERNAL;
  1104. } else {
  1105. /* copper device */
  1106. cmd->supported = SUPPORTED_10baseT_Half |
  1107. SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
  1108. | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
  1109. SUPPORTED_Autoneg | SUPPORTED_MII;
  1110. cmd->advertising = ADVERTISED_10baseT_Half |
  1111. ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
  1112. ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full|
  1113. ADVERTISED_Autoneg | ADVERTISED_MII;
  1114. cmd->port = PORT_MII;
  1115. cmd->transceiver = XCVR_INTERNAL;
  1116. }
  1117. if ( np->link_status ) {
  1118. cmd->speed = np->speed;
  1119. cmd->duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
  1120. } else {
  1121. cmd->speed = -1;
  1122. cmd->duplex = -1;
  1123. }
  1124. if ( np->an_enable)
  1125. cmd->autoneg = AUTONEG_ENABLE;
  1126. else
  1127. cmd->autoneg = AUTONEG_DISABLE;
  1128. cmd->phy_address = np->phy_addr;
  1129. return 0;
  1130. }
  1131. static int rio_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1132. {
  1133. struct netdev_private *np = netdev_priv(dev);
  1134. netif_carrier_off(dev);
  1135. if (cmd->autoneg == AUTONEG_ENABLE) {
  1136. if (np->an_enable)
  1137. return 0;
  1138. else {
  1139. np->an_enable = 1;
  1140. mii_set_media(dev);
  1141. return 0;
  1142. }
  1143. } else {
  1144. np->an_enable = 0;
  1145. if (np->speed == 1000) {
  1146. cmd->speed = SPEED_100;
  1147. cmd->duplex = DUPLEX_FULL;
  1148. printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
  1149. }
  1150. switch(cmd->speed + cmd->duplex) {
  1151. case SPEED_10 + DUPLEX_HALF:
  1152. np->speed = 10;
  1153. np->full_duplex = 0;
  1154. break;
  1155. case SPEED_10 + DUPLEX_FULL:
  1156. np->speed = 10;
  1157. np->full_duplex = 1;
  1158. break;
  1159. case SPEED_100 + DUPLEX_HALF:
  1160. np->speed = 100;
  1161. np->full_duplex = 0;
  1162. break;
  1163. case SPEED_100 + DUPLEX_FULL:
  1164. np->speed = 100;
  1165. np->full_duplex = 1;
  1166. break;
  1167. case SPEED_1000 + DUPLEX_HALF:/* not supported */
  1168. case SPEED_1000 + DUPLEX_FULL:/* not supported */
  1169. default:
  1170. return -EINVAL;
  1171. }
  1172. mii_set_media(dev);
  1173. }
  1174. return 0;
  1175. }
  1176. static u32 rio_get_link(struct net_device *dev)
  1177. {
  1178. struct netdev_private *np = netdev_priv(dev);
  1179. return np->link_status;
  1180. }
  1181. static struct ethtool_ops ethtool_ops = {
  1182. .get_drvinfo = rio_get_drvinfo,
  1183. .get_settings = rio_get_settings,
  1184. .set_settings = rio_set_settings,
  1185. .get_link = rio_get_link,
  1186. };
  1187. static int
  1188. rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
  1189. {
  1190. int phy_addr;
  1191. struct netdev_private *np = netdev_priv(dev);
  1192. struct mii_data *miidata = (struct mii_data *) &rq->ifr_ifru;
  1193. struct netdev_desc *desc;
  1194. int i;
  1195. phy_addr = np->phy_addr;
  1196. switch (cmd) {
  1197. case SIOCDEVPRIVATE:
  1198. break;
  1199. case SIOCDEVPRIVATE + 1:
  1200. miidata->out_value = mii_read (dev, phy_addr, miidata->reg_num);
  1201. break;
  1202. case SIOCDEVPRIVATE + 2:
  1203. mii_write (dev, phy_addr, miidata->reg_num, miidata->in_value);
  1204. break;
  1205. case SIOCDEVPRIVATE + 3:
  1206. break;
  1207. case SIOCDEVPRIVATE + 4:
  1208. break;
  1209. case SIOCDEVPRIVATE + 5:
  1210. netif_stop_queue (dev);
  1211. break;
  1212. case SIOCDEVPRIVATE + 6:
  1213. netif_wake_queue (dev);
  1214. break;
  1215. case SIOCDEVPRIVATE + 7:
  1216. printk
  1217. ("tx_full=%x cur_tx=%lx old_tx=%lx cur_rx=%lx old_rx=%lx\n",
  1218. netif_queue_stopped(dev), np->cur_tx, np->old_tx, np->cur_rx,
  1219. np->old_rx);
  1220. break;
  1221. case SIOCDEVPRIVATE + 8:
  1222. printk("TX ring:\n");
  1223. for (i = 0; i < TX_RING_SIZE; i++) {
  1224. desc = &np->tx_ring[i];
  1225. printk
  1226. ("%02x:cur:%08x next:%08x status:%08x frag1:%08x frag0:%08x",
  1227. i,
  1228. (u32) (np->tx_ring_dma + i * sizeof (*desc)),
  1229. (u32) desc->next_desc,
  1230. (u32) desc->status, (u32) (desc->fraginfo >> 32),
  1231. (u32) desc->fraginfo);
  1232. printk ("\n");
  1233. }
  1234. printk ("\n");
  1235. break;
  1236. default:
  1237. return -EOPNOTSUPP;
  1238. }
  1239. return 0;
  1240. }
  1241. #define EEP_READ 0x0200
  1242. #define EEP_BUSY 0x8000
  1243. /* Read the EEPROM word */
  1244. /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
  1245. int
  1246. read_eeprom (long ioaddr, int eep_addr)
  1247. {
  1248. int i = 1000;
  1249. outw (EEP_READ | (eep_addr & 0xff), ioaddr + EepromCtrl);
  1250. while (i-- > 0) {
  1251. if (!(inw (ioaddr + EepromCtrl) & EEP_BUSY)) {
  1252. return inw (ioaddr + EepromData);
  1253. }
  1254. }
  1255. return 0;
  1256. }
  1257. enum phy_ctrl_bits {
  1258. MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
  1259. MII_DUPLEX = 0x08,
  1260. };
  1261. #define mii_delay() readb(ioaddr)
  1262. static void
  1263. mii_sendbit (struct net_device *dev, u32 data)
  1264. {
  1265. long ioaddr = dev->base_addr + PhyCtrl;
  1266. data = (data) ? MII_DATA1 : 0;
  1267. data |= MII_WRITE;
  1268. data |= (readb (ioaddr) & 0xf8) | MII_WRITE;
  1269. writeb (data, ioaddr);
  1270. mii_delay ();
  1271. writeb (data | MII_CLK, ioaddr);
  1272. mii_delay ();
  1273. }
  1274. static int
  1275. mii_getbit (struct net_device *dev)
  1276. {
  1277. long ioaddr = dev->base_addr + PhyCtrl;
  1278. u8 data;
  1279. data = (readb (ioaddr) & 0xf8) | MII_READ;
  1280. writeb (data, ioaddr);
  1281. mii_delay ();
  1282. writeb (data | MII_CLK, ioaddr);
  1283. mii_delay ();
  1284. return ((readb (ioaddr) >> 1) & 1);
  1285. }
  1286. static void
  1287. mii_send_bits (struct net_device *dev, u32 data, int len)
  1288. {
  1289. int i;
  1290. for (i = len - 1; i >= 0; i--) {
  1291. mii_sendbit (dev, data & (1 << i));
  1292. }
  1293. }
  1294. static int
  1295. mii_read (struct net_device *dev, int phy_addr, int reg_num)
  1296. {
  1297. u32 cmd;
  1298. int i;
  1299. u32 retval = 0;
  1300. /* Preamble */
  1301. mii_send_bits (dev, 0xffffffff, 32);
  1302. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1303. /* ST,OP = 0110'b for read operation */
  1304. cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
  1305. mii_send_bits (dev, cmd, 14);
  1306. /* Turnaround */
  1307. if (mii_getbit (dev))
  1308. goto err_out;
  1309. /* Read data */
  1310. for (i = 0; i < 16; i++) {
  1311. retval |= mii_getbit (dev);
  1312. retval <<= 1;
  1313. }
  1314. /* End cycle */
  1315. mii_getbit (dev);
  1316. return (retval >> 1) & 0xffff;
  1317. err_out:
  1318. return 0;
  1319. }
  1320. static int
  1321. mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
  1322. {
  1323. u32 cmd;
  1324. /* Preamble */
  1325. mii_send_bits (dev, 0xffffffff, 32);
  1326. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1327. /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
  1328. cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
  1329. mii_send_bits (dev, cmd, 32);
  1330. /* End cycle */
  1331. mii_getbit (dev);
  1332. return 0;
  1333. }
  1334. static int
  1335. mii_wait_link (struct net_device *dev, int wait)
  1336. {
  1337. BMSR_t bmsr;
  1338. int phy_addr;
  1339. struct netdev_private *np;
  1340. np = netdev_priv(dev);
  1341. phy_addr = np->phy_addr;
  1342. do {
  1343. bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
  1344. if (bmsr.bits.link_status)
  1345. return 0;
  1346. mdelay (1);
  1347. } while (--wait > 0);
  1348. return -1;
  1349. }
  1350. static int
  1351. mii_get_media (struct net_device *dev)
  1352. {
  1353. ANAR_t negotiate;
  1354. BMSR_t bmsr;
  1355. BMCR_t bmcr;
  1356. MSCR_t mscr;
  1357. MSSR_t mssr;
  1358. int phy_addr;
  1359. struct netdev_private *np;
  1360. np = netdev_priv(dev);
  1361. phy_addr = np->phy_addr;
  1362. bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
  1363. if (np->an_enable) {
  1364. if (!bmsr.bits.an_complete) {
  1365. /* Auto-Negotiation not completed */
  1366. return -1;
  1367. }
  1368. negotiate.image = mii_read (dev, phy_addr, MII_ANAR) &
  1369. mii_read (dev, phy_addr, MII_ANLPAR);
  1370. mscr.image = mii_read (dev, phy_addr, MII_MSCR);
  1371. mssr.image = mii_read (dev, phy_addr, MII_MSSR);
  1372. if (mscr.bits.media_1000BT_FD & mssr.bits.lp_1000BT_FD) {
  1373. np->speed = 1000;
  1374. np->full_duplex = 1;
  1375. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1376. } else if (mscr.bits.media_1000BT_HD & mssr.bits.lp_1000BT_HD) {
  1377. np->speed = 1000;
  1378. np->full_duplex = 0;
  1379. printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
  1380. } else if (negotiate.bits.media_100BX_FD) {
  1381. np->speed = 100;
  1382. np->full_duplex = 1;
  1383. printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
  1384. } else if (negotiate.bits.media_100BX_HD) {
  1385. np->speed = 100;
  1386. np->full_duplex = 0;
  1387. printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
  1388. } else if (negotiate.bits.media_10BT_FD) {
  1389. np->speed = 10;
  1390. np->full_duplex = 1;
  1391. printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
  1392. } else if (negotiate.bits.media_10BT_HD) {
  1393. np->speed = 10;
  1394. np->full_duplex = 0;
  1395. printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
  1396. }
  1397. if (negotiate.bits.pause) {
  1398. np->tx_flow &= 1;
  1399. np->rx_flow &= 1;
  1400. } else if (negotiate.bits.asymmetric) {
  1401. np->tx_flow = 0;
  1402. np->rx_flow &= 1;
  1403. }
  1404. /* else tx_flow, rx_flow = user select */
  1405. } else {
  1406. bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
  1407. if (bmcr.bits.speed100 == 1 && bmcr.bits.speed1000 == 0) {
  1408. printk (KERN_INFO "Operating at 100 Mbps, ");
  1409. } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 0) {
  1410. printk (KERN_INFO "Operating at 10 Mbps, ");
  1411. } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 1) {
  1412. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1413. }
  1414. if (bmcr.bits.duplex_mode) {
  1415. printk ("Full duplex\n");
  1416. } else {
  1417. printk ("Half duplex\n");
  1418. }
  1419. }
  1420. if (np->tx_flow)
  1421. printk(KERN_INFO "Enable Tx Flow Control\n");
  1422. else
  1423. printk(KERN_INFO "Disable Tx Flow Control\n");
  1424. if (np->rx_flow)
  1425. printk(KERN_INFO "Enable Rx Flow Control\n");
  1426. else
  1427. printk(KERN_INFO "Disable Rx Flow Control\n");
  1428. return 0;
  1429. }
  1430. static int
  1431. mii_set_media (struct net_device *dev)
  1432. {
  1433. PHY_SCR_t pscr;
  1434. BMCR_t bmcr;
  1435. BMSR_t bmsr;
  1436. ANAR_t anar;
  1437. int phy_addr;
  1438. struct netdev_private *np;
  1439. np = netdev_priv(dev);
  1440. phy_addr = np->phy_addr;
  1441. /* Does user set speed? */
  1442. if (np->an_enable) {
  1443. /* Advertise capabilities */
  1444. bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
  1445. anar.image = mii_read (dev, phy_addr, MII_ANAR);
  1446. anar.bits.media_100BX_FD = bmsr.bits.media_100BX_FD;
  1447. anar.bits.media_100BX_HD = bmsr.bits.media_100BX_HD;
  1448. anar.bits.media_100BT4 = bmsr.bits.media_100BT4;
  1449. anar.bits.media_10BT_FD = bmsr.bits.media_10BT_FD;
  1450. anar.bits.media_10BT_HD = bmsr.bits.media_10BT_HD;
  1451. anar.bits.pause = 1;
  1452. anar.bits.asymmetric = 1;
  1453. mii_write (dev, phy_addr, MII_ANAR, anar.image);
  1454. /* Enable Auto crossover */
  1455. pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR);
  1456. pscr.bits.mdi_crossover_mode = 3; /* 11'b */
  1457. mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image);
  1458. /* Soft reset PHY */
  1459. mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
  1460. bmcr.image = 0;
  1461. bmcr.bits.an_enable = 1;
  1462. bmcr.bits.restart_an = 1;
  1463. bmcr.bits.reset = 1;
  1464. mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
  1465. mdelay(1);
  1466. } else {
  1467. /* Force speed setting */
  1468. /* 1) Disable Auto crossover */
  1469. pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR);
  1470. pscr.bits.mdi_crossover_mode = 0;
  1471. mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image);
  1472. /* 2) PHY Reset */
  1473. bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
  1474. bmcr.bits.reset = 1;
  1475. mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
  1476. /* 3) Power Down */
  1477. bmcr.image = 0x1940; /* must be 0x1940 */
  1478. mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
  1479. mdelay (100); /* wait a certain time */
  1480. /* 4) Advertise nothing */
  1481. mii_write (dev, phy_addr, MII_ANAR, 0);
  1482. /* 5) Set media and Power Up */
  1483. bmcr.image = 0;
  1484. bmcr.bits.power_down = 1;
  1485. if (np->speed == 100) {
  1486. bmcr.bits.speed100 = 1;
  1487. bmcr.bits.speed1000 = 0;
  1488. printk (KERN_INFO "Manual 100 Mbps, ");
  1489. } else if (np->speed == 10) {
  1490. bmcr.bits.speed100 = 0;
  1491. bmcr.bits.speed1000 = 0;
  1492. printk (KERN_INFO "Manual 10 Mbps, ");
  1493. }
  1494. if (np->full_duplex) {
  1495. bmcr.bits.duplex_mode = 1;
  1496. printk ("Full duplex\n");
  1497. } else {
  1498. bmcr.bits.duplex_mode = 0;
  1499. printk ("Half duplex\n");
  1500. }
  1501. #if 0
  1502. /* Set 1000BaseT Master/Slave setting */
  1503. mscr.image = mii_read (dev, phy_addr, MII_MSCR);
  1504. mscr.bits.cfg_enable = 1;
  1505. mscr.bits.cfg_value = 0;
  1506. #endif
  1507. mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
  1508. mdelay(10);
  1509. }
  1510. return 0;
  1511. }
  1512. static int
  1513. mii_get_media_pcs (struct net_device *dev)
  1514. {
  1515. ANAR_PCS_t negotiate;
  1516. BMSR_t bmsr;
  1517. BMCR_t bmcr;
  1518. int phy_addr;
  1519. struct netdev_private *np;
  1520. np = netdev_priv(dev);
  1521. phy_addr = np->phy_addr;
  1522. bmsr.image = mii_read (dev, phy_addr, PCS_BMSR);
  1523. if (np->an_enable) {
  1524. if (!bmsr.bits.an_complete) {
  1525. /* Auto-Negotiation not completed */
  1526. return -1;
  1527. }
  1528. negotiate.image = mii_read (dev, phy_addr, PCS_ANAR) &
  1529. mii_read (dev, phy_addr, PCS_ANLPAR);
  1530. np->speed = 1000;
  1531. if (negotiate.bits.full_duplex) {
  1532. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1533. np->full_duplex = 1;
  1534. } else {
  1535. printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
  1536. np->full_duplex = 0;
  1537. }
  1538. if (negotiate.bits.pause) {
  1539. np->tx_flow &= 1;
  1540. np->rx_flow &= 1;
  1541. } else if (negotiate.bits.asymmetric) {
  1542. np->tx_flow = 0;
  1543. np->rx_flow &= 1;
  1544. }
  1545. /* else tx_flow, rx_flow = user select */
  1546. } else {
  1547. bmcr.image = mii_read (dev, phy_addr, PCS_BMCR);
  1548. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1549. if (bmcr.bits.duplex_mode) {
  1550. printk ("Full duplex\n");
  1551. } else {
  1552. printk ("Half duplex\n");
  1553. }
  1554. }
  1555. if (np->tx_flow)
  1556. printk(KERN_INFO "Enable Tx Flow Control\n");
  1557. else
  1558. printk(KERN_INFO "Disable Tx Flow Control\n");
  1559. if (np->rx_flow)
  1560. printk(KERN_INFO "Enable Rx Flow Control\n");
  1561. else
  1562. printk(KERN_INFO "Disable Rx Flow Control\n");
  1563. return 0;
  1564. }
  1565. static int
  1566. mii_set_media_pcs (struct net_device *dev)
  1567. {
  1568. BMCR_t bmcr;
  1569. ESR_t esr;
  1570. ANAR_PCS_t anar;
  1571. int phy_addr;
  1572. struct netdev_private *np;
  1573. np = netdev_priv(dev);
  1574. phy_addr = np->phy_addr;
  1575. /* Auto-Negotiation? */
  1576. if (np->an_enable) {
  1577. /* Advertise capabilities */
  1578. esr.image = mii_read (dev, phy_addr, PCS_ESR);
  1579. anar.image = mii_read (dev, phy_addr, MII_ANAR);
  1580. anar.bits.half_duplex =
  1581. esr.bits.media_1000BT_HD | esr.bits.media_1000BX_HD;
  1582. anar.bits.full_duplex =
  1583. esr.bits.media_1000BT_FD | esr.bits.media_1000BX_FD;
  1584. anar.bits.pause = 1;
  1585. anar.bits.asymmetric = 1;
  1586. mii_write (dev, phy_addr, MII_ANAR, anar.image);
  1587. /* Soft reset PHY */
  1588. mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
  1589. bmcr.image = 0;
  1590. bmcr.bits.an_enable = 1;
  1591. bmcr.bits.restart_an = 1;
  1592. bmcr.bits.reset = 1;
  1593. mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
  1594. mdelay(1);
  1595. } else {
  1596. /* Force speed setting */
  1597. /* PHY Reset */
  1598. bmcr.image = 0;
  1599. bmcr.bits.reset = 1;
  1600. mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
  1601. mdelay(10);
  1602. bmcr.image = 0;
  1603. bmcr.bits.an_enable = 0;
  1604. if (np->full_duplex) {
  1605. bmcr.bits.duplex_mode = 1;
  1606. printk (KERN_INFO "Manual full duplex\n");
  1607. } else {
  1608. bmcr.bits.duplex_mode = 0;
  1609. printk (KERN_INFO "Manual half duplex\n");
  1610. }
  1611. mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
  1612. mdelay(10);
  1613. /* Advertise nothing */
  1614. mii_write (dev, phy_addr, MII_ANAR, 0);
  1615. }
  1616. return 0;
  1617. }
  1618. static int
  1619. rio_close (struct net_device *dev)
  1620. {
  1621. long ioaddr = dev->base_addr;
  1622. struct netdev_private *np = netdev_priv(dev);
  1623. struct sk_buff *skb;
  1624. int i;
  1625. netif_stop_queue (dev);
  1626. /* Disable interrupts */
  1627. writew (0, ioaddr + IntEnable);
  1628. /* Stop Tx and Rx logics */
  1629. writel (TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl);
  1630. synchronize_irq (dev->irq);
  1631. free_irq (dev->irq, dev);
  1632. del_timer_sync (&np->timer);
  1633. /* Free all the skbuffs in the queue. */
  1634. for (i = 0; i < RX_RING_SIZE; i++) {
  1635. np->rx_ring[i].status = 0;
  1636. np->rx_ring[i].fraginfo = 0;
  1637. skb = np->rx_skbuff[i];
  1638. if (skb) {
  1639. pci_unmap_single(np->pdev,
  1640. np->rx_ring[i].fraginfo & DMA_48BIT_MASK,
  1641. skb->len, PCI_DMA_FROMDEVICE);
  1642. dev_kfree_skb (skb);
  1643. np->rx_skbuff[i] = NULL;
  1644. }
  1645. }
  1646. for (i = 0; i < TX_RING_SIZE; i++) {
  1647. skb = np->tx_skbuff[i];
  1648. if (skb) {
  1649. pci_unmap_single(np->pdev,
  1650. np->tx_ring[i].fraginfo & DMA_48BIT_MASK,
  1651. skb->len, PCI_DMA_TODEVICE);
  1652. dev_kfree_skb (skb);
  1653. np->tx_skbuff[i] = NULL;
  1654. }
  1655. }
  1656. return 0;
  1657. }
  1658. static void __devexit
  1659. rio_remove1 (struct pci_dev *pdev)
  1660. {
  1661. struct net_device *dev = pci_get_drvdata (pdev);
  1662. if (dev) {
  1663. struct netdev_private *np = netdev_priv(dev);
  1664. unregister_netdev (dev);
  1665. pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
  1666. np->rx_ring_dma);
  1667. pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
  1668. np->tx_ring_dma);
  1669. #ifdef MEM_MAPPING
  1670. iounmap ((char *) (dev->base_addr));
  1671. #endif
  1672. free_netdev (dev);
  1673. pci_release_regions (pdev);
  1674. pci_disable_device (pdev);
  1675. }
  1676. pci_set_drvdata (pdev, NULL);
  1677. }
  1678. static struct pci_driver rio_driver = {
  1679. .name = "dl2k",
  1680. .id_table = rio_pci_tbl,
  1681. .probe = rio_probe1,
  1682. .remove = __devexit_p(rio_remove1),
  1683. };
  1684. static int __init
  1685. rio_init (void)
  1686. {
  1687. return pci_module_init (&rio_driver);
  1688. }
  1689. static void __exit
  1690. rio_exit (void)
  1691. {
  1692. pci_unregister_driver (&rio_driver);
  1693. }
  1694. module_init (rio_init);
  1695. module_exit (rio_exit);
  1696. /*
  1697. Compile command:
  1698. gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c
  1699. Read Documentation/networking/dl2k.txt for details.
  1700. */