irq.c 7.1 KB

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  1. /*
  2. * linux/arch/arm/mach-sa1100/irq.c
  3. *
  4. * Copyright (C) 1999-2001 Nicolas Pitre
  5. *
  6. * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/ioport.h>
  15. #include <linux/ptrace.h>
  16. #include <linux/sysdev.h>
  17. #include <asm/hardware.h>
  18. #include <asm/irq.h>
  19. #include <asm/mach/irq.h>
  20. #include "generic.h"
  21. /*
  22. * SA1100 GPIO edge detection for IRQs:
  23. * IRQs are generated on Falling-Edge, Rising-Edge, or both.
  24. * Use this instead of directly setting GRER/GFER.
  25. */
  26. static int GPIO_IRQ_rising_edge;
  27. static int GPIO_IRQ_falling_edge;
  28. static int GPIO_IRQ_mask = (1 << 11) - 1;
  29. /*
  30. * To get the GPIO number from an IRQ number
  31. */
  32. #define GPIO_11_27_IRQ(i) ((i) - 21)
  33. #define GPIO11_27_MASK(irq) (1 << GPIO_11_27_IRQ(irq))
  34. static int sa1100_gpio_type(unsigned int irq, unsigned int type)
  35. {
  36. unsigned int mask;
  37. if (irq <= 10)
  38. mask = 1 << irq;
  39. else
  40. mask = GPIO11_27_MASK(irq);
  41. if (type == IRQT_PROBE) {
  42. if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
  43. return 0;
  44. type = __IRQT_RISEDGE | __IRQT_FALEDGE;
  45. }
  46. if (type & __IRQT_RISEDGE) {
  47. GPIO_IRQ_rising_edge |= mask;
  48. } else
  49. GPIO_IRQ_rising_edge &= ~mask;
  50. if (type & __IRQT_FALEDGE) {
  51. GPIO_IRQ_falling_edge |= mask;
  52. } else
  53. GPIO_IRQ_falling_edge &= ~mask;
  54. GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
  55. GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
  56. return 0;
  57. }
  58. /*
  59. * GPIO IRQs must be acknowledged. This is for IRQs from 0 to 10.
  60. */
  61. static void sa1100_low_gpio_ack(unsigned int irq)
  62. {
  63. GEDR = (1 << irq);
  64. }
  65. static void sa1100_low_gpio_mask(unsigned int irq)
  66. {
  67. ICMR &= ~(1 << irq);
  68. }
  69. static void sa1100_low_gpio_unmask(unsigned int irq)
  70. {
  71. ICMR |= 1 << irq;
  72. }
  73. static int sa1100_low_gpio_wake(unsigned int irq, unsigned int on)
  74. {
  75. if (on)
  76. PWER |= 1 << irq;
  77. else
  78. PWER &= ~(1 << irq);
  79. return 0;
  80. }
  81. static struct irqchip sa1100_low_gpio_chip = {
  82. .ack = sa1100_low_gpio_ack,
  83. .mask = sa1100_low_gpio_mask,
  84. .unmask = sa1100_low_gpio_unmask,
  85. .set_type = sa1100_gpio_type,
  86. .set_wake = sa1100_low_gpio_wake,
  87. };
  88. /*
  89. * IRQ11 (GPIO11 through 27) handler. We enter here with the
  90. * irq_controller_lock held, and IRQs disabled. Decode the IRQ
  91. * and call the handler.
  92. */
  93. static void
  94. sa1100_high_gpio_handler(unsigned int irq, struct irqdesc *desc,
  95. struct pt_regs *regs)
  96. {
  97. unsigned int mask;
  98. mask = GEDR & 0xfffff800;
  99. do {
  100. /*
  101. * clear down all currently active IRQ sources.
  102. * We will be processing them all.
  103. */
  104. GEDR = mask;
  105. irq = IRQ_GPIO11;
  106. desc = irq_desc + irq;
  107. mask >>= 11;
  108. do {
  109. if (mask & 1)
  110. desc_handle_irq(irq, desc, regs);
  111. mask >>= 1;
  112. irq++;
  113. desc++;
  114. } while (mask);
  115. mask = GEDR & 0xfffff800;
  116. } while (mask);
  117. }
  118. /*
  119. * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
  120. * In addition, the IRQs are all collected up into one bit in the
  121. * interrupt controller registers.
  122. */
  123. static void sa1100_high_gpio_ack(unsigned int irq)
  124. {
  125. unsigned int mask = GPIO11_27_MASK(irq);
  126. GEDR = mask;
  127. }
  128. static void sa1100_high_gpio_mask(unsigned int irq)
  129. {
  130. unsigned int mask = GPIO11_27_MASK(irq);
  131. GPIO_IRQ_mask &= ~mask;
  132. GRER &= ~mask;
  133. GFER &= ~mask;
  134. }
  135. static void sa1100_high_gpio_unmask(unsigned int irq)
  136. {
  137. unsigned int mask = GPIO11_27_MASK(irq);
  138. GPIO_IRQ_mask |= mask;
  139. GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
  140. GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
  141. }
  142. static int sa1100_high_gpio_wake(unsigned int irq, unsigned int on)
  143. {
  144. if (on)
  145. PWER |= GPIO11_27_MASK(irq);
  146. else
  147. PWER &= ~GPIO11_27_MASK(irq);
  148. return 0;
  149. }
  150. static struct irqchip sa1100_high_gpio_chip = {
  151. .ack = sa1100_high_gpio_ack,
  152. .mask = sa1100_high_gpio_mask,
  153. .unmask = sa1100_high_gpio_unmask,
  154. .set_type = sa1100_gpio_type,
  155. .set_wake = sa1100_high_gpio_wake,
  156. };
  157. /*
  158. * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
  159. * this is for internal IRQs i.e. from 11 to 31.
  160. */
  161. static void sa1100_mask_irq(unsigned int irq)
  162. {
  163. ICMR &= ~(1 << irq);
  164. }
  165. static void sa1100_unmask_irq(unsigned int irq)
  166. {
  167. ICMR |= (1 << irq);
  168. }
  169. /*
  170. * Apart form GPIOs, only the RTC alarm can be a wakeup event.
  171. */
  172. static int sa1100_set_wake(unsigned int irq, unsigned int on)
  173. {
  174. if (irq == IRQ_RTCAlrm) {
  175. if (on)
  176. PWER |= PWER_RTC;
  177. else
  178. PWER &= ~PWER_RTC;
  179. return 0;
  180. }
  181. return -EINVAL;
  182. }
  183. static struct irqchip sa1100_normal_chip = {
  184. .ack = sa1100_mask_irq,
  185. .mask = sa1100_mask_irq,
  186. .unmask = sa1100_unmask_irq,
  187. .set_wake = sa1100_set_wake,
  188. };
  189. static struct resource irq_resource = {
  190. .name = "irqs",
  191. .start = 0x90050000,
  192. .end = 0x9005ffff,
  193. };
  194. static struct sa1100irq_state {
  195. unsigned int saved;
  196. unsigned int icmr;
  197. unsigned int iclr;
  198. unsigned int iccr;
  199. } sa1100irq_state;
  200. static int sa1100irq_suspend(struct sys_device *dev, pm_message_t state)
  201. {
  202. struct sa1100irq_state *st = &sa1100irq_state;
  203. st->saved = 1;
  204. st->icmr = ICMR;
  205. st->iclr = ICLR;
  206. st->iccr = ICCR;
  207. /*
  208. * Disable all GPIO-based interrupts.
  209. */
  210. ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7|
  211. IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
  212. IC_GPIO1|IC_GPIO0);
  213. /*
  214. * Set the appropriate edges for wakeup.
  215. */
  216. GRER = PWER & GPIO_IRQ_rising_edge;
  217. GFER = PWER & GPIO_IRQ_falling_edge;
  218. /*
  219. * Clear any pending GPIO interrupts.
  220. */
  221. GEDR = GEDR;
  222. return 0;
  223. }
  224. static int sa1100irq_resume(struct sys_device *dev)
  225. {
  226. struct sa1100irq_state *st = &sa1100irq_state;
  227. if (st->saved) {
  228. ICCR = st->iccr;
  229. ICLR = st->iclr;
  230. GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
  231. GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
  232. ICMR = st->icmr;
  233. }
  234. return 0;
  235. }
  236. static struct sysdev_class sa1100irq_sysclass = {
  237. set_kset_name("sa11x0-irq"),
  238. .suspend = sa1100irq_suspend,
  239. .resume = sa1100irq_resume,
  240. };
  241. static struct sys_device sa1100irq_device = {
  242. .id = 0,
  243. .cls = &sa1100irq_sysclass,
  244. };
  245. static int __init sa1100irq_init_devicefs(void)
  246. {
  247. sysdev_class_register(&sa1100irq_sysclass);
  248. return sysdev_register(&sa1100irq_device);
  249. }
  250. device_initcall(sa1100irq_init_devicefs);
  251. void __init sa1100_init_irq(void)
  252. {
  253. unsigned int irq;
  254. request_resource(&iomem_resource, &irq_resource);
  255. /* disable all IRQs */
  256. ICMR = 0;
  257. /* all IRQs are IRQ, not FIQ */
  258. ICLR = 0;
  259. /* clear all GPIO edge detects */
  260. GFER = 0;
  261. GRER = 0;
  262. GEDR = -1;
  263. /*
  264. * Whatever the doc says, this has to be set for the wait-on-irq
  265. * instruction to work... on a SA1100 rev 9 at least.
  266. */
  267. ICCR = 1;
  268. for (irq = 0; irq <= 10; irq++) {
  269. set_irq_chip(irq, &sa1100_low_gpio_chip);
  270. set_irq_handler(irq, do_edge_IRQ);
  271. set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
  272. }
  273. for (irq = 12; irq <= 31; irq++) {
  274. set_irq_chip(irq, &sa1100_normal_chip);
  275. set_irq_handler(irq, do_level_IRQ);
  276. set_irq_flags(irq, IRQF_VALID);
  277. }
  278. for (irq = 32; irq <= 48; irq++) {
  279. set_irq_chip(irq, &sa1100_high_gpio_chip);
  280. set_irq_handler(irq, do_edge_IRQ);
  281. set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
  282. }
  283. /*
  284. * Install handler for GPIO 11-27 edge detect interrupts
  285. */
  286. set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
  287. set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
  288. }