sleep.S 4.8 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/sleep.S
  3. *
  4. * (C) Copyright 2004
  5. * Texas Instruments, <www.ti.com>
  6. * Richard Woodruff <r-woodruff2@ti.com>
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <linux/config.h>
  24. #include <linux/linkage.h>
  25. #include <asm/assembler.h>
  26. #include <asm/arch/io.h>
  27. #include <asm/arch/pm.h>
  28. #define A_32KSYNC_CR_V IO_ADDRESS(OMAP_TIMER32K_BASE+0x10)
  29. #define A_PRCM_VOLTCTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x50)
  30. #define A_PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x80)
  31. #define A_CM_CLKEN_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x500)
  32. #define A_CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x520)
  33. #define A_CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x540)
  34. #define A_CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x544)
  35. #define A_SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0x60)
  36. #define A_SDRC_POWER_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0x70)
  37. #define A_SDRC_RFR_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA4)
  38. #define A_SDRC0_V (0xC0000000)
  39. #define A_SDRC_MANUAL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA8)
  40. .text
  41. /*
  42. * Forces OMAP into idle state
  43. *
  44. * omap24xx_idle_loop_suspend() - This bit of code just executes the WFI
  45. * for normal idles.
  46. *
  47. * Note: This code get's copied to internal SRAM at boot. When the OMAP
  48. * wakes up it continues execution at the point it went to sleep.
  49. */
  50. ENTRY(omap24xx_idle_loop_suspend)
  51. stmfd sp!, {r0, lr} @ save registers on stack
  52. mov r0, #0 @ clear for mcr setup
  53. mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
  54. ldmfd sp!, {r0, pc} @ restore regs and return
  55. ENTRY(omap24xx_idle_loop_suspend_sz)
  56. .word . - omap24xx_idle_loop_suspend
  57. /*
  58. * omap242x_cpu_suspend() - Forces OMAP into deep sleep state by completing
  59. * SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore
  60. * SDRC.
  61. *
  62. * Input:
  63. * R0 : DLL ctrl value pre-Sleep
  64. * R1 : Processor+Revision
  65. * 2420: 0x21 = 242xES1, 0x26 = 242xES2.2
  66. * 2430: 0x31 = 2430ES1, 0x32 = 2430ES2
  67. *
  68. * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
  69. * when we get called, but the DLL probably isn't. We will wait a bit more in
  70. * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
  71. * if in unlocked mode.
  72. *
  73. * For less than 242x-ES2.2 upon wake from a sleep mode where the external
  74. * oscillator was stopped, a timing bug exists where a non-stabilized 12MHz
  75. * clock can pass into the PRCM can cause problems at DSP and IVA.
  76. * To work around this the code will switch to the 32kHz source prior to sleep.
  77. * Post sleep we will shift back to using the DPLL. Apparently,
  78. * CM_IDLEST_CLKGEN does not reflect the full clock change so you need to wait
  79. * 3x12MHz + 3x32kHz clocks for a full switch.
  80. *
  81. * The DLL load value is not kept in RETENTION or OFF. It needs to be restored
  82. * at wake
  83. */
  84. ENTRY(omap24xx_cpu_suspend)
  85. stmfd sp!, {r0 - r12, lr} @ save registers on stack
  86. mov r3, #0x0 @ clear for mrc call
  87. mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
  88. nop
  89. nop
  90. ldr r3, A_SDRC_POWER @ addr of sdrc power
  91. ldr r4, [r3] @ value of sdrc power
  92. orr r4, r4, #0x40 @ enable self refresh on idle req
  93. mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
  94. str r4, [r3] @ make it so
  95. mov r2, #0
  96. nop
  97. mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
  98. nop
  99. loop:
  100. subs r5, r5, #0x1 @ awake, wait just a bit
  101. bne loop
  102. /* The DPLL has on before we take the DDR out of self refresh */
  103. bic r4, r4, #0x40 @ now clear self refresh bit.
  104. str r4, [r3] @ put vlaue back.
  105. ldr r4, A_SDRC0 @ make a clock happen
  106. ldr r4, [r4]
  107. nop @ start auto refresh only after clk ok
  108. movs r0, r0 @ see if DDR or SDR
  109. ldrne r1, A_SDRC_DLLA_CTRL_S @ get addr of DLL ctrl
  110. strne r0, [r1] @ rewrite DLLA to force DLL reload
  111. addne r1, r1, #0x8 @ move to DLLB
  112. strne r0, [r1] @ rewrite DLLB to force DLL reload
  113. mov r5, #0x1000
  114. loop2:
  115. subs r5, r5, #0x1
  116. bne loop2
  117. /* resume*/
  118. ldmfd sp!, {r0 - r12, pc} @ restore regs and return
  119. A_SDRC_POWER:
  120. .word A_SDRC_POWER_V
  121. A_SDRC0:
  122. .word A_SDRC0_V
  123. A_CM_CLKSEL2_PLL_S:
  124. .word A_CM_CLKSEL2_PLL_V
  125. A_CM_CLKEN_PLL:
  126. .word A_CM_CLKEN_PLL_V
  127. A_SDRC_DLLA_CTRL_S:
  128. .word A_SDRC_DLLA_CTRL_V
  129. A_SDRC_MANUAL_S:
  130. .word A_SDRC_MANUAL_V
  131. ENTRY(omap24xx_cpu_suspend_sz)
  132. .word . - omap24xx_cpu_suspend