mce_amd_64.c 15 KB

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  1. /*
  2. * (c) 2005, 2006 Advanced Micro Devices, Inc.
  3. * Your use of this code is subject to the terms and conditions of the
  4. * GNU general public license version 2. See "COPYING" or
  5. * http://www.gnu.org/licenses/gpl.html
  6. *
  7. * Written by Jacob Shin - AMD, Inc.
  8. *
  9. * Support : jacob.shin@amd.com
  10. *
  11. * April 2006
  12. * - added support for AMD Family 0x10 processors
  13. *
  14. * All MC4_MISCi registers are shared between multi-cores
  15. */
  16. #include <linux/cpu.h>
  17. #include <linux/errno.h>
  18. #include <linux/init.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/kobject.h>
  21. #include <linux/notifier.h>
  22. #include <linux/sched.h>
  23. #include <linux/smp.h>
  24. #include <linux/sysdev.h>
  25. #include <linux/sysfs.h>
  26. #include <asm/apic.h>
  27. #include <asm/mce.h>
  28. #include <asm/msr.h>
  29. #include <asm/percpu.h>
  30. #include <asm/idle.h>
  31. #define PFX "mce_threshold: "
  32. #define VERSION "version 1.1.1"
  33. #define NR_BANKS 6
  34. #define NR_BLOCKS 9
  35. #define THRESHOLD_MAX 0xFFF
  36. #define INT_TYPE_APIC 0x00020000
  37. #define MASK_VALID_HI 0x80000000
  38. #define MASK_CNTP_HI 0x40000000
  39. #define MASK_LOCKED_HI 0x20000000
  40. #define MASK_LVTOFF_HI 0x00F00000
  41. #define MASK_COUNT_EN_HI 0x00080000
  42. #define MASK_INT_TYPE_HI 0x00060000
  43. #define MASK_OVERFLOW_HI 0x00010000
  44. #define MASK_ERR_COUNT_HI 0x00000FFF
  45. #define MASK_BLKPTR_LO 0xFF000000
  46. #define MCG_XBLK_ADDR 0xC0000400
  47. struct threshold_block {
  48. unsigned int block;
  49. unsigned int bank;
  50. unsigned int cpu;
  51. u32 address;
  52. u16 interrupt_enable;
  53. u16 threshold_limit;
  54. struct kobject kobj;
  55. struct list_head miscj;
  56. };
  57. /* defaults used early on boot */
  58. static struct threshold_block threshold_defaults = {
  59. .interrupt_enable = 0,
  60. .threshold_limit = THRESHOLD_MAX,
  61. };
  62. struct threshold_bank {
  63. struct kobject *kobj;
  64. struct threshold_block *blocks;
  65. cpumask_t cpus;
  66. };
  67. static DEFINE_PER_CPU(struct threshold_bank *, threshold_banks[NR_BANKS]);
  68. #ifdef CONFIG_SMP
  69. static unsigned char shared_bank[NR_BANKS] = {
  70. 0, 0, 0, 0, 1
  71. };
  72. #endif
  73. static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
  74. /*
  75. * CPU Initialization
  76. */
  77. struct thresh_restart {
  78. struct threshold_block *b;
  79. int reset;
  80. u16 old_limit;
  81. };
  82. /* must be called with correct cpu affinity */
  83. static long threshold_restart_bank(void *_tr)
  84. {
  85. struct thresh_restart *tr = _tr;
  86. u32 mci_misc_hi, mci_misc_lo;
  87. rdmsr(tr->b->address, mci_misc_lo, mci_misc_hi);
  88. if (tr->b->threshold_limit < (mci_misc_hi & THRESHOLD_MAX))
  89. tr->reset = 1; /* limit cannot be lower than err count */
  90. if (tr->reset) { /* reset err count and overflow bit */
  91. mci_misc_hi =
  92. (mci_misc_hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
  93. (THRESHOLD_MAX - tr->b->threshold_limit);
  94. } else if (tr->old_limit) { /* change limit w/o reset */
  95. int new_count = (mci_misc_hi & THRESHOLD_MAX) +
  96. (tr->old_limit - tr->b->threshold_limit);
  97. mci_misc_hi = (mci_misc_hi & ~MASK_ERR_COUNT_HI) |
  98. (new_count & THRESHOLD_MAX);
  99. }
  100. tr->b->interrupt_enable ?
  101. (mci_misc_hi = (mci_misc_hi & ~MASK_INT_TYPE_HI) | INT_TYPE_APIC) :
  102. (mci_misc_hi &= ~MASK_INT_TYPE_HI);
  103. mci_misc_hi |= MASK_COUNT_EN_HI;
  104. wrmsr(tr->b->address, mci_misc_lo, mci_misc_hi);
  105. return 0;
  106. }
  107. /* cpu init entry point, called from mce.c with preempt off */
  108. void __cpuinit mce_amd_feature_init(struct cpuinfo_x86 *c)
  109. {
  110. unsigned int bank, block;
  111. unsigned int cpu = smp_processor_id();
  112. u8 lvt_off;
  113. u32 low = 0, high = 0, address = 0;
  114. struct thresh_restart tr;
  115. for (bank = 0; bank < NR_BANKS; ++bank) {
  116. for (block = 0; block < NR_BLOCKS; ++block) {
  117. if (block == 0)
  118. address = MSR_IA32_MC0_MISC + bank * 4;
  119. else if (block == 1) {
  120. address = (low & MASK_BLKPTR_LO) >> 21;
  121. if (!address)
  122. break;
  123. address += MCG_XBLK_ADDR;
  124. }
  125. else
  126. ++address;
  127. if (rdmsr_safe(address, &low, &high))
  128. break;
  129. if (!(high & MASK_VALID_HI)) {
  130. if (block)
  131. continue;
  132. else
  133. break;
  134. }
  135. if (!(high & MASK_CNTP_HI) ||
  136. (high & MASK_LOCKED_HI))
  137. continue;
  138. if (!block)
  139. per_cpu(bank_map, cpu) |= (1 << bank);
  140. #ifdef CONFIG_SMP
  141. if (shared_bank[bank] && c->cpu_core_id)
  142. break;
  143. #endif
  144. lvt_off = setup_APIC_eilvt_mce(THRESHOLD_APIC_VECTOR,
  145. APIC_EILVT_MSG_FIX, 0);
  146. high &= ~MASK_LVTOFF_HI;
  147. high |= lvt_off << 20;
  148. wrmsr(address, low, high);
  149. threshold_defaults.address = address;
  150. tr.b = &threshold_defaults;
  151. tr.reset = 0;
  152. tr.old_limit = 0;
  153. threshold_restart_bank(&tr);
  154. }
  155. }
  156. }
  157. /*
  158. * APIC Interrupt Handler
  159. */
  160. /*
  161. * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
  162. * the interrupt goes off when error_count reaches threshold_limit.
  163. * the handler will simply log mcelog w/ software defined bank number.
  164. */
  165. asmlinkage void mce_threshold_interrupt(void)
  166. {
  167. unsigned int bank, block;
  168. struct mce m;
  169. u32 low = 0, high = 0, address = 0;
  170. ack_APIC_irq();
  171. exit_idle();
  172. irq_enter();
  173. memset(&m, 0, sizeof(m));
  174. rdtscll(m.tsc);
  175. m.cpu = smp_processor_id();
  176. /* assume first bank caused it */
  177. for (bank = 0; bank < NR_BANKS; ++bank) {
  178. if (!(per_cpu(bank_map, m.cpu) & (1 << bank)))
  179. continue;
  180. for (block = 0; block < NR_BLOCKS; ++block) {
  181. if (block == 0)
  182. address = MSR_IA32_MC0_MISC + bank * 4;
  183. else if (block == 1) {
  184. address = (low & MASK_BLKPTR_LO) >> 21;
  185. if (!address)
  186. break;
  187. address += MCG_XBLK_ADDR;
  188. }
  189. else
  190. ++address;
  191. if (rdmsr_safe(address, &low, &high))
  192. break;
  193. if (!(high & MASK_VALID_HI)) {
  194. if (block)
  195. continue;
  196. else
  197. break;
  198. }
  199. if (!(high & MASK_CNTP_HI) ||
  200. (high & MASK_LOCKED_HI))
  201. continue;
  202. /* Log the machine check that caused the threshold
  203. event. */
  204. do_machine_check(NULL, 0);
  205. if (high & MASK_OVERFLOW_HI) {
  206. rdmsrl(address, m.misc);
  207. rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,
  208. m.status);
  209. m.bank = K8_MCE_THRESHOLD_BASE
  210. + bank * NR_BLOCKS
  211. + block;
  212. mce_log(&m);
  213. goto out;
  214. }
  215. }
  216. }
  217. out:
  218. inc_irq_stat(irq_threshold_count);
  219. irq_exit();
  220. }
  221. /*
  222. * Sysfs Interface
  223. */
  224. struct threshold_attr {
  225. struct attribute attr;
  226. ssize_t(*show) (struct threshold_block *, char *);
  227. ssize_t(*store) (struct threshold_block *, const char *, size_t count);
  228. };
  229. #define SHOW_FIELDS(name) \
  230. static ssize_t show_ ## name(struct threshold_block * b, char *buf) \
  231. { \
  232. return sprintf(buf, "%lx\n", (unsigned long) b->name); \
  233. }
  234. SHOW_FIELDS(interrupt_enable)
  235. SHOW_FIELDS(threshold_limit)
  236. static ssize_t store_interrupt_enable(struct threshold_block *b,
  237. const char *buf, size_t count)
  238. {
  239. char *end;
  240. struct thresh_restart tr;
  241. unsigned long new = simple_strtoul(buf, &end, 0);
  242. if (end == buf)
  243. return -EINVAL;
  244. b->interrupt_enable = !!new;
  245. tr.b = b;
  246. tr.reset = 0;
  247. tr.old_limit = 0;
  248. work_on_cpu(b->cpu, threshold_restart_bank, &tr);
  249. return end - buf;
  250. }
  251. static ssize_t store_threshold_limit(struct threshold_block *b,
  252. const char *buf, size_t count)
  253. {
  254. char *end;
  255. struct thresh_restart tr;
  256. unsigned long new = simple_strtoul(buf, &end, 0);
  257. if (end == buf)
  258. return -EINVAL;
  259. if (new > THRESHOLD_MAX)
  260. new = THRESHOLD_MAX;
  261. if (new < 1)
  262. new = 1;
  263. tr.old_limit = b->threshold_limit;
  264. b->threshold_limit = new;
  265. tr.b = b;
  266. tr.reset = 0;
  267. work_on_cpu(b->cpu, threshold_restart_bank, &tr);
  268. return end - buf;
  269. }
  270. static long local_error_count(void *_b)
  271. {
  272. struct threshold_block *b = _b;
  273. u32 low, high;
  274. rdmsr(b->address, low, high);
  275. return (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit);
  276. }
  277. static ssize_t show_error_count(struct threshold_block *b, char *buf)
  278. {
  279. return sprintf(buf, "%lx\n", work_on_cpu(b->cpu, local_error_count, b));
  280. }
  281. static ssize_t store_error_count(struct threshold_block *b,
  282. const char *buf, size_t count)
  283. {
  284. struct thresh_restart tr = { .b = b, .reset = 1, .old_limit = 0 };
  285. work_on_cpu(b->cpu, threshold_restart_bank, &tr);
  286. return 1;
  287. }
  288. #define THRESHOLD_ATTR(_name,_mode,_show,_store) { \
  289. .attr = {.name = __stringify(_name), .mode = _mode }, \
  290. .show = _show, \
  291. .store = _store, \
  292. };
  293. #define RW_ATTR(name) \
  294. static struct threshold_attr name = \
  295. THRESHOLD_ATTR(name, 0644, show_## name, store_## name)
  296. RW_ATTR(interrupt_enable);
  297. RW_ATTR(threshold_limit);
  298. RW_ATTR(error_count);
  299. static struct attribute *default_attrs[] = {
  300. &interrupt_enable.attr,
  301. &threshold_limit.attr,
  302. &error_count.attr,
  303. NULL
  304. };
  305. #define to_block(k) container_of(k, struct threshold_block, kobj)
  306. #define to_attr(a) container_of(a, struct threshold_attr, attr)
  307. static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
  308. {
  309. struct threshold_block *b = to_block(kobj);
  310. struct threshold_attr *a = to_attr(attr);
  311. ssize_t ret;
  312. ret = a->show ? a->show(b, buf) : -EIO;
  313. return ret;
  314. }
  315. static ssize_t store(struct kobject *kobj, struct attribute *attr,
  316. const char *buf, size_t count)
  317. {
  318. struct threshold_block *b = to_block(kobj);
  319. struct threshold_attr *a = to_attr(attr);
  320. ssize_t ret;
  321. ret = a->store ? a->store(b, buf, count) : -EIO;
  322. return ret;
  323. }
  324. static struct sysfs_ops threshold_ops = {
  325. .show = show,
  326. .store = store,
  327. };
  328. static struct kobj_type threshold_ktype = {
  329. .sysfs_ops = &threshold_ops,
  330. .default_attrs = default_attrs,
  331. };
  332. static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
  333. unsigned int bank,
  334. unsigned int block,
  335. u32 address)
  336. {
  337. int err;
  338. u32 low, high;
  339. struct threshold_block *b = NULL;
  340. if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))
  341. return 0;
  342. if (rdmsr_safe(address, &low, &high))
  343. return 0;
  344. if (!(high & MASK_VALID_HI)) {
  345. if (block)
  346. goto recurse;
  347. else
  348. return 0;
  349. }
  350. if (!(high & MASK_CNTP_HI) ||
  351. (high & MASK_LOCKED_HI))
  352. goto recurse;
  353. b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
  354. if (!b)
  355. return -ENOMEM;
  356. b->block = block;
  357. b->bank = bank;
  358. b->cpu = cpu;
  359. b->address = address;
  360. b->interrupt_enable = 0;
  361. b->threshold_limit = THRESHOLD_MAX;
  362. INIT_LIST_HEAD(&b->miscj);
  363. if (per_cpu(threshold_banks, cpu)[bank]->blocks)
  364. list_add(&b->miscj,
  365. &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
  366. else
  367. per_cpu(threshold_banks, cpu)[bank]->blocks = b;
  368. err = kobject_init_and_add(&b->kobj, &threshold_ktype,
  369. per_cpu(threshold_banks, cpu)[bank]->kobj,
  370. "misc%i", block);
  371. if (err)
  372. goto out_free;
  373. recurse:
  374. if (!block) {
  375. address = (low & MASK_BLKPTR_LO) >> 21;
  376. if (!address)
  377. return 0;
  378. address += MCG_XBLK_ADDR;
  379. } else
  380. ++address;
  381. err = allocate_threshold_blocks(cpu, bank, ++block, address);
  382. if (err)
  383. goto out_free;
  384. if (b)
  385. kobject_uevent(&b->kobj, KOBJ_ADD);
  386. return err;
  387. out_free:
  388. if (b) {
  389. kobject_put(&b->kobj);
  390. kfree(b);
  391. }
  392. return err;
  393. }
  394. static long local_allocate_threshold_blocks(void *_bank)
  395. {
  396. unsigned int *bank = _bank;
  397. return allocate_threshold_blocks(smp_processor_id(), *bank, 0,
  398. MSR_IA32_MC0_MISC + *bank * 4);
  399. }
  400. /* symlinks sibling shared banks to first core. first core owns dir/files. */
  401. static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
  402. {
  403. int i, err = 0;
  404. struct threshold_bank *b = NULL;
  405. char name[32];
  406. sprintf(name, "threshold_bank%i", bank);
  407. #ifdef CONFIG_SMP
  408. if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) { /* symlink */
  409. i = first_cpu(per_cpu(cpu_core_map, cpu));
  410. /* first core not up yet */
  411. if (cpu_data(i).cpu_core_id)
  412. goto out;
  413. /* already linked */
  414. if (per_cpu(threshold_banks, cpu)[bank])
  415. goto out;
  416. b = per_cpu(threshold_banks, i)[bank];
  417. if (!b)
  418. goto out;
  419. err = sysfs_create_link(&per_cpu(device_mce, cpu).kobj,
  420. b->kobj, name);
  421. if (err)
  422. goto out;
  423. b->cpus = per_cpu(cpu_core_map, cpu);
  424. per_cpu(threshold_banks, cpu)[bank] = b;
  425. goto out;
  426. }
  427. #endif
  428. b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
  429. if (!b) {
  430. err = -ENOMEM;
  431. goto out;
  432. }
  433. b->kobj = kobject_create_and_add(name, &per_cpu(device_mce, cpu).kobj);
  434. if (!b->kobj)
  435. goto out_free;
  436. #ifndef CONFIG_SMP
  437. b->cpus = CPU_MASK_ALL;
  438. #else
  439. b->cpus = per_cpu(cpu_core_map, cpu);
  440. #endif
  441. per_cpu(threshold_banks, cpu)[bank] = b;
  442. err = work_on_cpu(cpu, local_allocate_threshold_blocks, &bank);
  443. if (err)
  444. goto out_free;
  445. for_each_cpu_mask_nr(i, b->cpus) {
  446. if (i == cpu)
  447. continue;
  448. err = sysfs_create_link(&per_cpu(device_mce, i).kobj,
  449. b->kobj, name);
  450. if (err)
  451. goto out;
  452. per_cpu(threshold_banks, i)[bank] = b;
  453. }
  454. goto out;
  455. out_free:
  456. per_cpu(threshold_banks, cpu)[bank] = NULL;
  457. kfree(b);
  458. out:
  459. return err;
  460. }
  461. /* create dir/files for all valid threshold banks */
  462. static __cpuinit int threshold_create_device(unsigned int cpu)
  463. {
  464. unsigned int bank;
  465. int err = 0;
  466. for (bank = 0; bank < NR_BANKS; ++bank) {
  467. if (!(per_cpu(bank_map, cpu) & (1 << bank)))
  468. continue;
  469. err = threshold_create_bank(cpu, bank);
  470. if (err)
  471. goto out;
  472. }
  473. out:
  474. return err;
  475. }
  476. /*
  477. * let's be hotplug friendly.
  478. * in case of multiple core processors, the first core always takes ownership
  479. * of shared sysfs dir/files, and rest of the cores will be symlinked to it.
  480. */
  481. static void deallocate_threshold_block(unsigned int cpu,
  482. unsigned int bank)
  483. {
  484. struct threshold_block *pos = NULL;
  485. struct threshold_block *tmp = NULL;
  486. struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
  487. if (!head)
  488. return;
  489. list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
  490. kobject_put(&pos->kobj);
  491. list_del(&pos->miscj);
  492. kfree(pos);
  493. }
  494. kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
  495. per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
  496. }
  497. static void threshold_remove_bank(unsigned int cpu, int bank)
  498. {
  499. int i = 0;
  500. struct threshold_bank *b;
  501. char name[32];
  502. b = per_cpu(threshold_banks, cpu)[bank];
  503. if (!b)
  504. return;
  505. if (!b->blocks)
  506. goto free_out;
  507. sprintf(name, "threshold_bank%i", bank);
  508. #ifdef CONFIG_SMP
  509. /* sibling symlink */
  510. if (shared_bank[bank] && b->blocks->cpu != cpu) {
  511. sysfs_remove_link(&per_cpu(device_mce, cpu).kobj, name);
  512. per_cpu(threshold_banks, cpu)[bank] = NULL;
  513. return;
  514. }
  515. #endif
  516. /* remove all sibling symlinks before unregistering */
  517. for_each_cpu_mask_nr(i, b->cpus) {
  518. if (i == cpu)
  519. continue;
  520. sysfs_remove_link(&per_cpu(device_mce, i).kobj, name);
  521. per_cpu(threshold_banks, i)[bank] = NULL;
  522. }
  523. deallocate_threshold_block(cpu, bank);
  524. free_out:
  525. kobject_del(b->kobj);
  526. kobject_put(b->kobj);
  527. kfree(b);
  528. per_cpu(threshold_banks, cpu)[bank] = NULL;
  529. }
  530. static void threshold_remove_device(unsigned int cpu)
  531. {
  532. unsigned int bank;
  533. for (bank = 0; bank < NR_BANKS; ++bank) {
  534. if (!(per_cpu(bank_map, cpu) & (1 << bank)))
  535. continue;
  536. threshold_remove_bank(cpu, bank);
  537. }
  538. }
  539. /* get notified when a cpu comes on/off */
  540. static void __cpuinit amd_64_threshold_cpu_callback(unsigned long action,
  541. unsigned int cpu)
  542. {
  543. if (cpu >= NR_CPUS)
  544. return;
  545. switch (action) {
  546. case CPU_ONLINE:
  547. case CPU_ONLINE_FROZEN:
  548. threshold_create_device(cpu);
  549. break;
  550. case CPU_DEAD:
  551. case CPU_DEAD_FROZEN:
  552. threshold_remove_device(cpu);
  553. break;
  554. default:
  555. break;
  556. }
  557. }
  558. static __init int threshold_init_device(void)
  559. {
  560. unsigned lcpu = 0;
  561. /* to hit CPUs online before the notifier is up */
  562. for_each_online_cpu(lcpu) {
  563. int err = threshold_create_device(lcpu);
  564. if (err)
  565. return err;
  566. }
  567. threshold_cpu_callback = amd_64_threshold_cpu_callback;
  568. return 0;
  569. }
  570. device_initcall(threshold_init_device);