mmu_context_32.h 1.4 KB

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  1. #ifndef _ASM_X86_MMU_CONTEXT_32_H
  2. #define _ASM_X86_MMU_CONTEXT_32_H
  3. static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
  4. {
  5. #ifdef CONFIG_SMP
  6. if (x86_read_percpu(cpu_tlbstate.state) == TLBSTATE_OK)
  7. x86_write_percpu(cpu_tlbstate.state, TLBSTATE_LAZY);
  8. #endif
  9. }
  10. static inline void switch_mm(struct mm_struct *prev,
  11. struct mm_struct *next,
  12. struct task_struct *tsk)
  13. {
  14. int cpu = smp_processor_id();
  15. if (likely(prev != next)) {
  16. /* stop flush ipis for the previous mm */
  17. cpu_clear(cpu, prev->cpu_vm_mask);
  18. #ifdef CONFIG_SMP
  19. x86_write_percpu(cpu_tlbstate.state, TLBSTATE_OK);
  20. x86_write_percpu(cpu_tlbstate.active_mm, next);
  21. #endif
  22. cpu_set(cpu, next->cpu_vm_mask);
  23. /* Re-load page tables */
  24. load_cr3(next->pgd);
  25. /*
  26. * load the LDT, if the LDT is different:
  27. */
  28. if (unlikely(prev->context.ldt != next->context.ldt))
  29. load_LDT_nolock(&next->context);
  30. }
  31. #ifdef CONFIG_SMP
  32. else {
  33. x86_write_percpu(cpu_tlbstate.state, TLBSTATE_OK);
  34. BUG_ON(x86_read_percpu(cpu_tlbstate.active_mm) != next);
  35. if (!cpu_test_and_set(cpu, next->cpu_vm_mask)) {
  36. /* We were in lazy tlb mode and leave_mm disabled
  37. * tlb flush IPI delivery. We must reload %cr3.
  38. */
  39. load_cr3(next->pgd);
  40. load_LDT_nolock(&next->context);
  41. }
  42. }
  43. #endif
  44. }
  45. #define deactivate_mm(tsk, mm) \
  46. asm("movl %0,%%gs": :"r" (0));
  47. #endif /* _ASM_X86_MMU_CONTEXT_32_H */