sbc8349.dts 6.7 KB

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  1. /*
  2. * SBC8349E Device Tree Source
  3. *
  4. * Copyright 2007 Wind River Inc.
  5. *
  6. * Paul Gortmaker (see MAINTAINERS for contact information)
  7. *
  8. * -based largely on the Freescale MPC834x_MDS dts.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. */
  15. /dts-v1/;
  16. / {
  17. model = "SBC8349E";
  18. compatible = "SBC834xE";
  19. #address-cells = <1>;
  20. #size-cells = <1>;
  21. aliases {
  22. ethernet0 = &enet0;
  23. ethernet1 = &enet1;
  24. serial0 = &serial0;
  25. serial1 = &serial1;
  26. pci0 = &pci0;
  27. };
  28. cpus {
  29. #address-cells = <1>;
  30. #size-cells = <0>;
  31. PowerPC,8349@0 {
  32. device_type = "cpu";
  33. reg = <0x0>;
  34. d-cache-line-size = <32>;
  35. i-cache-line-size = <32>;
  36. d-cache-size = <32768>;
  37. i-cache-size = <32768>;
  38. timebase-frequency = <0>; // from bootloader
  39. bus-frequency = <0>; // from bootloader
  40. clock-frequency = <0>; // from bootloader
  41. };
  42. };
  43. memory {
  44. device_type = "memory";
  45. reg = <0x00000000 0x10000000>; // 256MB at 0
  46. };
  47. soc8349@e0000000 {
  48. #address-cells = <1>;
  49. #size-cells = <1>;
  50. device_type = "soc";
  51. ranges = <0x0 0xe0000000 0x00100000>;
  52. reg = <0xe0000000 0x00000200>;
  53. bus-frequency = <0>;
  54. wdt@200 {
  55. compatible = "mpc83xx_wdt";
  56. reg = <0x200 0x100>;
  57. };
  58. i2c@3000 {
  59. #address-cells = <1>;
  60. #size-cells = <0>;
  61. cell-index = <0>;
  62. compatible = "fsl-i2c";
  63. reg = <0x3000 0x100>;
  64. interrupts = <14 0x8>;
  65. interrupt-parent = <&ipic>;
  66. dfsrr;
  67. };
  68. i2c@3100 {
  69. #address-cells = <1>;
  70. #size-cells = <0>;
  71. cell-index = <1>;
  72. compatible = "fsl-i2c";
  73. reg = <0x3100 0x100>;
  74. interrupts = <15 0x8>;
  75. interrupt-parent = <&ipic>;
  76. dfsrr;
  77. };
  78. spi@7000 {
  79. cell-index = <0>;
  80. compatible = "fsl,spi";
  81. reg = <0x7000 0x1000>;
  82. interrupts = <16 0x8>;
  83. interrupt-parent = <&ipic>;
  84. mode = "cpu";
  85. };
  86. dma@82a8 {
  87. #address-cells = <1>;
  88. #size-cells = <1>;
  89. compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
  90. reg = <0x82a8 4>;
  91. ranges = <0 0x8100 0x1a8>;
  92. interrupt-parent = <&ipic>;
  93. interrupts = <71 8>;
  94. cell-index = <0>;
  95. dma-channel@0 {
  96. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  97. reg = <0 0x80>;
  98. cell-index = <0>;
  99. interrupt-parent = <&ipic>;
  100. interrupts = <71 8>;
  101. };
  102. dma-channel@80 {
  103. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  104. reg = <0x80 0x80>;
  105. cell-index = <1>;
  106. interrupt-parent = <&ipic>;
  107. interrupts = <71 8>;
  108. };
  109. dma-channel@100 {
  110. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  111. reg = <0x100 0x80>;
  112. cell-index = <2>;
  113. interrupt-parent = <&ipic>;
  114. interrupts = <71 8>;
  115. };
  116. dma-channel@180 {
  117. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  118. reg = <0x180 0x28>;
  119. cell-index = <3>;
  120. interrupt-parent = <&ipic>;
  121. interrupts = <71 8>;
  122. };
  123. };
  124. /* phy type (ULPI or SERIAL) are only types supported for MPH */
  125. /* port = 0 or 1 */
  126. usb@22000 {
  127. compatible = "fsl-usb2-mph";
  128. reg = <0x22000 0x1000>;
  129. #address-cells = <1>;
  130. #size-cells = <0>;
  131. interrupt-parent = <&ipic>;
  132. interrupts = <39 0x8>;
  133. phy_type = "ulpi";
  134. port1;
  135. };
  136. /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
  137. usb@23000 {
  138. device_type = "usb";
  139. compatible = "fsl-usb2-dr";
  140. reg = <0x23000 0x1000>;
  141. #address-cells = <1>;
  142. #size-cells = <0>;
  143. interrupt-parent = <&ipic>;
  144. interrupts = <38 0x8>;
  145. dr_mode = "otg";
  146. phy_type = "ulpi";
  147. };
  148. mdio@24520 {
  149. #address-cells = <1>;
  150. #size-cells = <0>;
  151. compatible = "fsl,gianfar-mdio";
  152. reg = <0x24520 0x20>;
  153. phy0: ethernet-phy@19 {
  154. interrupt-parent = <&ipic>;
  155. interrupts = <20 0x8>;
  156. reg = <0x19>;
  157. device_type = "ethernet-phy";
  158. };
  159. phy1: ethernet-phy@1a {
  160. interrupt-parent = <&ipic>;
  161. interrupts = <21 0x8>;
  162. reg = <0x1a>;
  163. device_type = "ethernet-phy";
  164. };
  165. tbi0: tbi-phy@11 {
  166. reg = <0x11>;
  167. device_type = "tbi-phy";
  168. };
  169. };
  170. mdio@25520 {
  171. #address-cells = <1>;
  172. #size-cells = <0>;
  173. compatible = "fsl,gianfar-tbi";
  174. reg = <0x25520 0x20>;
  175. tbi1: tbi-phy@11 {
  176. reg = <0x11>;
  177. device_type = "tbi-phy";
  178. };
  179. };
  180. enet0: ethernet@24000 {
  181. cell-index = <0>;
  182. device_type = "network";
  183. model = "TSEC";
  184. compatible = "gianfar";
  185. reg = <0x24000 0x1000>;
  186. local-mac-address = [ 00 00 00 00 00 00 ];
  187. interrupts = <32 0x8 33 0x8 34 0x8>;
  188. interrupt-parent = <&ipic>;
  189. tbi-handle = <&tbi0>;
  190. phy-handle = <&phy0>;
  191. linux,network-index = <0>;
  192. };
  193. enet1: ethernet@25000 {
  194. cell-index = <1>;
  195. device_type = "network";
  196. model = "TSEC";
  197. compatible = "gianfar";
  198. reg = <0x25000 0x1000>;
  199. local-mac-address = [ 00 00 00 00 00 00 ];
  200. interrupts = <35 0x8 36 0x8 37 0x8>;
  201. interrupt-parent = <&ipic>;
  202. tbi-handle = <&tbi1>;
  203. phy-handle = <&phy1>;
  204. linux,network-index = <1>;
  205. };
  206. serial0: serial@4500 {
  207. cell-index = <0>;
  208. device_type = "serial";
  209. compatible = "ns16550";
  210. reg = <0x4500 0x100>;
  211. clock-frequency = <0>;
  212. interrupts = <9 0x8>;
  213. interrupt-parent = <&ipic>;
  214. };
  215. serial1: serial@4600 {
  216. cell-index = <1>;
  217. device_type = "serial";
  218. compatible = "ns16550";
  219. reg = <0x4600 0x100>;
  220. clock-frequency = <0>;
  221. interrupts = <10 0x8>;
  222. interrupt-parent = <&ipic>;
  223. };
  224. crypto@30000 {
  225. compatible = "fsl,sec2.0";
  226. reg = <0x30000 0x10000>;
  227. interrupts = <11 0x8>;
  228. interrupt-parent = <&ipic>;
  229. fsl,num-channels = <4>;
  230. fsl,channel-fifo-len = <24>;
  231. fsl,exec-units-mask = <0x7e>;
  232. fsl,descriptor-types-mask = <0x01010ebf>;
  233. };
  234. /* IPIC
  235. * interrupts cell = <intr #, sense>
  236. * sense values match linux IORESOURCE_IRQ_* defines:
  237. * sense == 8: Level, low assertion
  238. * sense == 2: Edge, high-to-low change
  239. */
  240. ipic: pic@700 {
  241. interrupt-controller;
  242. #address-cells = <0>;
  243. #interrupt-cells = <2>;
  244. reg = <0x700 0x100>;
  245. device_type = "ipic";
  246. };
  247. };
  248. pci0: pci@e0008500 {
  249. cell-index = <1>;
  250. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  251. interrupt-map = <
  252. /* IDSEL 0x11 */
  253. 0x8800 0x0 0x0 0x1 &ipic 20 0x8
  254. 0x8800 0x0 0x0 0x2 &ipic 21 0x8
  255. 0x8800 0x0 0x0 0x3 &ipic 22 0x8
  256. 0x8800 0x0 0x0 0x4 &ipic 23 0x8>;
  257. interrupt-parent = <&ipic>;
  258. interrupts = <0x42 0x8>;
  259. bus-range = <0 0>;
  260. ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  261. 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  262. 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
  263. clock-frequency = <66666666>;
  264. #interrupt-cells = <1>;
  265. #size-cells = <2>;
  266. #address-cells = <3>;
  267. reg = <0xe0008500 0x100 /* internal registers */
  268. 0xe0008300 0x8>; /* config space access registers */
  269. compatible = "fsl,mpc8349-pci";
  270. device_type = "pci";
  271. };
  272. };