mpc8536ds.dts 10.0 KB

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  1. /*
  2. * MPC8536 DS Device Tree Source
  3. *
  4. * Copyright 2008 Freescale Semiconductor, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "fsl,mpc8536ds";
  14. compatible = "fsl,mpc8536ds";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. pci0 = &pci0;
  23. pci1 = &pci1;
  24. pci2 = &pci2;
  25. pci3 = &pci3;
  26. };
  27. cpus {
  28. #cpus = <1>;
  29. #address-cells = <1>;
  30. #size-cells = <0>;
  31. PowerPC,8536@0 {
  32. device_type = "cpu";
  33. reg = <0>;
  34. next-level-cache = <&L2>;
  35. };
  36. };
  37. memory {
  38. device_type = "memory";
  39. reg = <00000000 00000000>; // Filled by U-Boot
  40. };
  41. soc@ffe00000 {
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. device_type = "soc";
  45. compatible = "simple-bus";
  46. ranges = <0x0 0xffe00000 0x100000>;
  47. reg = <0xffe00000 0x1000>;
  48. bus-frequency = <0>; // Filled out by uboot.
  49. memory-controller@2000 {
  50. compatible = "fsl,mpc8536-memory-controller";
  51. reg = <0x2000 0x1000>;
  52. interrupt-parent = <&mpic>;
  53. interrupts = <18 0x2>;
  54. };
  55. L2: l2-cache-controller@20000 {
  56. compatible = "fsl,mpc8536-l2-cache-controller";
  57. reg = <0x20000 0x1000>;
  58. interrupt-parent = <&mpic>;
  59. interrupts = <16 0x2>;
  60. };
  61. i2c@3000 {
  62. #address-cells = <1>;
  63. #size-cells = <0>;
  64. cell-index = <0>;
  65. compatible = "fsl-i2c";
  66. reg = <0x3000 0x100>;
  67. interrupts = <43 0x2>;
  68. interrupt-parent = <&mpic>;
  69. dfsrr;
  70. };
  71. i2c@3100 {
  72. #address-cells = <1>;
  73. #size-cells = <0>;
  74. cell-index = <1>;
  75. compatible = "fsl-i2c";
  76. reg = <0x3100 0x100>;
  77. interrupts = <43 0x2>;
  78. interrupt-parent = <&mpic>;
  79. dfsrr;
  80. rtc@68 {
  81. compatible = "dallas,ds3232";
  82. reg = <0x68>;
  83. interrupts = <0 0x1>;
  84. interrupt-parent = <&mpic>;
  85. };
  86. };
  87. dma@21300 {
  88. #address-cells = <1>;
  89. #size-cells = <1>;
  90. compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
  91. reg = <0x21300 4>;
  92. ranges = <0 0x21100 0x200>;
  93. cell-index = <0>;
  94. dma-channel@0 {
  95. compatible = "fsl,mpc8536-dma-channel",
  96. "fsl,eloplus-dma-channel";
  97. reg = <0x0 0x80>;
  98. cell-index = <0>;
  99. interrupt-parent = <&mpic>;
  100. interrupts = <20 2>;
  101. };
  102. dma-channel@80 {
  103. compatible = "fsl,mpc8536-dma-channel",
  104. "fsl,eloplus-dma-channel";
  105. reg = <0x80 0x80>;
  106. cell-index = <1>;
  107. interrupt-parent = <&mpic>;
  108. interrupts = <21 2>;
  109. };
  110. dma-channel@100 {
  111. compatible = "fsl,mpc8536-dma-channel",
  112. "fsl,eloplus-dma-channel";
  113. reg = <0x100 0x80>;
  114. cell-index = <2>;
  115. interrupt-parent = <&mpic>;
  116. interrupts = <22 2>;
  117. };
  118. dma-channel@180 {
  119. compatible = "fsl,mpc8536-dma-channel",
  120. "fsl,eloplus-dma-channel";
  121. reg = <0x180 0x80>;
  122. cell-index = <3>;
  123. interrupt-parent = <&mpic>;
  124. interrupts = <23 2>;
  125. };
  126. };
  127. mdio@24520 {
  128. #address-cells = <1>;
  129. #size-cells = <0>;
  130. compatible = "fsl,gianfar-mdio";
  131. reg = <0x24520 0x20>;
  132. phy0: ethernet-phy@0 {
  133. interrupt-parent = <&mpic>;
  134. interrupts = <10 0x1>;
  135. reg = <0>;
  136. device_type = "ethernet-phy";
  137. };
  138. phy1: ethernet-phy@1 {
  139. interrupt-parent = <&mpic>;
  140. interrupts = <10 0x1>;
  141. reg = <1>;
  142. device_type = "ethernet-phy";
  143. };
  144. tbi0: tbi-phy@11 {
  145. reg = <0x11>;
  146. device_type = "tbi-phy";
  147. };
  148. };
  149. mdio@26520 {
  150. #address-cells = <1>;
  151. #size-cells = <0>;
  152. compatible = "fsl,gianfar-tbi";
  153. reg = <0x26520 0x20>;
  154. tbi1: tbi-phy@11 {
  155. reg = <0x11>;
  156. device_type = "tbi-phy";
  157. };
  158. };
  159. usb@22000 {
  160. compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
  161. reg = <0x22000 0x1000>;
  162. #address-cells = <1>;
  163. #size-cells = <0>;
  164. interrupt-parent = <&mpic>;
  165. interrupts = <28 0x2>;
  166. phy_type = "ulpi";
  167. };
  168. usb@23000 {
  169. compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
  170. reg = <0x23000 0x1000>;
  171. #address-cells = <1>;
  172. #size-cells = <0>;
  173. interrupt-parent = <&mpic>;
  174. interrupts = <46 0x2>;
  175. phy_type = "ulpi";
  176. };
  177. enet0: ethernet@24000 {
  178. cell-index = <0>;
  179. device_type = "network";
  180. model = "eTSEC";
  181. compatible = "gianfar";
  182. reg = <0x24000 0x1000>;
  183. local-mac-address = [ 00 00 00 00 00 00 ];
  184. interrupts = <29 2 30 2 34 2>;
  185. interrupt-parent = <&mpic>;
  186. tbi-handle = <&tbi0>;
  187. phy-handle = <&phy1>;
  188. phy-connection-type = "rgmii-id";
  189. };
  190. enet1: ethernet@26000 {
  191. cell-index = <1>;
  192. device_type = "network";
  193. model = "eTSEC";
  194. compatible = "gianfar";
  195. reg = <0x26000 0x1000>;
  196. local-mac-address = [ 00 00 00 00 00 00 ];
  197. interrupts = <31 2 32 2 33 2>;
  198. interrupt-parent = <&mpic>;
  199. tbi-handle = <&tbi1>;
  200. phy-handle = <&phy0>;
  201. phy-connection-type = "rgmii-id";
  202. };
  203. usb@2b000 {
  204. compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
  205. reg = <0x2b000 0x1000>;
  206. #address-cells = <1>;
  207. #size-cells = <0>;
  208. interrupt-parent = <&mpic>;
  209. interrupts = <60 0x2>;
  210. dr_mode = "peripheral";
  211. phy_type = "ulpi";
  212. };
  213. serial0: serial@4500 {
  214. cell-index = <0>;
  215. device_type = "serial";
  216. compatible = "ns16550";
  217. reg = <0x4500 0x100>;
  218. clock-frequency = <0>;
  219. interrupts = <42 0x2>;
  220. interrupt-parent = <&mpic>;
  221. };
  222. serial1: serial@4600 {
  223. cell-index = <1>;
  224. device_type = "serial";
  225. compatible = "ns16550";
  226. reg = <0x4600 0x100>;
  227. clock-frequency = <0>;
  228. interrupts = <42 0x2>;
  229. interrupt-parent = <&mpic>;
  230. };
  231. crypto@30000 {
  232. compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
  233. "fsl,sec2.1", "fsl,sec2.0";
  234. reg = <0x30000 0x10000>;
  235. interrupts = <45 2 58 2>;
  236. interrupt-parent = <&mpic>;
  237. fsl,num-channels = <4>;
  238. fsl,channel-fifo-len = <24>;
  239. fsl,exec-units-mask = <0x9fe>;
  240. fsl,descriptor-types-mask = <0x3ab0ebf>;
  241. };
  242. sata@18000 {
  243. compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
  244. reg = <0x18000 0x1000>;
  245. cell-index = <1>;
  246. interrupts = <74 0x2>;
  247. interrupt-parent = <&mpic>;
  248. };
  249. sata@19000 {
  250. compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
  251. reg = <0x19000 0x1000>;
  252. cell-index = <2>;
  253. interrupts = <41 0x2>;
  254. interrupt-parent = <&mpic>;
  255. };
  256. global-utilities@e0000 { //global utilities block
  257. compatible = "fsl,mpc8548-guts";
  258. reg = <0xe0000 0x1000>;
  259. fsl,has-rstcr;
  260. };
  261. mpic: pic@40000 {
  262. clock-frequency = <0>;
  263. interrupt-controller;
  264. #address-cells = <0>;
  265. #interrupt-cells = <2>;
  266. reg = <0x40000 0x40000>;
  267. compatible = "chrp,open-pic";
  268. device_type = "open-pic";
  269. big-endian;
  270. };
  271. msi@41600 {
  272. compatible = "fsl,mpc8536-msi", "fsl,mpic-msi";
  273. reg = <0x41600 0x80>;
  274. msi-available-ranges = <0 0x100>;
  275. interrupts = <
  276. 0xe0 0
  277. 0xe1 0
  278. 0xe2 0
  279. 0xe3 0
  280. 0xe4 0
  281. 0xe5 0
  282. 0xe6 0
  283. 0xe7 0>;
  284. interrupt-parent = <&mpic>;
  285. };
  286. };
  287. pci0: pci@ffe08000 {
  288. cell-index = <0>;
  289. compatible = "fsl,mpc8540-pci";
  290. device_type = "pci";
  291. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  292. interrupt-map = <
  293. /* IDSEL 0x11 J17 Slot 1 */
  294. 0x8800 0 0 1 &mpic 1 1
  295. 0x8800 0 0 2 &mpic 2 1
  296. 0x8800 0 0 3 &mpic 3 1
  297. 0x8800 0 0 4 &mpic 4 1>;
  298. interrupt-parent = <&mpic>;
  299. interrupts = <24 0x2>;
  300. bus-range = <0 0xff>;
  301. ranges = <0x02000000 0 0x80000000 0x80000000 0 0x10000000
  302. 0x01000000 0 0x00000000 0xffc00000 0 0x00010000>;
  303. clock-frequency = <66666666>;
  304. #interrupt-cells = <1>;
  305. #size-cells = <2>;
  306. #address-cells = <3>;
  307. reg = <0xffe08000 0x1000>;
  308. };
  309. pci1: pcie@ffe09000 {
  310. cell-index = <1>;
  311. compatible = "fsl,mpc8548-pcie";
  312. device_type = "pci";
  313. #interrupt-cells = <1>;
  314. #size-cells = <2>;
  315. #address-cells = <3>;
  316. reg = <0xffe09000 0x1000>;
  317. bus-range = <0 0xff>;
  318. ranges = <0x02000000 0 0x98000000 0x98000000 0 0x08000000
  319. 0x01000000 0 0x00000000 0xffc20000 0 0x00010000>;
  320. clock-frequency = <33333333>;
  321. interrupt-parent = <&mpic>;
  322. interrupts = <25 0x2>;
  323. interrupt-map-mask = <0xf800 0 0 7>;
  324. interrupt-map = <
  325. /* IDSEL 0x0 */
  326. 0000 0 0 1 &mpic 4 1
  327. 0000 0 0 2 &mpic 5 1
  328. 0000 0 0 3 &mpic 6 1
  329. 0000 0 0 4 &mpic 7 1
  330. >;
  331. pcie@0 {
  332. reg = <0 0 0 0 0>;
  333. #size-cells = <2>;
  334. #address-cells = <3>;
  335. device_type = "pci";
  336. ranges = <0x02000000 0 0x98000000
  337. 0x02000000 0 0x98000000
  338. 0 0x08000000
  339. 0x01000000 0 0x00000000
  340. 0x01000000 0 0x00000000
  341. 0 0x00010000>;
  342. };
  343. };
  344. pci2: pcie@ffe0a000 {
  345. cell-index = <2>;
  346. compatible = "fsl,mpc8548-pcie";
  347. device_type = "pci";
  348. #interrupt-cells = <1>;
  349. #size-cells = <2>;
  350. #address-cells = <3>;
  351. reg = <0xffe0a000 0x1000>;
  352. bus-range = <0 0xff>;
  353. ranges = <0x02000000 0 0x90000000 0x90000000 0 0x08000000
  354. 0x01000000 0 0x00000000 0xffc10000 0 0x00010000>;
  355. clock-frequency = <33333333>;
  356. interrupt-parent = <&mpic>;
  357. interrupts = <26 0x2>;
  358. interrupt-map-mask = <0xf800 0 0 7>;
  359. interrupt-map = <
  360. /* IDSEL 0x0 */
  361. 0000 0 0 1 &mpic 0 1
  362. 0000 0 0 2 &mpic 1 1
  363. 0000 0 0 3 &mpic 2 1
  364. 0000 0 0 4 &mpic 3 1
  365. >;
  366. pcie@0 {
  367. reg = <0 0 0 0 0>;
  368. #size-cells = <2>;
  369. #address-cells = <3>;
  370. device_type = "pci";
  371. ranges = <0x02000000 0 0x90000000
  372. 0x02000000 0 0x90000000
  373. 0 0x08000000
  374. 0x01000000 0 0x00000000
  375. 0x01000000 0 0x00000000
  376. 0 0x00010000>;
  377. };
  378. };
  379. pci3: pcie@ffe0b000 {
  380. cell-index = <3>;
  381. compatible = "fsl,mpc8548-pcie";
  382. device_type = "pci";
  383. #interrupt-cells = <1>;
  384. #size-cells = <2>;
  385. #address-cells = <3>;
  386. reg = <0xffe0b000 0x1000>;
  387. bus-range = <0 0xff>;
  388. ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
  389. 0x01000000 0 0x00000000 0xffc30000 0 0x00010000>;
  390. clock-frequency = <33333333>;
  391. interrupt-parent = <&mpic>;
  392. interrupts = <27 0x2>;
  393. interrupt-map-mask = <0xf800 0 0 7>;
  394. interrupt-map = <
  395. /* IDSEL 0x0 */
  396. 0000 0 0 1 &mpic 8 1
  397. 0000 0 0 2 &mpic 9 1
  398. 0000 0 0 3 &mpic 10 1
  399. 0000 0 0 4 &mpic 11 1
  400. >;
  401. pcie@0 {
  402. reg = <0 0 0 0 0>;
  403. #size-cells = <2>;
  404. #address-cells = <3>;
  405. device_type = "pci";
  406. ranges = <0x02000000 0 0xa0000000
  407. 0x02000000 0 0xa0000000
  408. 0 0x20000000
  409. 0x01000000 0 0x00000000
  410. 0x01000000 0 0x00000000
  411. 0 0x00100000>;
  412. };
  413. };
  414. };