mpc8315erdb.dts 8.0 KB

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  1. /*
  2. * MPC8315E RDB Device Tree Source
  3. *
  4. * Copyright 2007 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. compatible = "fsl,mpc8315erdb";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. aliases {
  17. ethernet0 = &enet0;
  18. ethernet1 = &enet1;
  19. serial0 = &serial0;
  20. serial1 = &serial1;
  21. pci0 = &pci0;
  22. };
  23. cpus {
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. PowerPC,8315@0 {
  27. device_type = "cpu";
  28. reg = <0x0>;
  29. d-cache-line-size = <32>;
  30. i-cache-line-size = <32>;
  31. d-cache-size = <16384>;
  32. i-cache-size = <16384>;
  33. timebase-frequency = <0>; // from bootloader
  34. bus-frequency = <0>; // from bootloader
  35. clock-frequency = <0>; // from bootloader
  36. };
  37. };
  38. memory {
  39. device_type = "memory";
  40. reg = <0x00000000 0x08000000>; // 128MB at 0
  41. };
  42. localbus@e0005000 {
  43. #address-cells = <2>;
  44. #size-cells = <1>;
  45. compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
  46. reg = <0xe0005000 0x1000>;
  47. interrupts = <77 0x8>;
  48. interrupt-parent = <&ipic>;
  49. // CS0 and CS1 are swapped when
  50. // booting from nand, but the
  51. // addresses are the same.
  52. ranges = <0x0 0x0 0xfe000000 0x00800000
  53. 0x1 0x0 0xe0600000 0x00002000
  54. 0x2 0x0 0xf0000000 0x00020000
  55. 0x3 0x0 0xfa000000 0x00008000>;
  56. flash@0,0 {
  57. #address-cells = <1>;
  58. #size-cells = <1>;
  59. compatible = "cfi-flash";
  60. reg = <0x0 0x0 0x800000>;
  61. bank-width = <2>;
  62. device-width = <1>;
  63. };
  64. nand@1,0 {
  65. #address-cells = <1>;
  66. #size-cells = <1>;
  67. compatible = "fsl,mpc8315-fcm-nand",
  68. "fsl,elbc-fcm-nand";
  69. reg = <0x1 0x0 0x2000>;
  70. u-boot@0 {
  71. reg = <0x0 0x100000>;
  72. read-only;
  73. };
  74. kernel@100000 {
  75. reg = <0x100000 0x300000>;
  76. };
  77. fs@400000 {
  78. reg = <0x400000 0x1c00000>;
  79. };
  80. };
  81. };
  82. immr@e0000000 {
  83. #address-cells = <1>;
  84. #size-cells = <1>;
  85. device_type = "soc";
  86. compatible = "fsl,mpc8315-immr", "simple-bus";
  87. ranges = <0 0xe0000000 0x00100000>;
  88. reg = <0xe0000000 0x00000200>;
  89. bus-frequency = <0>;
  90. wdt@200 {
  91. device_type = "watchdog";
  92. compatible = "mpc83xx_wdt";
  93. reg = <0x200 0x100>;
  94. };
  95. i2c@3000 {
  96. #address-cells = <1>;
  97. #size-cells = <0>;
  98. cell-index = <0>;
  99. compatible = "fsl-i2c";
  100. reg = <0x3000 0x100>;
  101. interrupts = <14 0x8>;
  102. interrupt-parent = <&ipic>;
  103. dfsrr;
  104. rtc@68 {
  105. compatible = "dallas,ds1339";
  106. reg = <0x68>;
  107. };
  108. mcu_pio: mcu@a {
  109. #gpio-cells = <2>;
  110. compatible = "fsl,mc9s08qg8-mpc8315erdb",
  111. "fsl,mcu-mpc8349emitx";
  112. reg = <0x0a>;
  113. gpio-controller;
  114. };
  115. };
  116. spi@7000 {
  117. cell-index = <0>;
  118. compatible = "fsl,spi";
  119. reg = <0x7000 0x1000>;
  120. interrupts = <16 0x8>;
  121. interrupt-parent = <&ipic>;
  122. mode = "cpu";
  123. };
  124. dma@82a8 {
  125. #address-cells = <1>;
  126. #size-cells = <1>;
  127. compatible = "fsl,mpc8315-dma", "fsl,elo-dma";
  128. reg = <0x82a8 4>;
  129. ranges = <0 0x8100 0x1a8>;
  130. interrupt-parent = <&ipic>;
  131. interrupts = <71 8>;
  132. cell-index = <0>;
  133. dma-channel@0 {
  134. compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
  135. reg = <0 0x80>;
  136. cell-index = <0>;
  137. interrupt-parent = <&ipic>;
  138. interrupts = <71 8>;
  139. };
  140. dma-channel@80 {
  141. compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
  142. reg = <0x80 0x80>;
  143. cell-index = <1>;
  144. interrupt-parent = <&ipic>;
  145. interrupts = <71 8>;
  146. };
  147. dma-channel@100 {
  148. compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
  149. reg = <0x100 0x80>;
  150. cell-index = <2>;
  151. interrupt-parent = <&ipic>;
  152. interrupts = <71 8>;
  153. };
  154. dma-channel@180 {
  155. compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
  156. reg = <0x180 0x28>;
  157. cell-index = <3>;
  158. interrupt-parent = <&ipic>;
  159. interrupts = <71 8>;
  160. };
  161. };
  162. usb@23000 {
  163. compatible = "fsl-usb2-dr";
  164. reg = <0x23000 0x1000>;
  165. #address-cells = <1>;
  166. #size-cells = <0>;
  167. interrupt-parent = <&ipic>;
  168. interrupts = <38 0x8>;
  169. phy_type = "utmi";
  170. };
  171. mdio@24520 {
  172. #address-cells = <1>;
  173. #size-cells = <0>;
  174. compatible = "fsl,gianfar-mdio";
  175. reg = <0x24520 0x20>;
  176. phy0: ethernet-phy@0 {
  177. interrupt-parent = <&ipic>;
  178. interrupts = <20 0x8>;
  179. reg = <0x0>;
  180. device_type = "ethernet-phy";
  181. };
  182. phy1: ethernet-phy@1 {
  183. interrupt-parent = <&ipic>;
  184. interrupts = <19 0x8>;
  185. reg = <0x1>;
  186. device_type = "ethernet-phy";
  187. };
  188. tbi0: tbi-phy@11 {
  189. reg = <0x11>;
  190. device_type = "tbi-phy";
  191. };
  192. };
  193. mdio@25520 {
  194. #address-cells = <1>;
  195. #size-cells = <0>;
  196. compatible = "fsl,gianfar-tbi";
  197. reg = <0x25520 0x20>;
  198. tbi1: tbi-phy@11 {
  199. reg = <0x11>;
  200. device_type = "tbi-phy";
  201. };
  202. };
  203. enet0: ethernet@24000 {
  204. cell-index = <0>;
  205. device_type = "network";
  206. model = "eTSEC";
  207. compatible = "gianfar";
  208. reg = <0x24000 0x1000>;
  209. local-mac-address = [ 00 00 00 00 00 00 ];
  210. interrupts = <32 0x8 33 0x8 34 0x8>;
  211. interrupt-parent = <&ipic>;
  212. tbi-handle = <&tbi0>;
  213. phy-handle = < &phy0 >;
  214. };
  215. enet1: ethernet@25000 {
  216. cell-index = <1>;
  217. device_type = "network";
  218. model = "eTSEC";
  219. compatible = "gianfar";
  220. reg = <0x25000 0x1000>;
  221. local-mac-address = [ 00 00 00 00 00 00 ];
  222. interrupts = <35 0x8 36 0x8 37 0x8>;
  223. interrupt-parent = <&ipic>;
  224. tbi-handle = <&tbi1>;
  225. phy-handle = < &phy1 >;
  226. };
  227. serial0: serial@4500 {
  228. cell-index = <0>;
  229. device_type = "serial";
  230. compatible = "ns16550";
  231. reg = <0x4500 0x100>;
  232. clock-frequency = <0>;
  233. interrupts = <9 0x8>;
  234. interrupt-parent = <&ipic>;
  235. };
  236. serial1: serial@4600 {
  237. cell-index = <1>;
  238. device_type = "serial";
  239. compatible = "ns16550";
  240. reg = <0x4600 0x100>;
  241. clock-frequency = <0>;
  242. interrupts = <10 0x8>;
  243. interrupt-parent = <&ipic>;
  244. };
  245. crypto@30000 {
  246. compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
  247. "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
  248. "fsl,sec2.0";
  249. reg = <0x30000 0x10000>;
  250. interrupts = <11 0x8>;
  251. interrupt-parent = <&ipic>;
  252. fsl,num-channels = <4>;
  253. fsl,channel-fifo-len = <24>;
  254. fsl,exec-units-mask = <0x97c>;
  255. fsl,descriptor-types-mask = <0x3ab0abf>;
  256. };
  257. sata@18000 {
  258. compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
  259. reg = <0x18000 0x1000>;
  260. cell-index = <1>;
  261. interrupts = <44 0x8>;
  262. interrupt-parent = <&ipic>;
  263. };
  264. sata@19000 {
  265. compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
  266. reg = <0x19000 0x1000>;
  267. cell-index = <2>;
  268. interrupts = <45 0x8>;
  269. interrupt-parent = <&ipic>;
  270. };
  271. /* IPIC
  272. * interrupts cell = <intr #, sense>
  273. * sense values match linux IORESOURCE_IRQ_* defines:
  274. * sense == 8: Level, low assertion
  275. * sense == 2: Edge, high-to-low change
  276. */
  277. ipic: interrupt-controller@700 {
  278. interrupt-controller;
  279. #address-cells = <0>;
  280. #interrupt-cells = <2>;
  281. reg = <0x700 0x100>;
  282. device_type = "ipic";
  283. };
  284. };
  285. pci0: pci@e0008500 {
  286. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  287. interrupt-map = <
  288. /* IDSEL 0x0E -mini PCI */
  289. 0x7000 0x0 0x0 0x1 &ipic 18 0x8
  290. 0x7000 0x0 0x0 0x2 &ipic 18 0x8
  291. 0x7000 0x0 0x0 0x3 &ipic 18 0x8
  292. 0x7000 0x0 0x0 0x4 &ipic 18 0x8
  293. /* IDSEL 0x0F -mini PCI */
  294. 0x7800 0x0 0x0 0x1 &ipic 17 0x8
  295. 0x7800 0x0 0x0 0x2 &ipic 17 0x8
  296. 0x7800 0x0 0x0 0x3 &ipic 17 0x8
  297. 0x7800 0x0 0x0 0x4 &ipic 17 0x8
  298. /* IDSEL 0x10 - PCI slot */
  299. 0x8000 0x0 0x0 0x1 &ipic 48 0x8
  300. 0x8000 0x0 0x0 0x2 &ipic 17 0x8
  301. 0x8000 0x0 0x0 0x3 &ipic 48 0x8
  302. 0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
  303. interrupt-parent = <&ipic>;
  304. interrupts = <66 0x8>;
  305. bus-range = <0x0 0x0>;
  306. ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
  307. 0x42000000 0 0x80000000 0x80000000 0 0x10000000
  308. 0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;
  309. clock-frequency = <66666666>;
  310. #interrupt-cells = <1>;
  311. #size-cells = <2>;
  312. #address-cells = <3>;
  313. reg = <0xe0008500 0x100 /* internal registers */
  314. 0xe0008300 0x8>; /* config space access registers */
  315. compatible = "fsl,mpc8349-pci";
  316. device_type = "pci";
  317. };
  318. };