head.S 4.5 KB

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  1. /*
  2. * Common Blackfin startup code
  3. *
  4. * Copyright 2004-2008 Analog Devices Inc.
  5. *
  6. * Enter bugs at http://blackfin.uclinux.org/
  7. *
  8. * Licensed under the GPL-2 or later.
  9. */
  10. #include <linux/linkage.h>
  11. #include <linux/init.h>
  12. #include <asm/blackfin.h>
  13. #include <asm/thread_info.h>
  14. #include <asm/trace.h>
  15. #include <asm/asm-offsets.h>
  16. __INIT
  17. #define INITIAL_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
  18. ENTRY(__start)
  19. /* R0: argument of command line string, passed from uboot, save it */
  20. R7 = R0;
  21. /* Enable Cycle Counter and Nesting Of Interrupts */
  22. #ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
  23. R0 = SYSCFG_SNEN;
  24. #else
  25. R0 = SYSCFG_SNEN | SYSCFG_CCEN;
  26. #endif
  27. SYSCFG = R0;
  28. R0 = 0;
  29. /* Clear Out All the data and pointer Registers */
  30. R1 = R0;
  31. R2 = R0;
  32. R3 = R0;
  33. R4 = R0;
  34. R5 = R0;
  35. R6 = R0;
  36. P0 = R0;
  37. P1 = R0;
  38. P2 = R0;
  39. P3 = R0;
  40. P4 = R0;
  41. P5 = R0;
  42. LC0 = r0;
  43. LC1 = r0;
  44. L0 = r0;
  45. L1 = r0;
  46. L2 = r0;
  47. L3 = r0;
  48. /* Clear Out All the DAG Registers */
  49. B0 = r0;
  50. B1 = r0;
  51. B2 = r0;
  52. B3 = r0;
  53. I0 = r0;
  54. I1 = r0;
  55. I2 = r0;
  56. I3 = r0;
  57. M0 = r0;
  58. M1 = r0;
  59. M2 = r0;
  60. M3 = r0;
  61. /*
  62. * Clear ITEST_COMMAND and DTEST_COMMAND registers,
  63. * Leaving these as non-zero can confuse the emulator
  64. */
  65. p0.L = LO(DTEST_COMMAND);
  66. p0.H = HI(DTEST_COMMAND);
  67. [p0] = R0;
  68. [p0 + (ITEST_COMMAND - DTEST_COMMAND)] = R0;
  69. CSYNC;
  70. trace_buffer_init(p0,r0);
  71. P0 = R1;
  72. R0 = R1;
  73. /* Turn off the icache */
  74. p0.l = LO(IMEM_CONTROL);
  75. p0.h = HI(IMEM_CONTROL);
  76. R1 = [p0];
  77. R0 = ~ENICPLB;
  78. R0 = R0 & R1;
  79. [p0] = R0;
  80. SSYNC;
  81. /* Turn off the dcache */
  82. p0.l = LO(DMEM_CONTROL);
  83. p0.h = HI(DMEM_CONTROL);
  84. R1 = [p0];
  85. R0 = ~ENDCPLB;
  86. R0 = R0 & R1;
  87. [p0] = R0;
  88. SSYNC;
  89. /* in case of double faults, save a few things */
  90. p0.l = _init_retx;
  91. p0.h = _init_retx;
  92. R0 = RETX;
  93. [P0] = R0;
  94. #ifdef CONFIG_DEBUG_DOUBLEFAULT
  95. /* Only save these if we are storing them,
  96. * This happens here, since L1 gets clobbered
  97. * below
  98. */
  99. GET_PDA(p0, r0);
  100. r7 = [p0 + PDA_RETX];
  101. p1.l = _init_saved_retx;
  102. p1.h = _init_saved_retx;
  103. [p1] = r7;
  104. r7 = [p0 + PDA_DCPLB];
  105. p1.l = _init_saved_dcplb_fault_addr;
  106. p1.h = _init_saved_dcplb_fault_addr;
  107. [p1] = r7;
  108. r7 = [p0 + PDA_ICPLB];
  109. p1.l = _init_saved_icplb_fault_addr;
  110. p1.h = _init_saved_icplb_fault_addr;
  111. [p1] = r7;
  112. r7 = [p0 + PDA_SEQSTAT];
  113. p1.l = _init_saved_seqstat;
  114. p1.h = _init_saved_seqstat;
  115. [p1] = r7;
  116. #endif
  117. /* Initialize stack pointer */
  118. sp.l = lo(INITIAL_STACK);
  119. sp.h = hi(INITIAL_STACK);
  120. fp = sp;
  121. usp = sp;
  122. #ifdef CONFIG_EARLY_PRINTK
  123. call _init_early_exception_vectors;
  124. #endif
  125. /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
  126. call _bfin_relocate_l1_mem;
  127. #ifdef CONFIG_BFIN_KERNEL_CLOCK
  128. call _start_dma_code;
  129. #endif
  130. /* This section keeps the processor in supervisor mode
  131. * during kernel boot. Switches to user mode at end of boot.
  132. * See page 3-9 of Hardware Reference manual for documentation.
  133. */
  134. /* EVT15 = _real_start */
  135. p0.l = lo(EVT15);
  136. p0.h = hi(EVT15);
  137. p1.l = _real_start;
  138. p1.h = _real_start;
  139. [p0] = p1;
  140. csync;
  141. r0 = EVT_IVG15 (z);
  142. sti r0;
  143. raise 15;
  144. p0.l = .LWAIT_HERE;
  145. p0.h = .LWAIT_HERE;
  146. reti = p0;
  147. #if ANOMALY_05000281
  148. nop; nop; nop;
  149. #endif
  150. rti;
  151. .LWAIT_HERE:
  152. jump .LWAIT_HERE;
  153. ENDPROC(__start)
  154. /* A little BF561 glue ... */
  155. #ifndef WDOG_CTL
  156. # define WDOG_CTL WDOGA_CTL
  157. #endif
  158. ENTRY(__init_clear_bss)
  159. r2 = r2 - r1;
  160. cc = r2 == 0;
  161. if cc jump .L_bss_done;
  162. r2 >>= 2;
  163. p1 = r1;
  164. p2 = r2;
  165. lsetup (1f, 1f) lc0 = p2;
  166. 1: [p1++] = r0;
  167. .L_bss_done:
  168. rts;
  169. ENDPROC(__init_clear_bss)
  170. ENTRY(_real_start)
  171. /* Enable nested interrupts */
  172. [--sp] = reti;
  173. /* watchdog off for now */
  174. p0.l = lo(WDOG_CTL);
  175. p0.h = hi(WDOG_CTL);
  176. r0 = 0xAD6(z);
  177. w[p0] = r0;
  178. ssync;
  179. r0 = 0 (x);
  180. /* Zero out all of the fun bss regions */
  181. #if L1_DATA_A_LENGTH > 0
  182. r1.l = __sbss_l1;
  183. r1.h = __sbss_l1;
  184. r2.l = __ebss_l1;
  185. r2.h = __ebss_l1;
  186. call __init_clear_bss
  187. #endif
  188. #if L1_DATA_B_LENGTH > 0
  189. r1.l = __sbss_b_l1;
  190. r1.h = __sbss_b_l1;
  191. r2.l = __ebss_b_l1;
  192. r2.h = __ebss_b_l1;
  193. call __init_clear_bss
  194. #endif
  195. #if L2_LENGTH > 0
  196. r1.l = __sbss_l2;
  197. r1.h = __sbss_l2;
  198. r2.l = __ebss_l2;
  199. r2.h = __ebss_l2;
  200. call __init_clear_bss
  201. #endif
  202. r1.l = ___bss_start;
  203. r1.h = ___bss_start;
  204. r2.l = ___bss_stop;
  205. r2.h = ___bss_stop;
  206. call __init_clear_bss
  207. /* Pass the u-boot arguments to the global value command line */
  208. R0 = R7;
  209. call _cmdline_init;
  210. /* Load the current thread pointer and stack */
  211. sp.l = _init_thread_union;
  212. sp.h = _init_thread_union;
  213. p1 = THREAD_SIZE (z);
  214. sp = sp + p1;
  215. usp = sp;
  216. fp = sp;
  217. sp += -12;
  218. call _init_pda
  219. sp += 12;
  220. jump.l _start_kernel;
  221. ENDPROC(_real_start)
  222. __FINIT