anomaly.h 8.8 KB

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  1. /*
  2. * File: include/asm-blackfin/mach-bf548/anomaly.h
  3. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  4. *
  5. * Copyright (C) 2004-2008 Analog Devices Inc.
  6. * Licensed under the GPL-2 or later.
  7. */
  8. /* This file shoule be up to date with:
  9. * - Revision G, 08/07/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
  10. */
  11. #ifndef _MACH_ANOMALY_H_
  12. #define _MACH_ANOMALY_H_
  13. /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
  14. #define ANOMALY_05000074 (1)
  15. /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
  16. #define ANOMALY_05000119 (1)
  17. /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
  18. #define ANOMALY_05000122 (1)
  19. /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
  20. #define ANOMALY_05000245 (1)
  21. /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
  22. #define ANOMALY_05000265 (1)
  23. /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
  24. #define ANOMALY_05000272 (1)
  25. /* False Hardware Error Exception when ISR context is not restored */
  26. #define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
  27. /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
  28. #define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
  29. /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
  30. #define ANOMALY_05000310 (1)
  31. /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
  32. #define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
  33. /* TWI Slave Boot Mode Is Not Functional */
  34. #define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
  35. /* External FIFO Boot Mode Is Not Functional */
  36. #define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
  37. /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
  38. #define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
  39. /* Incorrect Access of OTP_STATUS During otp_write() Function */
  40. #define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
  41. /* Synchronous Burst Flash Boot Mode Is Not Functional */
  42. #define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
  43. /* Host DMA Boot Modes Are Not Functional */
  44. #define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
  45. /* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
  46. #define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
  47. /* Inadequate Rotary Debounce Logic Duration */
  48. #define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
  49. /* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
  50. #define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
  51. /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
  52. #define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
  53. /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
  54. #define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
  55. /* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
  56. #define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
  57. /* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
  58. #define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
  59. /* USB Calibration Value Is Not Intialized */
  60. #define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
  61. /* USB Calibration Value to use */
  62. #define ANOMALY_05000346_value 0x5411
  63. /* Preboot Routine Incorrectly Alters Reset Value of USB Register */
  64. #define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
  65. /* Data Lost when Core Reads SDH Data FIFO */
  66. #define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
  67. /* PLL Status Register Is Inaccurate */
  68. #define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
  69. /* bfrom_SysControl() Firmware Function Performs Improper System Reset */
  70. #define ANOMALY_05000353 (__SILICON_REVISION__ < 2)
  71. /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
  72. #define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
  73. /* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
  74. #define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
  75. /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
  76. #define ANOMALY_05000357 (1)
  77. /* External Memory Read Access Hangs Core With PLL Bypass */
  78. #define ANOMALY_05000360 (1)
  79. /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
  80. #define ANOMALY_05000365 (1)
  81. /* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
  82. #define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
  83. /* Addressing Conflict between Boot ROM and Asynchronous Memory */
  84. #define ANOMALY_05000369 (1)
  85. /* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
  86. #define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
  87. /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
  88. #define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
  89. /* USB DP/DM Data Pins May Lose State When Entering Hibernate */
  90. #define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
  91. /* Mobile DDR Operation Not Functional */
  92. #define ANOMALY_05000377 (1)
  93. /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
  94. #define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
  95. /* 16-Bit NAND FLASH Boot Mode Is Not Functional */
  96. #define ANOMALY_05000379 (1)
  97. /* 8-Bit NAND Flash Boot Mode Not Functional */
  98. #define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
  99. /* Some ATAPI Modes Are Not Functional */
  100. #define ANOMALY_05000383 (1)
  101. /* Boot from OTP Memory Not Functional */
  102. #define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
  103. /* bfrom_SysControl() Firmware Routine Not Functional */
  104. #define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
  105. /* Programmable Preboot Settings Not Functional */
  106. #define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
  107. /* CRC32 Checksum Support Not Functional */
  108. #define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
  109. /* Reset Vector Must Not Be in SDRAM Memory Space */
  110. #define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
  111. /* Changed Meaning of BCODE Field in SYSCR Register */
  112. #define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
  113. /* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
  114. #define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
  115. /* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
  116. #define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
  117. /* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
  118. #define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
  119. /* Log Buffer Not Functional */
  120. #define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
  121. /* Hook Routine Not Functional */
  122. #define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
  123. /* Header Indirect Bit Not Functional */
  124. #define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
  125. /* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
  126. #define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
  127. /* Lockbox SESR Disallows Certain User Interrupts */
  128. #define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
  129. /* Lockbox SESR Firmware Does Not Save/Restore Full Context */
  130. #define ANOMALY_05000405 (1)
  131. /* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
  132. #define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
  133. /* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
  134. #define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
  135. /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
  136. #define ANOMALY_05000408 (1)
  137. /* Lockbox firmware leaves MDMA0 channel enabled */
  138. #define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
  139. /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
  140. #define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
  141. /* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
  142. #define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
  143. /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
  144. #define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
  145. /* Speculative Fetches Can Cause Undesired External FIFO Operations */
  146. #define ANOMALY_05000416 (1)
  147. /* Multichannel SPORT Channel Misalignment Under Specific Configuration */
  148. #define ANOMALY_05000425 (1)
  149. /* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */
  150. #define ANOMALY_05000426 (1)
  151. /* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
  152. #define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
  153. /* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Behaves as a Buffer Status Bit Instead of an IRQ Status Bit */
  154. #define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
  155. /* Software System Reset Corrupts PLL_LOCKCNT Register */
  156. #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
  157. /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
  158. #define ANOMALY_05000443 (1)
  159. /* Anomalies that don't exist on this proc */
  160. #define ANOMALY_05000125 (0)
  161. #define ANOMALY_05000158 (0)
  162. #define ANOMALY_05000183 (0)
  163. #define ANOMALY_05000198 (0)
  164. #define ANOMALY_05000230 (0)
  165. #define ANOMALY_05000244 (0)
  166. #define ANOMALY_05000261 (0)
  167. #define ANOMALY_05000263 (0)
  168. #define ANOMALY_05000266 (0)
  169. #define ANOMALY_05000273 (0)
  170. #define ANOMALY_05000307 (0)
  171. #define ANOMALY_05000311 (0)
  172. #define ANOMALY_05000323 (0)
  173. #define ANOMALY_05000363 (0)
  174. #endif