ezbrd.c 18 KB

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  1. /*
  2. * File: arch/blackfin/mach-bf527/boards/ezbrd.c
  3. * Based on: arch/blackfin/mach-bf537/boards/stamp.c
  4. * Author: Aidan Williams <aidan@nicta.com.au>
  5. *
  6. * Created:
  7. * Description:
  8. *
  9. * Modified:
  10. * Copyright 2005 National ICT Australia (NICTA)
  11. * Copyright 2004-2008 Analog Devices Inc.
  12. *
  13. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, see the file COPYING, or write
  27. * to the Free Software Foundation, Inc.,
  28. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  29. */
  30. #include <linux/device.h>
  31. #include <linux/platform_device.h>
  32. #include <linux/mtd/mtd.h>
  33. #include <linux/mtd/partitions.h>
  34. #include <linux/mtd/physmap.h>
  35. #include <linux/spi/spi.h>
  36. #include <linux/spi/flash.h>
  37. #include <linux/i2c.h>
  38. #include <linux/irq.h>
  39. #include <linux/interrupt.h>
  40. #include <linux/usb/musb.h>
  41. #include <asm/dma.h>
  42. #include <asm/bfin5xx_spi.h>
  43. #include <asm/reboot.h>
  44. #include <asm/nand.h>
  45. #include <asm/portmux.h>
  46. #include <asm/dpmc.h>
  47. #include <linux/spi/ad7877.h>
  48. /*
  49. * Name the Board for the /proc/cpuinfo
  50. */
  51. const char bfin_board_name[] = "ADI BF526-EZBRD";
  52. /*
  53. * Driver needs to know address, irq and flag pin.
  54. */
  55. #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
  56. static struct resource musb_resources[] = {
  57. [0] = {
  58. .start = 0xffc03800,
  59. .end = 0xffc03cff,
  60. .flags = IORESOURCE_MEM,
  61. },
  62. [1] = { /* general IRQ */
  63. .start = IRQ_USB_INT0,
  64. .end = IRQ_USB_INT0,
  65. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  66. },
  67. [2] = { /* DMA IRQ */
  68. .start = IRQ_USB_DMA,
  69. .end = IRQ_USB_DMA,
  70. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  71. },
  72. };
  73. static struct musb_hdrc_config musb_config = {
  74. .multipoint = 0,
  75. .dyn_fifo = 0,
  76. .soft_con = 1,
  77. .dma = 1,
  78. .num_eps = 7,
  79. .dma_channels = 7,
  80. .gpio_vrsel = GPIO_PG13,
  81. };
  82. static struct musb_hdrc_platform_data musb_plat = {
  83. #if defined(CONFIG_USB_MUSB_OTG)
  84. .mode = MUSB_OTG,
  85. #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
  86. .mode = MUSB_HOST,
  87. #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
  88. .mode = MUSB_PERIPHERAL,
  89. #endif
  90. .config = &musb_config,
  91. };
  92. static u64 musb_dmamask = ~(u32)0;
  93. static struct platform_device musb_device = {
  94. .name = "musb_hdrc",
  95. .id = 0,
  96. .dev = {
  97. .dma_mask = &musb_dmamask,
  98. .coherent_dma_mask = 0xffffffff,
  99. .platform_data = &musb_plat,
  100. },
  101. .num_resources = ARRAY_SIZE(musb_resources),
  102. .resource = musb_resources,
  103. };
  104. #endif
  105. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  106. static struct mtd_partition ezbrd_partitions[] = {
  107. {
  108. .name = "bootloader(nor)",
  109. .size = 0x40000,
  110. .offset = 0,
  111. }, {
  112. .name = "linux kernel(nor)",
  113. .size = 0x1C0000,
  114. .offset = MTDPART_OFS_APPEND,
  115. }, {
  116. .name = "file system(nor)",
  117. .size = MTDPART_SIZ_FULL,
  118. .offset = MTDPART_OFS_APPEND,
  119. }
  120. };
  121. static struct physmap_flash_data ezbrd_flash_data = {
  122. .width = 2,
  123. .parts = ezbrd_partitions,
  124. .nr_parts = ARRAY_SIZE(ezbrd_partitions),
  125. };
  126. static struct resource ezbrd_flash_resource = {
  127. .start = 0x20000000,
  128. .end = 0x203fffff,
  129. .flags = IORESOURCE_MEM,
  130. };
  131. static struct platform_device ezbrd_flash_device = {
  132. .name = "physmap-flash",
  133. .id = 0,
  134. .dev = {
  135. .platform_data = &ezbrd_flash_data,
  136. },
  137. .num_resources = 1,
  138. .resource = &ezbrd_flash_resource,
  139. };
  140. #endif
  141. #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
  142. static struct mtd_partition partition_info[] = {
  143. {
  144. .name = "linux kernel(nand)",
  145. .offset = 0,
  146. .size = 4 * 1024 * 1024,
  147. },
  148. {
  149. .name = "file system(nand)",
  150. .offset = MTDPART_OFS_APPEND,
  151. .size = MTDPART_SIZ_FULL,
  152. },
  153. };
  154. static struct bf5xx_nand_platform bf5xx_nand_platform = {
  155. .page_size = NFC_PG_SIZE_256,
  156. .data_width = NFC_NWIDTH_8,
  157. .partitions = partition_info,
  158. .nr_partitions = ARRAY_SIZE(partition_info),
  159. .rd_dly = 3,
  160. .wr_dly = 3,
  161. };
  162. static struct resource bf5xx_nand_resources[] = {
  163. {
  164. .start = NFC_CTL,
  165. .end = NFC_DATA_RD + 2,
  166. .flags = IORESOURCE_MEM,
  167. },
  168. {
  169. .start = CH_NFC,
  170. .end = CH_NFC,
  171. .flags = IORESOURCE_IRQ,
  172. },
  173. };
  174. static struct platform_device bf5xx_nand_device = {
  175. .name = "bf5xx-nand",
  176. .id = 0,
  177. .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
  178. .resource = bf5xx_nand_resources,
  179. .dev = {
  180. .platform_data = &bf5xx_nand_platform,
  181. },
  182. };
  183. #endif
  184. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  185. static struct platform_device rtc_device = {
  186. .name = "rtc-bfin",
  187. .id = -1,
  188. };
  189. #endif
  190. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  191. static struct platform_device bfin_mac_device = {
  192. .name = "bfin_mac",
  193. };
  194. #endif
  195. #if defined(CONFIG_MTD_M25P80) \
  196. || defined(CONFIG_MTD_M25P80_MODULE)
  197. static struct mtd_partition bfin_spi_flash_partitions[] = {
  198. {
  199. .name = "bootloader(spi)",
  200. .size = 0x00040000,
  201. .offset = 0,
  202. .mask_flags = MTD_CAP_ROM
  203. }, {
  204. .name = "linux kernel(spi)",
  205. .size = MTDPART_SIZ_FULL,
  206. .offset = MTDPART_OFS_APPEND,
  207. }
  208. };
  209. static struct flash_platform_data bfin_spi_flash_data = {
  210. .name = "m25p80",
  211. .parts = bfin_spi_flash_partitions,
  212. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  213. .type = "m25p16",
  214. };
  215. /* SPI flash chip (m25p64) */
  216. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  217. .enable_dma = 0, /* use dma transfer with this chip*/
  218. .bits_per_word = 8,
  219. };
  220. #endif
  221. #if defined(CONFIG_SPI_ADC_BF533) \
  222. || defined(CONFIG_SPI_ADC_BF533_MODULE)
  223. /* SPI ADC chip */
  224. static struct bfin5xx_spi_chip spi_adc_chip_info = {
  225. .enable_dma = 1, /* use dma transfer with this chip*/
  226. .bits_per_word = 16,
  227. };
  228. #endif
  229. #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
  230. static struct bfin5xx_spi_chip spi_mmc_chip_info = {
  231. .enable_dma = 1,
  232. .bits_per_word = 8,
  233. };
  234. #endif
  235. #if defined(CONFIG_PBX)
  236. static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
  237. .ctl_reg = 0x4, /* send zero */
  238. .enable_dma = 0,
  239. .bits_per_word = 8,
  240. .cs_change_per_word = 1,
  241. };
  242. #endif
  243. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  244. static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
  245. .enable_dma = 0,
  246. .bits_per_word = 16,
  247. };
  248. static const struct ad7877_platform_data bfin_ad7877_ts_info = {
  249. .model = 7877,
  250. .vref_delay_usecs = 50, /* internal, no capacitor */
  251. .x_plate_ohms = 419,
  252. .y_plate_ohms = 486,
  253. .pressure_max = 1000,
  254. .pressure_min = 0,
  255. .stopacq_polarity = 1,
  256. .first_conversion_delay = 3,
  257. .acquisition_time = 1,
  258. .averaging = 1,
  259. .pen_down_acc_interval = 1,
  260. };
  261. #endif
  262. #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
  263. && defined(CONFIG_SND_SOC_WM8731_SPI)
  264. static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
  265. .enable_dma = 0,
  266. .bits_per_word = 16,
  267. };
  268. #endif
  269. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  270. static struct bfin5xx_spi_chip spidev_chip_info = {
  271. .enable_dma = 0,
  272. .bits_per_word = 8,
  273. };
  274. #endif
  275. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  276. static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
  277. .enable_dma = 0,
  278. .bits_per_word = 8,
  279. };
  280. #endif
  281. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  282. #if defined(CONFIG_MTD_M25P80) \
  283. || defined(CONFIG_MTD_M25P80_MODULE)
  284. {
  285. /* the modalias must be the same as spi device driver name */
  286. .modalias = "m25p80", /* Name of spi_driver for this device */
  287. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  288. .bus_num = 0, /* Framework bus number */
  289. .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
  290. .platform_data = &bfin_spi_flash_data,
  291. .controller_data = &spi_flash_chip_info,
  292. .mode = SPI_MODE_3,
  293. },
  294. #endif
  295. #if defined(CONFIG_SPI_ADC_BF533) \
  296. || defined(CONFIG_SPI_ADC_BF533_MODULE)
  297. {
  298. .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
  299. .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
  300. .bus_num = 0, /* Framework bus number */
  301. .chip_select = 1, /* Framework chip select. */
  302. .platform_data = NULL, /* No spi_driver specific config */
  303. .controller_data = &spi_adc_chip_info,
  304. },
  305. #endif
  306. #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
  307. {
  308. .modalias = "spi_mmc_dummy",
  309. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  310. .bus_num = 0,
  311. .chip_select = 0,
  312. .platform_data = NULL,
  313. .controller_data = &spi_mmc_chip_info,
  314. .mode = SPI_MODE_3,
  315. },
  316. {
  317. .modalias = "spi_mmc",
  318. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  319. .bus_num = 0,
  320. .chip_select = CONFIG_SPI_MMC_CS_CHAN,
  321. .platform_data = NULL,
  322. .controller_data = &spi_mmc_chip_info,
  323. .mode = SPI_MODE_3,
  324. },
  325. #endif
  326. #if defined(CONFIG_PBX)
  327. {
  328. .modalias = "fxs-spi",
  329. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  330. .bus_num = 0,
  331. .chip_select = 8 - CONFIG_J11_JUMPER,
  332. .controller_data = &spi_si3xxx_chip_info,
  333. .mode = SPI_MODE_3,
  334. },
  335. {
  336. .modalias = "fxo-spi",
  337. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  338. .bus_num = 0,
  339. .chip_select = 8 - CONFIG_J19_JUMPER,
  340. .controller_data = &spi_si3xxx_chip_info,
  341. .mode = SPI_MODE_3,
  342. },
  343. #endif
  344. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  345. {
  346. .modalias = "ad7877",
  347. .platform_data = &bfin_ad7877_ts_info,
  348. .irq = IRQ_PF8,
  349. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  350. .bus_num = 0,
  351. .chip_select = 2,
  352. .controller_data = &spi_ad7877_chip_info,
  353. },
  354. #endif
  355. #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
  356. && defined(CONFIG_SND_SOC_WM8731_SPI)
  357. {
  358. .modalias = "wm8731",
  359. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  360. .bus_num = 0,
  361. .chip_select = 5,
  362. .controller_data = &spi_wm8731_chip_info,
  363. .mode = SPI_MODE_0,
  364. },
  365. #endif
  366. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  367. {
  368. .modalias = "spidev",
  369. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  370. .bus_num = 0,
  371. .chip_select = 1,
  372. .controller_data = &spidev_chip_info,
  373. },
  374. #endif
  375. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  376. {
  377. .modalias = "bfin-lq035q1-spi",
  378. .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
  379. .bus_num = 0,
  380. .chip_select = 1,
  381. .controller_data = &lq035q1_spi_chip_info,
  382. .mode = SPI_CPHA | SPI_CPOL,
  383. },
  384. #endif
  385. };
  386. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  387. /* SPI controller data */
  388. static struct bfin5xx_spi_master bfin_spi0_info = {
  389. .num_chipselect = 8,
  390. .enable_dma = 1, /* master has the ability to do dma transfer */
  391. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  392. };
  393. /* SPI (0) */
  394. static struct resource bfin_spi0_resource[] = {
  395. [0] = {
  396. .start = SPI0_REGBASE,
  397. .end = SPI0_REGBASE + 0xFF,
  398. .flags = IORESOURCE_MEM,
  399. },
  400. [1] = {
  401. .start = CH_SPI,
  402. .end = CH_SPI,
  403. .flags = IORESOURCE_IRQ,
  404. },
  405. };
  406. static struct platform_device bfin_spi0_device = {
  407. .name = "bfin-spi",
  408. .id = 0, /* Bus number */
  409. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  410. .resource = bfin_spi0_resource,
  411. .dev = {
  412. .platform_data = &bfin_spi0_info, /* Passed to driver */
  413. },
  414. };
  415. #endif /* spi master and devices */
  416. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  417. static struct resource bfin_uart_resources[] = {
  418. #ifdef CONFIG_SERIAL_BFIN_UART0
  419. {
  420. .start = 0xFFC00400,
  421. .end = 0xFFC004FF,
  422. .flags = IORESOURCE_MEM,
  423. },
  424. #endif
  425. #ifdef CONFIG_SERIAL_BFIN_UART1
  426. {
  427. .start = 0xFFC02000,
  428. .end = 0xFFC020FF,
  429. .flags = IORESOURCE_MEM,
  430. },
  431. #endif
  432. };
  433. static struct platform_device bfin_uart_device = {
  434. .name = "bfin-uart",
  435. .id = 1,
  436. .num_resources = ARRAY_SIZE(bfin_uart_resources),
  437. .resource = bfin_uart_resources,
  438. };
  439. #endif
  440. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  441. static struct resource bfin_sir_resources[] = {
  442. #ifdef CONFIG_BFIN_SIR0
  443. {
  444. .start = 0xFFC00400,
  445. .end = 0xFFC004FF,
  446. .flags = IORESOURCE_MEM,
  447. },
  448. #endif
  449. #ifdef CONFIG_BFIN_SIR1
  450. {
  451. .start = 0xFFC02000,
  452. .end = 0xFFC020FF,
  453. .flags = IORESOURCE_MEM,
  454. },
  455. #endif
  456. };
  457. static struct platform_device bfin_sir_device = {
  458. .name = "bfin_sir",
  459. .id = 0,
  460. .num_resources = ARRAY_SIZE(bfin_sir_resources),
  461. .resource = bfin_sir_resources,
  462. };
  463. #endif
  464. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  465. static struct resource bfin_twi0_resource[] = {
  466. [0] = {
  467. .start = TWI0_REGBASE,
  468. .end = TWI0_REGBASE,
  469. .flags = IORESOURCE_MEM,
  470. },
  471. [1] = {
  472. .start = IRQ_TWI,
  473. .end = IRQ_TWI,
  474. .flags = IORESOURCE_IRQ,
  475. },
  476. };
  477. static struct platform_device i2c_bfin_twi_device = {
  478. .name = "i2c-bfin-twi",
  479. .id = 0,
  480. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  481. .resource = bfin_twi0_resource,
  482. };
  483. #endif
  484. #ifdef CONFIG_I2C_BOARDINFO
  485. static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
  486. #if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
  487. {
  488. I2C_BOARD_INFO("pcf8574_lcd", 0x22),
  489. },
  490. #endif
  491. #if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE)
  492. {
  493. I2C_BOARD_INFO("pcf8574_keypad", 0x27),
  494. .irq = IRQ_PF8,
  495. },
  496. #endif
  497. };
  498. #endif
  499. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  500. static struct platform_device bfin_sport0_uart_device = {
  501. .name = "bfin-sport-uart",
  502. .id = 0,
  503. };
  504. static struct platform_device bfin_sport1_uart_device = {
  505. .name = "bfin-sport-uart",
  506. .id = 1,
  507. };
  508. #endif
  509. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  510. #include <linux/input.h>
  511. #include <linux/gpio_keys.h>
  512. static struct gpio_keys_button bfin_gpio_keys_table[] = {
  513. {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
  514. {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
  515. };
  516. static struct gpio_keys_platform_data bfin_gpio_keys_data = {
  517. .buttons = bfin_gpio_keys_table,
  518. .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
  519. };
  520. static struct platform_device bfin_device_gpiokeys = {
  521. .name = "gpio-keys",
  522. .dev = {
  523. .platform_data = &bfin_gpio_keys_data,
  524. },
  525. };
  526. #endif
  527. static struct resource bfin_gpios_resources = {
  528. .start = 0,
  529. .end = MAX_BLACKFIN_GPIOS - 1,
  530. .flags = IORESOURCE_IRQ,
  531. };
  532. static struct platform_device bfin_gpios_device = {
  533. .name = "simple-gpio",
  534. .id = -1,
  535. .num_resources = 1,
  536. .resource = &bfin_gpios_resources,
  537. };
  538. static const unsigned int cclk_vlev_datasheet[] =
  539. {
  540. VRPAIR(VLEV_100, 400000000),
  541. VRPAIR(VLEV_105, 426000000),
  542. VRPAIR(VLEV_110, 500000000),
  543. VRPAIR(VLEV_115, 533000000),
  544. VRPAIR(VLEV_120, 600000000),
  545. };
  546. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  547. .tuple_tab = cclk_vlev_datasheet,
  548. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  549. .vr_settling_time = 25 /* us */,
  550. };
  551. static struct platform_device bfin_dpmc = {
  552. .name = "bfin dpmc",
  553. .dev = {
  554. .platform_data = &bfin_dmpc_vreg_data,
  555. },
  556. };
  557. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  558. #include <asm/bfin-lq035q1.h>
  559. static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
  560. .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
  561. .use_bl = 1,
  562. .gpio_bl = GPIO_PG12,
  563. };
  564. static struct resource bfin_lq035q1_resources[] = {
  565. {
  566. .start = IRQ_PPI_ERROR,
  567. .end = IRQ_PPI_ERROR,
  568. .flags = IORESOURCE_IRQ,
  569. },
  570. };
  571. static struct platform_device bfin_lq035q1_device = {
  572. .name = "bfin-lq035q1",
  573. .id = -1,
  574. .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
  575. .resource = bfin_lq035q1_resources,
  576. .dev = {
  577. .platform_data = &bfin_lq035q1_data,
  578. },
  579. };
  580. #endif
  581. static struct platform_device *stamp_devices[] __initdata = {
  582. &bfin_dpmc,
  583. #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
  584. &bf5xx_nand_device,
  585. #endif
  586. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  587. &rtc_device,
  588. #endif
  589. #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
  590. &musb_device,
  591. #endif
  592. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  593. &bfin_mac_device,
  594. #endif
  595. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  596. &bfin_spi0_device,
  597. #endif
  598. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  599. &bfin_uart_device,
  600. #endif
  601. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  602. &bfin_lq035q1_device,
  603. #endif
  604. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  605. &bfin_sir_device,
  606. #endif
  607. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  608. &i2c_bfin_twi_device,
  609. #endif
  610. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  611. &bfin_sport0_uart_device,
  612. &bfin_sport1_uart_device,
  613. #endif
  614. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  615. &bfin_device_gpiokeys,
  616. #endif
  617. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  618. &ezbrd_flash_device,
  619. #endif
  620. &bfin_gpios_device,
  621. };
  622. static int __init stamp_init(void)
  623. {
  624. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  625. #ifdef CONFIG_I2C_BOARDINFO
  626. i2c_register_board_info(0, bfin_i2c_board_info,
  627. ARRAY_SIZE(bfin_i2c_board_info));
  628. #endif
  629. platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
  630. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  631. return 0;
  632. }
  633. arch_initcall(stamp_init);
  634. void native_machine_restart(char *cmd)
  635. {
  636. /* workaround reboot hang when booting from SPI */
  637. if ((bfin_read_SYSCR() & 0x7) == 0x3)
  638. bfin_gpio_reset_spi0_ssel1();
  639. }
  640. void bfin_get_ether_addr(char *addr)
  641. {
  642. /* the MAC is stored in OTP memory page 0xDF */
  643. u32 ret;
  644. u64 otp_mac;
  645. u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
  646. ret = otp_read(0xDF, 0x00, &otp_mac);
  647. if (!(ret & 0x1)) {
  648. char *otp_mac_p = (char *)&otp_mac;
  649. for (ret = 0; ret < 6; ++ret)
  650. addr[ret] = otp_mac_p[5 - ret];
  651. }
  652. }
  653. EXPORT_SYMBOL(bfin_get_ether_addr);