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arch
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blackfin
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mach-bf518
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include
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mach
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dma.h

dma.h 1.9 KB
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  1. /*
    2. 

  2.  * file:        include/asm-blackfin/mach-bf518/dma.h
    3. 

  3.  * based on:	include/asm-blackfin/mach-bf527/dma.h
    4. 

  4.  * author:	Michael Hennerich (michael.hennerich@analog.com)
    5. 

  5.  *
    6. 

  6.  * created:
    7. 

  7.  * description:
    8. 

  8.  *	system DMA map
    9. 

  9.  * rev:
    10. 

  10.  *
    11. 

  11.  * modified:
    12. 

  12.  *
    13. 

  13.  *
    14. 

  14.  * bugs:         enter bugs at http://blackfin.uclinux.org/
    15. 

  15.  *
    16. 

  16.  * this program is free software; you can redistribute it and/or modify
    17. 

  17.  * it under the terms of the gnu general public license as published by
    18. 

  18.  * the free software foundation; either version 2, or (at your option)
    19. 

  19.  * any later version.
    20. 

  20.  *
    21. 

  21.  * this program is distributed in the hope that it will be useful,
    22. 

  22.  * but without any warranty; without even the implied warranty of
    23. 

  23.  * merchantability or fitness for a particular purpose.  see the
    24. 

  24.  * gnu general public license for more details.
    25. 

  25.  *
    26. 

  26.  * you should have received a copy of the gnu general public license
    27. 

  27.  * along with this program; see the file copying.
    28. 

  28.  * if not, write to the free software foundation,
    29. 

  29.  * 59 temple place - suite 330, boston, ma 02111-1307, usa.
    30. 

  30.  */
    31. 

  31. 

  32. #ifndef _MACH_DMA_H_
    33. 

  33. #define _MACH_DMA_H_
    34. 

  34. 

  35. #define MAX_BLACKFIN_DMA_CHANNEL 16
    36. 

  36. 

  37. #define CH_PPI 			0	/* PPI receive/transmit */
    38. 

  38. #define CH_EMAC_RX 		1	/* Ethernet MAC receive */
    39. 

  39. #define CH_EMAC_TX 		2	/* Ethernet MAC transmit */
    40. 

  40. #define CH_SPORT0_RX 		3	/* SPORT0 receive */
    41. 

  41. #define CH_SPORT0_TX 		4	/* SPORT0 transmit */
    42. 

  42. #define CH_RSI 			4	/* RSI */
    43. 

  43. #define CH_SPORT1_RX 		5	/* SPORT1 receive */
    44. 

  44. #define CH_SPI1 		5	/* SPI1 transmit/receive */
    45. 

  45. #define CH_SPORT1_TX 		6	/* SPORT1 transmit */
    46. 

  46. #define CH_SPI0 		7	/* SPI0 transmit/receive */
    47. 

  47. #define CH_UART0_RX 		8	/* UART0 receive */
    48. 

  48. #define CH_UART0_TX 		9	/* UART0 transmit */
    49. 

  49. #define CH_UART1_RX 		10	/* UART1 receive */
    50. 

  50. #define CH_UART1_TX 		11	/* UART1 transmit */
    51. 

  51. 

  52. #define CH_MEM_STREAM0_SRC 	12	/* RX */
    53. 

  53. #define CH_MEM_STREAM0_DEST	13	/* TX */
    54. 

  54. #define CH_MEM_STREAM1_SRC 	14	/* RX */
    55. 

  55. #define CH_MEM_STREAM1_DEST	15	/* TX */
    56. 

  56. 

  57. #endif
    58.