cplbmgr.S 16 KB

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  1. /*
  2. * File: arch/blackfin/mach-common/cplbmgtr.S
  3. * Based on:
  4. * Author: LG Soft India
  5. *
  6. * Created: ?
  7. * Description: CPLB replacement routine for CPLB mismatch
  8. *
  9. * Modified:
  10. * Copyright 2004-2006 Analog Devices Inc.
  11. *
  12. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, see the file COPYING, or write
  26. * to the Free Software Foundation, Inc.,
  27. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  28. */
  29. /* Usage: int _cplb_mgr(is_data_miss,int enable_cache)
  30. * is_data_miss==2 => Mark as Dirty, write to the clean data page
  31. * is_data_miss==1 => Replace a data CPLB.
  32. * is_data_miss==0 => Replace an instruction CPLB.
  33. *
  34. * Returns:
  35. * CPLB_RELOADED => Successfully updated CPLB table.
  36. * CPLB_NO_UNLOCKED => All CPLBs are locked, so cannot be evicted.
  37. * This indicates that the CPLBs in the configuration
  38. * tablei are badly configured, as this should never
  39. * occur.
  40. * CPLB_NO_ADDR_MATCH => The address being accessed, that triggered the
  41. * exception, is not covered by any of the CPLBs in
  42. * the configuration table. The application is
  43. * presumably misbehaving.
  44. * CPLB_PROT_VIOL => The address being accessed, that triggered the
  45. * exception, was not a first-write to a clean Write
  46. * Back Data page, and so presumably is a genuine
  47. * violation of the page's protection attributes.
  48. * The application is misbehaving.
  49. */
  50. #include <linux/linkage.h>
  51. #include <asm/blackfin.h>
  52. #include <asm/cplb.h>
  53. #include <asm/asm-offsets.h>
  54. #ifdef CONFIG_EXCPT_IRQ_SYSC_L1
  55. .section .l1.text
  56. #else
  57. .text
  58. #endif
  59. .align 2;
  60. ENTRY(_cplb_mgr)
  61. [--SP]=( R7:4,P5:3 );
  62. CC = R0 == 2;
  63. IF CC JUMP .Ldcplb_write;
  64. CC = R0 == 0;
  65. IF !CC JUMP .Ldcplb_miss_compare;
  66. /* ICPLB Miss Exception. We need to choose one of the
  67. * currently-installed CPLBs, and replace it with one
  68. * from the configuration table.
  69. */
  70. /* A multi-word instruction can cross a page boundary. This means the
  71. * first part of the instruction can be in a valid page, but the
  72. * second part is not, and hence generates the instruction miss.
  73. * However, the fault address is for the start of the instruction,
  74. * not the part that's in the bad page. Therefore, we have to check
  75. * whether the fault address applies to a page that is already present
  76. * in the table.
  77. */
  78. P4.L = LO(ICPLB_FAULT_ADDR);
  79. P4.H = HI(ICPLB_FAULT_ADDR);
  80. P1 = 16;
  81. P5.L = _page_size_table;
  82. P5.H = _page_size_table;
  83. P0.L = LO(ICPLB_DATA0);
  84. P0.H = HI(ICPLB_DATA0);
  85. R4 = [P4]; /* Get faulting address*/
  86. R6 = 64; /* Advance past the fault address, which*/
  87. R6 = R6 + R4; /* we'll use if we find a match*/
  88. R3 = ((16 << 8) | 2); /* Extract mask, two bits at posn 16 */
  89. R5 = 0;
  90. .Lisearch:
  91. R1 = [P0-0x100]; /* Address for this CPLB */
  92. R0 = [P0++]; /* Info for this CPLB*/
  93. CC = BITTST(R0,0); /* Is the CPLB valid?*/
  94. IF !CC JUMP .Lnomatch; /* Skip it, if not.*/
  95. CC = R4 < R1(IU); /* If fault address less than page start*/
  96. IF CC JUMP .Lnomatch; /* then skip this one.*/
  97. R2 = EXTRACT(R0,R3.L) (Z); /* Get page size*/
  98. P1 = R2;
  99. P1 = P5 + (P1<<2); /* index into page-size table*/
  100. R2 = [P1]; /* Get the page size*/
  101. R1 = R1 + R2; /* and add to page start, to get page end*/
  102. CC = R4 < R1(IU); /* and see whether fault addr is in page.*/
  103. IF !CC R4 = R6; /* If so, advance the address and finish loop.*/
  104. IF !CC JUMP .Lisearch_done;
  105. .Lnomatch:
  106. /* Go around again*/
  107. R5 += 1;
  108. CC = BITTST(R5, 4); /* i.e CC = R5 >= 16*/
  109. IF !CC JUMP .Lisearch;
  110. .Lisearch_done:
  111. I0 = R4; /* Fault address we'll search for*/
  112. /* set up pointers */
  113. P0.L = LO(ICPLB_DATA0);
  114. P0.H = HI(ICPLB_DATA0);
  115. /* The replacement procedure for ICPLBs */
  116. P4.L = LO(IMEM_CONTROL);
  117. P4.H = HI(IMEM_CONTROL);
  118. /* Turn off CPLBs while we work, necessary according to HRM before
  119. * modifying CPLB descriptors
  120. */
  121. R5 = [P4]; /* Control Register*/
  122. BITCLR(R5,ENICPLB_P);
  123. CLI R1;
  124. SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
  125. .align 8;
  126. [P4] = R5;
  127. SSYNC;
  128. STI R1;
  129. R1 = -1; /* end point comparison */
  130. R3 = 16; /* counter */
  131. /* Search through CPLBs for first non-locked entry */
  132. /* Overwrite it by moving everyone else up by 1 */
  133. .Licheck_lock:
  134. R0 = [P0++];
  135. R3 = R3 + R1;
  136. CC = R3 == R1;
  137. IF CC JUMP .Lall_locked;
  138. CC = BITTST(R0, 0); /* an invalid entry is good */
  139. IF !CC JUMP .Lifound_victim;
  140. CC = BITTST(R0,1); /* but a locked entry isn't */
  141. IF CC JUMP .Licheck_lock;
  142. .Lifound_victim:
  143. #ifdef CONFIG_CPLB_INFO
  144. R7 = [P0 - 0x104];
  145. GET_PDA(P2, R2);
  146. P3 = [P2 + PDA_IPDT_SWAPCOUNT];
  147. P2 = [P2 + PDA_IPDT];
  148. P3 += -4;
  149. .Licount:
  150. R2 = [P2]; /* address from config table */
  151. P2 += 8;
  152. P3 += 8;
  153. CC = R2==-1;
  154. IF CC JUMP .Licount_done;
  155. CC = R7==R2;
  156. IF !CC JUMP .Licount;
  157. R7 = [P3];
  158. R7 += 1;
  159. [P3] = R7;
  160. CSYNC;
  161. .Licount_done:
  162. #endif
  163. LC0=R3;
  164. LSETUP(.Lis_move,.Lie_move) LC0;
  165. .Lis_move:
  166. R0 = [P0];
  167. [P0 - 4] = R0;
  168. R0 = [P0 - 0x100];
  169. [P0-0x104] = R0;
  170. .Lie_move:
  171. P0+=4;
  172. /* Clear ICPLB_DATA15, in case we don't find a replacement
  173. * otherwise, we would have a duplicate entry, and will crash
  174. */
  175. R0 = 0;
  176. [P0 - 4] = R0;
  177. /* We've made space in the ICPLB table, so that ICPLB15
  178. * is now free to be overwritten. Next, we have to determine
  179. * which CPLB we need to install, from the configuration
  180. * table. This is a matter of getting the start-of-page
  181. * addresses and page-lengths from the config table, and
  182. * determining whether the fault address falls within that
  183. * range.
  184. */
  185. GET_PDA(P3, R0);
  186. P2 = [P3 + PDA_IPDT];
  187. #ifdef CONFIG_CPLB_INFO
  188. P3 = [P3 + PDA_IPDT_SWAPCOUNT];
  189. P3 += -8;
  190. #endif
  191. P0.L = _page_size_table;
  192. P0.H = _page_size_table;
  193. /* Retrieve our fault address (which may have been advanced
  194. * because the faulting instruction crossed a page boundary).
  195. */
  196. R0 = I0;
  197. /* An extraction pattern, to get the page-size bits from
  198. * the CPLB data entry. Bits 16-17, so two bits at posn 16.
  199. */
  200. R1 = ((16<<8)|2);
  201. .Linext: R4 = [P2++]; /* address from config table */
  202. R2 = [P2++]; /* data from config table */
  203. #ifdef CONFIG_CPLB_INFO
  204. P3 += 8;
  205. #endif
  206. CC = R4 == -1; /* End of config table*/
  207. IF CC JUMP .Lno_page_in_table;
  208. /* See if failed address > start address */
  209. CC = R4 <= R0(IU);
  210. IF !CC JUMP .Linext;
  211. /* extract page size (17:16)*/
  212. R3 = EXTRACT(R2, R1.L) (Z);
  213. /* add page size to addr to get range */
  214. P5 = R3;
  215. P5 = P0 + (P5 << 2); /* scaled, for int access*/
  216. R3 = [P5];
  217. R3 = R3 + R4;
  218. /* See if failed address < (start address + page size) */
  219. CC = R0 < R3(IU);
  220. IF !CC JUMP .Linext;
  221. /* We've found a CPLB in the config table that covers
  222. * the faulting address, so install this CPLB into the
  223. * last entry of the table.
  224. */
  225. P1.L = LO(ICPLB_DATA15); /* ICPLB_DATA15 */
  226. P1.H = HI(ICPLB_DATA15);
  227. [P1] = R2;
  228. [P1-0x100] = R4;
  229. #ifdef CONFIG_CPLB_INFO
  230. R3 = [P3];
  231. R3 += 1;
  232. [P3] = R3;
  233. #endif
  234. /* P4 points to IMEM_CONTROL, and R5 contains its old
  235. * value, after we disabled ICPLBS. Re-enable them.
  236. */
  237. BITSET(R5,ENICPLB_P);
  238. CLI R2;
  239. SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
  240. .align 8;
  241. [P4] = R5;
  242. SSYNC;
  243. STI R2;
  244. ( R7:4,P5:3 ) = [SP++];
  245. R0 = CPLB_RELOADED;
  246. RTS;
  247. /* FAILED CASES*/
  248. .Lno_page_in_table:
  249. R0 = CPLB_NO_ADDR_MATCH;
  250. JUMP .Lfail_ret;
  251. .Lall_locked:
  252. R0 = CPLB_NO_UNLOCKED;
  253. JUMP .Lfail_ret;
  254. .Lprot_violation:
  255. R0 = CPLB_PROT_VIOL;
  256. .Lfail_ret:
  257. /* Make sure we turn protection/cache back on, even in the failing case */
  258. BITSET(R5,ENICPLB_P);
  259. CLI R2;
  260. SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
  261. .align 8;
  262. [P4] = R5;
  263. SSYNC;
  264. STI R2;
  265. ( R7:4,P5:3 ) = [SP++];
  266. RTS;
  267. .Ldcplb_write:
  268. /* if a DCPLB is marked as write-back (CPLB_WT==0), and
  269. * it is clean (CPLB_DIRTY==0), then a write to the
  270. * CPLB's page triggers a protection violation. We have to
  271. * mark the CPLB as dirty, to indicate that there are
  272. * pending writes associated with the CPLB.
  273. */
  274. P4.L = LO(DCPLB_STATUS);
  275. P4.H = HI(DCPLB_STATUS);
  276. P3.L = LO(DCPLB_DATA0);
  277. P3.H = HI(DCPLB_DATA0);
  278. R5 = [P4];
  279. /* A protection violation can be caused by more than just writes
  280. * to a clean WB page, so we have to ensure that:
  281. * - It's a write
  282. * - to a clean WB page
  283. * - and is allowed in the mode the access occurred.
  284. */
  285. CC = BITTST(R5, 16); /* ensure it was a write*/
  286. IF !CC JUMP .Lprot_violation;
  287. /* to check the rest, we have to retrieve the DCPLB.*/
  288. /* The low half of DCPLB_STATUS is a bit mask*/
  289. R2 = R5.L (Z); /* indicating which CPLB triggered the event.*/
  290. R3 = 30; /* so we can use this to determine the offset*/
  291. R2.L = SIGNBITS R2;
  292. R2 = R2.L (Z); /* into the DCPLB table.*/
  293. R3 = R3 - R2;
  294. P4 = R3;
  295. P3 = P3 + (P4<<2);
  296. R3 = [P3]; /* Retrieve the CPLB*/
  297. /* Now we can check whether it's a clean WB page*/
  298. CC = BITTST(R3, 14); /* 0==WB, 1==WT*/
  299. IF CC JUMP .Lprot_violation;
  300. CC = BITTST(R3, 7); /* 0 == clean, 1 == dirty*/
  301. IF CC JUMP .Lprot_violation;
  302. /* Check whether the write is allowed in the mode that was active.*/
  303. R2 = 1<<3; /* checking write in user mode*/
  304. CC = BITTST(R5, 17); /* 0==was user, 1==was super*/
  305. R5 = CC;
  306. R2 <<= R5; /* if was super, check write in super mode*/
  307. R2 = R3 & R2;
  308. CC = R2 == 0;
  309. IF CC JUMP .Lprot_violation;
  310. /* It's a genuine write-to-clean-page.*/
  311. BITSET(R3, 7); /* mark as dirty*/
  312. [P3] = R3; /* and write back.*/
  313. NOP;
  314. CSYNC;
  315. ( R7:4,P5:3 ) = [SP++];
  316. R0 = CPLB_RELOADED;
  317. RTS;
  318. .Ldcplb_miss_compare:
  319. /* Data CPLB Miss event. We need to choose a CPLB to
  320. * evict, and then locate a new CPLB to install from the
  321. * config table, that covers the faulting address.
  322. */
  323. P1.L = LO(DCPLB_DATA15);
  324. P1.H = HI(DCPLB_DATA15);
  325. P4.L = LO(DCPLB_FAULT_ADDR);
  326. P4.H = HI(DCPLB_FAULT_ADDR);
  327. R4 = [P4];
  328. I0 = R4;
  329. /* The replacement procedure for DCPLBs*/
  330. R6 = R1; /* Save for later*/
  331. /* Turn off CPLBs while we work.*/
  332. P4.L = LO(DMEM_CONTROL);
  333. P4.H = HI(DMEM_CONTROL);
  334. R5 = [P4];
  335. BITCLR(R5,ENDCPLB_P);
  336. CLI R0;
  337. SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
  338. .align 8;
  339. [P4] = R5;
  340. SSYNC;
  341. STI R0;
  342. /* Start looking for a CPLB to evict. Our order of preference
  343. * is: invalid CPLBs, clean CPLBs, dirty CPLBs. Locked CPLBs
  344. * are no good.
  345. */
  346. I1.L = LO(DCPLB_DATA0);
  347. I1.H = HI(DCPLB_DATA0);
  348. P1 = 2;
  349. P2 = 16;
  350. I2.L = _dcplb_preference;
  351. I2.H = _dcplb_preference;
  352. LSETUP(.Lsdsearch1, .Ledsearch1) LC0 = P1;
  353. .Lsdsearch1:
  354. R0 = [I2++]; /* Get the bits we're interested in*/
  355. P0 = I1; /* Go back to start of table*/
  356. LSETUP (.Lsdsearch2, .Ledsearch2) LC1 = P2;
  357. .Lsdsearch2:
  358. R1 = [P0++]; /* Fetch each installed CPLB in turn*/
  359. R2 = R1 & R0; /* and test for interesting bits.*/
  360. CC = R2 == 0; /* If none are set, it'll do.*/
  361. IF !CC JUMP .Lskip_stack_check;
  362. R2 = [P0 - 0x104]; /* R2 - PageStart */
  363. P3.L = _page_size_table; /* retrieve end address */
  364. P3.H = _page_size_table; /* retrieve end address */
  365. R3 = 0x1002; /* 16th - position, 2 bits -length */
  366. #if ANOMALY_05000209
  367. nop; /* Anomaly 05000209 */
  368. #endif
  369. R7 = EXTRACT(R1,R3.l);
  370. R7 = R7 << 2; /* Page size index offset */
  371. P5 = R7;
  372. P3 = P3 + P5;
  373. R7 = [P3]; /* page size in bytes */
  374. R7 = R2 + R7; /* R7 - PageEnd */
  375. R4 = SP; /* Test SP is in range */
  376. CC = R7 < R4; /* if PageEnd < SP */
  377. IF CC JUMP .Ldfound_victim;
  378. R3 = 0x284; /* stack length from start of trap till
  379. * the point.
  380. * 20 stack locations for future modifications
  381. */
  382. R4 = R4 + R3;
  383. CC = R4 < R2; /* if SP + stacklen < PageStart */
  384. IF CC JUMP .Ldfound_victim;
  385. .Lskip_stack_check:
  386. .Ledsearch2: NOP;
  387. .Ledsearch1: NOP;
  388. /* If we got here, we didn't find a DCPLB we considered
  389. * replacable, which means all of them were locked.
  390. */
  391. JUMP .Lall_locked;
  392. .Ldfound_victim:
  393. #ifdef CONFIG_CPLB_INFO
  394. R7 = [P0 - 0x104];
  395. GET_PDA(P2, R2);
  396. P3 = [P2 + PDA_DPDT_SWAPCOUNT];
  397. P2 = [P2 + PDA_DPDT];
  398. P3 += -4;
  399. .Ldicount:
  400. R2 = [P2];
  401. P2 += 8;
  402. P3 += 8;
  403. CC = R2==-1;
  404. IF CC JUMP .Ldicount_done;
  405. CC = R7==R2;
  406. IF !CC JUMP .Ldicount;
  407. R7 = [P3];
  408. R7 += 1;
  409. [P3] = R7;
  410. .Ldicount_done:
  411. #endif
  412. /* Clean down the hardware loops*/
  413. R2 = 0;
  414. LC1 = R2;
  415. LC0 = R2;
  416. /* There's a suitable victim in [P0-4] (because we've
  417. * advanced already).
  418. */
  419. .LDdoverwrite:
  420. /* [P0-4] is a suitable victim CPLB, so we want to
  421. * overwrite it by moving all the following CPLBs
  422. * one space closer to the start.
  423. */
  424. R1.L = LO(DCPLB_DATA16); /* DCPLB_DATA15 + 4 */
  425. R1.H = HI(DCPLB_DATA16);
  426. R0 = P0;
  427. /* If the victim happens to be in DCPLB15,
  428. * we don't need to move anything.
  429. */
  430. CC = R1 == R0;
  431. IF CC JUMP .Lde_moved;
  432. R1 = R1 - R0;
  433. R1 >>= 2;
  434. P1 = R1;
  435. LSETUP(.Lds_move, .Lde_move) LC0=P1;
  436. .Lds_move:
  437. R0 = [P0++]; /* move data */
  438. [P0 - 8] = R0;
  439. R0 = [P0-0x104] /* move address */
  440. .Lde_move:
  441. [P0-0x108] = R0;
  442. .Lde_moved:
  443. NOP;
  444. /* Clear DCPLB_DATA15, in case we don't find a replacement
  445. * otherwise, we would have a duplicate entry, and will crash
  446. */
  447. R0 = 0;
  448. [P0 - 0x4] = R0;
  449. /* We've now made space in DCPLB15 for the new CPLB to be
  450. * installed. The next stage is to locate a CPLB in the
  451. * config table that covers the faulting address.
  452. */
  453. R0 = I0; /* Our faulting address */
  454. GET_PDA(P3, R1);
  455. P2 = [P3 + PDA_DPDT];
  456. #ifdef CONFIG_CPLB_INFO
  457. P3 = [P3 + PDA_DPDT_SWAPCOUNT];
  458. P3 += -8;
  459. #endif
  460. P1.L = _page_size_table;
  461. P1.H = _page_size_table;
  462. /* An extraction pattern, to retrieve bits 17:16.*/
  463. R1 = (16<<8)|2;
  464. .Ldnext: R4 = [P2++]; /* address */
  465. R2 = [P2++]; /* data */
  466. #ifdef CONFIG_CPLB_INFO
  467. P3 += 8;
  468. #endif
  469. CC = R4 == -1;
  470. IF CC JUMP .Lno_page_in_table;
  471. /* See if failed address > start address */
  472. CC = R4 <= R0(IU);
  473. IF !CC JUMP .Ldnext;
  474. /* extract page size (17:16)*/
  475. R3 = EXTRACT(R2, R1.L) (Z);
  476. /* add page size to addr to get range */
  477. P5 = R3;
  478. P5 = P1 + (P5 << 2);
  479. R3 = [P5];
  480. R3 = R3 + R4;
  481. /* See if failed address < (start address + page size) */
  482. CC = R0 < R3(IU);
  483. IF !CC JUMP .Ldnext;
  484. /* We've found the CPLB that should be installed, so
  485. * write it into CPLB15, masking off any caching bits
  486. * if necessary.
  487. */
  488. P1.L = LO(DCPLB_DATA15);
  489. P1.H = HI(DCPLB_DATA15);
  490. /* If the DCPLB has cache bits set, but caching hasn't
  491. * been enabled, then we want to mask off the cache-in-L1
  492. * bit before installing. Moreover, if caching is off, we
  493. * also want to ensure that the DCPLB has WT mode set, rather
  494. * than WB, since WB pages still trigger first-write exceptions
  495. * even when not caching is off, and the page isn't marked as
  496. * cachable. Finally, we could mark the page as clean, not dirty,
  497. * but we choose to leave that decision to the user; if the user
  498. * chooses to have a CPLB pre-defined as dirty, then they always
  499. * pay the cost of flushing during eviction, but don't pay the
  500. * cost of first-write exceptions to mark the page as dirty.
  501. */
  502. #ifdef CONFIG_BFIN_WT
  503. BITSET(R6, 14); /* Set WT*/
  504. #endif
  505. [P1] = R2;
  506. [P1-0x100] = R4;
  507. #ifdef CONFIG_CPLB_INFO
  508. R3 = [P3];
  509. R3 += 1;
  510. [P3] = R3;
  511. #endif
  512. /* We've installed the CPLB, so re-enable CPLBs. P4
  513. * points to DMEM_CONTROL, and R5 is the value we
  514. * last wrote to it, when we were disabling CPLBs.
  515. */
  516. BITSET(R5,ENDCPLB_P);
  517. CLI R2;
  518. .align 8;
  519. [P4] = R5;
  520. SSYNC;
  521. STI R2;
  522. ( R7:4,P5:3 ) = [SP++];
  523. R0 = CPLB_RELOADED;
  524. RTS;
  525. ENDPROC(_cplb_mgr)
  526. #ifdef CONFIG_CPLB_SWITCH_TAB_L1
  527. .section .l1.data
  528. #else
  529. .data
  530. #endif
  531. ENTRY(_page_size_table)
  532. .byte4 0x00000400; /* 1K */
  533. .byte4 0x00001000; /* 4K */
  534. .byte4 0x00100000; /* 1M */
  535. .byte4 0x00400000; /* 4M */
  536. END(_page_size_table)
  537. ENTRY(_dcplb_preference)
  538. .byte4 0x00000001; /* valid bit */
  539. .byte4 0x00000002; /* lock bit */
  540. END(_dcplb_preference)